JPH10222987A - Semiconductor integrated circuit and data processing system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the number of transfer gates to realize high speed operation of a latch circuit by decoding an input signal and forming a slave stage of the master/slave latch with an output transfer gate and output static latch. SOLUTION: A decoder 1 decodes the input signals A0, A1 of two bits to output the decoded signals S0 to S3 of four bits. The master/slave latch 2 has the master stage in the input side of the decoder 1 and has the input transfer gates 20, 21 and input static latches 30, 31 for each input signals A0, A1 of two bits of the decoder 1. The slave stage is provided with the output transfer gates 40 to 43 and output static latches 50 to 53 for each output signal S0 to S3 of four bits of the decoder 1. The number of the input transfer gates 20, 21 forming the master stage is equal to the 2-bit signal same as the input signals A0, A1 of two bits and reduces a load of the clock signal CLK.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a latch circuit with a decoding function formed on a semiconductor substrate by combining a decoder and a master / slave latch. Further, a semiconductor memory device including the latch circuit with the decode function,
Further, the present invention relates to a data processing system in which the semiconductor storage device is applied to a cache memory. The present invention relates to a technology effective when applied to, for example, a synchronous SRAM or a pipeline burst SRAM.

[0002]

2. Description of the Related Art A clock synchronous semiconductor memory device such as a synchronous SRAM or a pipeline burst SRAM includes an address input latch circuit for latching an externally supplied address signal and a decode latch circuit for latching a decode output of an address decoder. Has a pipeline latch circuit such as a data output latch circuit for latching data read from a memory cell selected by the output of the decode latch circuit, and performs a memory operation by synchronizing the pipeline latch circuits with a clock signal. It has become. When access to such a clock-synchronous semiconductor memory device is continuous, after the first data is read, read data can be obtained every latch operation of the pipeline latch circuit. That is, similarly to the pipeline operation of the microprocessor, data can be output to the outside so that the pipeline is ticked in clock signal cycle units (in latch operation cycle units of the latch circuit). Such a clock-synchronous semiconductor memory device contributes to speeding up memory access in applications where memory access is continuous.

As the above-mentioned pipeline latch circuit, a master-slave type latch is usually used. This latch is well known. For example, a master stage and a slave stage each having a CMOS transfer gate and a static latch are connected in series, and the CMOS transfer gate of the master stage and the CMOS transfer gate of the slave stage change the clock signal. Switch control is carried out in reverse phase based on this.

[0004]

The inventor has studied a latch circuit that receives the output of a decoder. When latching the output of the decoder, a number of the latches equal to the number of bits of the decoded output are arranged in parallel. A common clock signal is used to control the latch operation of the latches arranged in parallel.

However, as the number of latches arranged in parallel increases, the input gate capacitance component of the control terminal of the CMOS transfer gate increases as a whole. As a result, the present inventor has clarified that the load of the clock signal increases and the operating frequency of the clock signal cannot be increased to shorten the latch operation cycle. In the case of the above-mentioned clock synchronous type semiconductor memory device, as the number of bits of the address signal increases, the scale of the decode latch circuit increases, and the load of the clock signal increases. Would.

An object of the present invention is to provide a latch circuit with a decode function which can reduce the load of a clock signal for latching a decode output in a master-slave format.

Another object of the present invention is to provide a semiconductor memory device capable of improving an access speed of clock synchronization.

Another object of the present invention is to provide a data processing system capable of contributing to an increase in data processing speed accompanying a memory access operation in terms of a high speed operation of a cache memory.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0010]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

That is, the semiconductor integrated circuit decodes an ^n- bit input signal to generate a 2 ⁿ -bit output signal, an input transfer gate for supplying the input signal to the decoder, and each input transfer gate. An input static latch which latches the input signal supplied from the decoder and supplies it to the decoder, an output transfer gate which passes each output signal of the decoder in a phase opposite to that of the input transfer gate, and an output of each output transfer gate And a latch circuit with a decode function having an output static latch for latching the latch circuit.

The input transfer gate and the input static latch constitute a master stage of a master-slave latch, and the output transfer gate and the output static latch constitute a slave stage of a master-slave latch. The number of the input transfer gates constituting the master stage may be the number of bits (n bits) before decoding the n-bit input signal. On the other hand, in a configuration in which the output of the decoder is directly latched by the master-slave latch circuit, the master stage of the master-slave latch circuit must have a number of transfer gates equal to the number of bits of the decoder output. Therefore, the number of transfer gates is much smaller in the latch circuit with the decode function according to the present invention. By reducing the number of transfer gates, the input capacitance component of the transfer gates constituting the load of the clock signal for controlling the latch operation is reduced as a whole. Since the load on the clock signal can be reduced, the operation speed of the latch circuit can be easily increased.

By adopting the above-mentioned latch circuit with a decoding function in a memory instead of an address decoder and a latch circuit, the clock signal frequency of a clock synchronous memory can be increased, and the access speed synchronized with the clock can be improved. .

If the above-mentioned memory is used as a secondary cache memory of a microprocessor, etc., it is possible to contribute to an increase in data processing speed accompanied by a memory access operation in terms of high-speed operation of the cache memory.

[0015]

FIG. 1 shows an example of a latch circuit having a decoding function. In the figure, 1 is a decoder, 2
Is a master-slave latch. Decoder 1 decodes 2-bit input signals A0 and A1 and outputs 4-bit decode signals S0 to S3. The logical configuration of the decoder 1 is a known content, and the input signals A0 and A1 are
The complementary signals are assigned to 0 and 11 and the complementary signals are allocated to the input signals of the four 2-input NAND gates 12 to 15, and the output signals S0 to S0 are set according to the four combinations of the levels of the 2-bit input signals A0 and A1. Obtain four states in S3,
It has a logical configuration. In other words, the 4-bit output signals S0 to S0 depend on the state of the 2-bit input signals A0 and A1.
There is a decoding theory that makes any one of S3 low level.

The master / slave latch 2 has a master stage on the input side of the decoder 1 and a slave stage on the output side of the decoder 1. The master stage supplies an input transfer gate 2 for each 2-bit input signal A0, A1 of the decoder 1.
0, 21 and input static latches 30, 31. Similarly, the slave stage is provided with output transfer gates 40 to 43 and output static latches 50 to 53 for each of the 4-bit output signals S0 to S3 of the decoder 1. Each transfer gate 2
0, 21, 40 to 43 are constituted by CMOS transfer gates. Each static latch 3
Each of 0, 31, 50 to 53 is constituted by a pair of CMOS inverters having one input mutually coupled to the other output. The transfer gates 20, 21 and 40 to 43
Are switch-controlled in opposite phases by the clock signal CLK.

According to the latch circuit having the decoding function, the input transfer gate 2 constituting the master stage
The numbers 0 and 21 are the same as the 2-bit input signals A0 and A1.
Just a bit. On the other hand, in the configuration in which the output of the decoder 6 is directly latched by the master-slave latch circuit 7 as illustrated in FIG. 2, the master stage of the master-slave latch circuit 7 has the number of bits (4 bits) of the decoder output. It must have an equal number of four transfer gates. Therefore, the number of transfer gates is smaller in the latch circuit with the decode function in FIG. By reducing the number of transfer gates, the input capacitance (input gate capacitance) component of the transfer gates constituting the load of the clock signal CLK for controlling the latch operation is reduced as a whole. Since the load of the clock signal CLK can be reduced, the operation speed of the latch circuit can be easily increased.

FIG. 3 shows an example of a latch circuit with a decoding function when the number of bits of an input signal and an output signal is expanded. In the example shown in the figure, the latch circuit with a decode function receives 8-bit input signals A0 to A2 and forms 8-bit output signals S0 to S7. 3 will be easily understood by those skilled in the art from the description of FIG. 1, and a detailed description thereof will be omitted. In FIG.
2 is an input transfer gate, 30 to 32 are input static latches, 40 to 47 are output transfer gates,
50 to 57 are output static latches.

FIG. 4 is a block diagram of a synchronous SRAM to which a latch circuit with a decoding function is applied.
In FIG. 4, a latch circuit with a decoding function is applied to a row address decode circuit 802 and a column address decode circuit 805.

In FIG. 4, reference numeral 800 denotes a memory cell array in which a large number of static memory cells MC are arranged in a matrix. FIG. 4 representatively shows one memory cell MC. The selection terminal of the memory cell MC is coupled to a representatively shown word line WL, and the data input / output terminal is coupled to a typically shown complementary bit line BL.

A row address signal for selecting a memory cell is latched by a row address latch circuit 803, and the latched row address signal is applied to a row address decode circuit 802. Row address decode circuit 80
2 decodes a row address signal to form a word line selection signal. The word line selection signal is sent to the word driver circuit 8
01, the word driver circuit 801 drives the word line WL selected by the word line selection signal to a selected level.

A column address signal for selecting a memory cell is latched by a column address latch circuit 806 and applied to a column address decode circuit 805.
A column address decode circuit 805 decodes a column address signal to form a bit line selection signal. The complementary bit line BL is commonly coupled to a complementary common data line CD via a column switch circuit 804. The column switch circuit 804 makes the complementary bit line selected by the bit line selection signal conductive to the complementary common data line CD.

In the read operation, the signal read from the memory cell to the complementary common data line CD is applied to the sense amplifier 8
07, the output of the sense amplifier 807 is latched by the data output latch circuit 808, and the data input / output circuit 8
The signal is output to the outside through the line 10. In the write operation,
Write data externally applied to the data input / output circuit 810 is latched by the data input latch circuit 809 and supplied to the complementary common data line CD. Although not shown, the data input latch circuit 809 and the data output latch circuit 808 are constituted by a master slave latch.

In FIG. 4, reference numeral 811 denotes a timing controller to which a chip select signal CS, a write enable signal WE, an output enable signal OE, and a clock signal CK are supplied from outside. The timing controller 811 outputs the chip select signal CS
When the chip selection state is instructed, the write operation is controlled by the assertion of the write enable signal WE, and the read operation is controlled by the assertion of the output enable signal OE. Internal operation timings in the write operation and the read operation are synchronized with the clock signal CK. CLK is one of the internal clock signals for defining the internal operation timing of the synchronous SRAM.

The basic configuration of the row address decode circuit 802 and the column address decode circuit 805 is the same as that of FIG. 1 except that the number of bits of input signals and output signals is much larger than that of FIG. Absent. In the row address decode circuit 802, the address decoder 1 of FIG. 1 has decode logic as a row address decoder, and in the column address decode circuit 805, the address decoder 1 of FIG. 1 has decode logic as a column address decoder.

The row address input latch circuit 803,
Column address input latch circuit 806, row address decode circuit 802, column address decode circuit 80
5. The latch operation of the data output latch circuit 808 and the data input latch circuit 809 is not particularly limited, but is synchronized with the clock signal CLK. In the latch circuits included in these circuits, the master stage performs an input operation and the slave stage performs a holding operation during a low level period of the clock signal CLK. In addition, the master stage performs the holding operation and the slave stage performs the input operation during the high level period of the clock signal CLK.
Therefore, in the read operation of the synchronous SRAM 8, the address signal is applied to the row address input latch circuit 8
03 and the column address input latch circuit 806, the read data is output to the outside from the data input / output circuit 810 two cycles after the clock signal CLK. When the read operation for the synchronous SRAM is continued, data is read out to the outside every cycle of the clock signal CLK. This read cycle becomes shorter as the frequency of the clock signal CLK becomes higher.

At this time, the row address decode circuit 80
2 and the number of output bits of the column address decode circuit 805 correspond to the row address input latch circuit 803, the column address input latch circuit 806, and the data output latch circuit 8
08 and the number of output bits of the data input latch circuit 809. In consideration of this, the configuration shown in FIG. 1 is adopted for the row address decode circuit 802 and the column address decode circuit 805, and the input capacitance component of the transfer gate constituting the load of the clock signal CLK is reduced as a whole. Therefore, it is easy to increase the frequency of the clock signal CK and increase the access speed in synchronization with it. The same applies to the write operation.

FIG. 5 shows a data processing system to which the synchronous SRAM of FIG. 4 is applied. Reference numeral 100 denotes a microprocessor, and a secondary cache memory 102 is connected to the microprocessor 100 via an external bus 101.

The microprocessor 100 is not particularly limited, but may be a 32-bit reduced instruction command RISC (RISC).
et Computer) architecture. The microprocessor 100 has a floating point unit 103. Further, the microprocessor 100 has a central processing unit (CP).
U) 104, and the CPU 104 is an integer unit capable of processing integers. The CPU 104 is connected to the floating point unit 103 via an internal bus 105.
Is joined to. The CPU 104 and the floating point unit 103 fetch instructions and data from the primary cache memory 106. The primary cache memory 106 is connected to a bus controller 108 via a cache bus 107. An instruction address and a data address for external access due to a cache miss or the like in the primary cache memory 106 are given to the bus controller 108. The bus controller 108 activates an external bus cycle to access an external memory or the like according to the instruction address or the data address.

When the external bus cycle is activated, the secondary cache memory 102 is searched.
Data is read from the secondary cache memory 102 or data is written to the secondary cache memory 102. In the case of a cache miss, there is no particular limitation,
A cache fill is performed from the main memory 109 or the like to the secondary cache memory, necessary data is given to the microprocessor 100, or write data is stored in the cache entry where the cache fill is performed.

Although not particularly limited, in FIG.
Is a main memory, which is connected to the external bus 101 at a stage subsequent to the secondary cache memory 102.

FIG. 6 shows a data memory section 110 and an address memory section 111 of the secondary cache memory 102. Although not particularly limited, the secondary cache memory 102 has a configuration as a known set-associative cache memory having a plurality of ways. The synchronous SRAM described with reference to FIG. 4 is used to configure the data memory unit 110 of the secondary cache memory 102. The address memory unit 111 has fields for storing cache tags, valid bits, and the like.
10 has a corresponding field for holding a cache entry. An address signal for external bus access by the bus controller 108 is a tag address 1
12, index address 113 and offset 11
Consists of four. The index for the address memory unit 111 and the data memory unit 110 is index address 1
13 is performed. The address memory unit 111 compares the indexed cache tag with the address tag 112. The comparison operation is performed for each way. The data memory unit 110 is accessed by way selection signal 115, index address 113, and offset 114 in the case of a cache hit. The way selection signal 115, index address 113, and offset 114 correspond to the row address signal and the column address signal supplied to the synchronous SRAM of FIG.
The data memory unit 110 is accessed by the address signal. In FIG. 6, the access path for the cache fill operation and the writing of the tag address is not shown.

If the synchronous SRAM shown in FIG. 4 is used for the secondary cache memory 102 of the microprocessor 100, the cache memory 102 can contribute to a higher data processing speed accompanied by a memory access operation in terms of a high-speed operation.

Although the invention made by the inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited to the embodiments and can be variously modified without departing from the gist of the invention. No.

For example, the number of bits of the decode input signal of the latch circuit with a decode function is not limited to 2 bits or 3 bits, but can be changed as appropriate. The latch circuit with the decode function is not limited to the case where the latch circuit is applied to a synchronous SRAM.
It can be applied to the I logic stage and the like. Further, the configuration of the cache memory to which the latch circuit with the decoding function is applied is not limited to the set associative type, and a cache memory of a direct map, full associative type, or the like can be applied. Further, the present invention can be applied to a general-purpose memory.

[0036]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, the input transfer gate and the input static latch constitute a master stage of the master-slave latch, and the output transfer gate and the output static latch constitute a slave stage of the master-slave latch. The number of the input transfer gates constituting the master stage is the same as that of the n-bit input signal. On the other hand, in a configuration in which the output of the decoder is directly latched by the master-slave latch circuit, the master stage of the master-slave latch circuit must have a number of transfer gates equal to the number of bits of the decoder output. Therefore, the number of transfer gates is much smaller in the latch circuit with the decode function according to the present invention. By reducing the number of transfer gates, the input capacitance component of the transfer gates constituting the load of the clock signal for controlling the latch operation can be reduced as a whole.
Since the load on the clock signal can be reduced, it is easy to increase the operating speed of the latch circuit.

By adopting the latch circuit with the decoding function in the memory instead of the address decoder and the latch circuit, the clock signal frequency of the clock synchronous memory can be increased, and the access speed synchronized with the clock can be improved. .

If the above-mentioned memory is adopted as a cache memory of a microprocessor, it can contribute to an increase in data processing speed accompanied by a memory access operation in terms of a high-speed operation of the cache memory.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an example of a latch circuit with a decoding function.

FIG. 2 is a block diagram showing a comparative example in which an output of a decoder is directly latched by a master-slave latch circuit.

FIG. 3 is a block diagram of a latch circuit with a decoding function when the number of bits of an input signal and an output signal is expanded.

FIG. 4 is a block diagram of a synchronous SRAM to which a latch circuit with a decoding function is applied.

5 is a block diagram of a data processing system to which the synchronous SRAM of FIG. 4 is applied.

6 is a block diagram showing a data memory unit and an address memory unit of the secondary cache memory shown in FIG.

[Description of Signs] 1 Decoder 2 Master-Slave Latch 20-22 Input Transfer Gate 30-32 Input Static Latch 40-47 Output Transfer Gate 50-57 Output Static Latch A0, A1, A2 Input Signal S0-S7 Output Selection Signal CLK Clock Signal 800 Memory cell array MC Memory cell 802 Row address decode circuit 805 Column address decode circuit 100 Microprocessor 101 External bus 102 Secondary cache memory 110 Data memory unit 111 Address memory unit

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hirofumi Kuriko 5-20-1, Josuihoncho, Kodaira-shi, Tokyo Inside Hitachi RLS Engineering Co., Ltd. (72) Inventor Sadayuki Morita Kodaira, Tokyo Hitachi, Ltd. Semiconductor Company, Hitachi, Ltd. 5-2-1, Josuihoncho, Incorporated (72) Inventor Atsushi Hiraishi 5-2-1, Josuihonmachi, Kodaira-shi, Tokyo (72) Inventor Tomohiro Nagano 5-20-1, Josuihoncho, Kodaira-shi, Tokyo Intraday Hitachi SRL Engineering Co., Ltd. (72) Inventor Masaki Harada 5, Josuihoncho, Kodaira-shi, Tokyo Chome 20-1 Nichiyo Cho LSI Engineering Co., Ltd.

Claims (3)

[Claims] 1. An n-bit input signal is decoded to obtain 2 ⁿ
A decoder for generating a bit output signal, an input transfer gate for supplying the input signal to the decoder,
An input static latch for latching the input signal supplied from each input transfer gate and providing the input signal to the decoder, an output transfer gate for passing each output signal of the decoder in a phase opposite to that of the input transfer gate, A semiconductor integrated circuit comprising a latch circuit with a decoding function having an output static latch for latching the output of the output transfer gate. 2. An addressless decoder for selecting a memory cell from a memory cell array based on an address signal,
A semiconductor integrated circuit having a latch circuit for latching a decode signal output from an address decoder, wherein a latch operation of the latch circuit is controlled in synchronization with a clock signal; 2. The semiconductor integrated circuit according to claim 1, further comprising a decoder and a latch circuit. 3. A data processing system comprising a microprocessor integrated into a semiconductor integrated circuit, a cache memory coupled to the microprocessor, and a bus coupled to the cache memory, wherein the cache memory is A data processing system comprising a semiconductor integrated circuit according to item 2 provided in a memory unit.