JPH10214244A - Data transfer control method and communication control processor applying the method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a communication control processor by which DMA data transfer performance corresponding to a line speed can be obtained, and the data transfer performance can not be degraded even when the number of transfer words is small. SOLUTION: In this communication control processor, an information processor 2, main storage device 3, and plural line adapters 41 -4n are connected to a common bus 1 in a fixed priority system. The line adapters 41 -4n are provided with a bus request delay processing means for delaying a bus request interval by using a transmission and reception clock from a MODEM 5 or a DSU 6 whose line speeds are different for obtaining the data transfer performance of the common bus 1 corresponding to the line speed, and a bus request delay invalidation processing means for invalidating the delay of the bus request interval when the number of transfer words is small based on the transmission and reception clock.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer control method capable of performing data processing based on a DMA data transfer performance mainly corresponding to a line speed, and an information processing device and a main storage device provided on a common bus of a fixed priority system. The present invention relates to a communication control processing device to which a line adapter is connected and to which the data transfer control method is applied.

[0002]

2. Description of the Related Art Conventionally, in this type of communication control processing device,
The information processing device, the main storage device, and the memory device are connected to a common bus of a fixed priority system. The memory device here includes a counter for counting the clock of the transmitter, the most significant bit of the counter, and a DMA (Direct M
and means for outputting a result of performing a logical product operation (AND) with a bus request signal of the "memory access" transfer.

That is, in the communication control processing device, the information processing device instructs the DMA controller to start DMA, and
When the bus response signal becomes "1" from the common bus as a result of the completion of the first data transfer by the start of the transfer, the counter is reset at the rising edge and the most significant bit becomes "0". The data transfer request signal is gated and the bus request signal to the common bus is not output. At the same time, the clock of the oscillator is supplied to the counter to start counting. When the count-up proceeds and the most significant bit becomes "1", the gate of the data transfer request signal from the memory device is released and a bus request to the common bus is made. A signal is output.

Incidentally, as a well-known technique related to such a DMA transfer and a memory device, for example, JP-A-59-27
No. 334 discloses a direct memory access (DMA) memory device.

[0005]

In the case of the communication control processor described above, if a plurality of line adapters are connected to a common bus of a fixed priority system, a line adapter with a higher priority does not occupy the common bus. It is necessary to set a data transfer interval (data transfer performance) according to the line speed in the modem, but the line speed is determined by the modem or DSU (Digital S).
service unit) is determined and is not notified to the line adapter. Therefore, since there is no determining means for determining an appropriate counter value for delaying the bus request interval, the DMA is determined.
DMA according to line speed while data transfer performance remains constant
There is a problem that data transfer performance cannot be obtained.

In particular, when the number of words to be transferred is small, such as a pre-processing time in which the information processing apparatus instructs the DMA controller to start the DMA or a post-processing time in which the completion of the DMA is confirmed, the data transfer interval is averaged to the set value. It becomes longer and the data transfer performance decreases.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and the technical problem is that the data transfer performance according to the line speed can be obtained and the data transfer can be performed even when the number of transfer words is small. An object of the present invention is to provide a data transfer control method that does not degrade performance and a communication control processing device to which the method is applied.

[0008]

According to the present invention, when a plurality of line adapters connected to modems or DSUs having different line speeds are connected to a common bus of a fixed priority system to perform data transfer control, a plurality of line adapters are connected. On the line adapter side, a bus request delay processing step of delaying a bus request interval using a transmission / reception clock from a modem or a DSU in order to obtain data transfer performance of a common bus according to the line speed, and the number of transfer words based on the transmission / reception clock Is small, a bus request delay invalidation processing step of invalidating the delay of the bus request interval is obtained.

Further, according to the present invention, in a plurality of line adapters connected to a modem or a DSU having different line speeds and connected to a common bus of a fixed priority system, data transfer of the common bus according to the line speed is performed. Bus request delay processing means for delaying a bus request interval using a transmission / reception clock from a modem or a DSU in order to obtain performance; and a bus request for disabling the delay of the bus request interval when the number of transfer words is small based on the transmission / reception clock. A line adapter having delay invalidation processing means is obtained.

Further, according to the present invention, there is provided a communication control processing device including the line adapter, an information processing device connected to a common bus, and a main storage device.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A data transfer control method according to the present invention and a communication control processing device to which the data transfer control method is applied will be described in detail with reference to the drawings.

First, the outline of the data transfer control method of the present invention will be briefly described. In this data transfer control method, when a plurality of line adapters connected to modems or DSUs having different line speeds are connected to a common bus of a fixed priority system to perform data transfer control, the plurality of line adapters correspond to the line speeds. A bus request delay processing step of delaying a bus request interval using a transmission / reception clock from a modem or a DSU in order to obtain data transfer performance of the common bus, and a delay of the bus request interval when the number of transfer words is small based on the transmission / reception clock. And a bus request delay invalidation processing stage for invalidating the bus request delay.

When such a data transfer control method is applied to line adapters,
Bus request delay processing means for delaying a bus request interval using a transmission / reception clock from a modem or DSU in order to obtain data transfer performance of a common bus according to the line speed; and a bus when the number of transfer words is small based on the transmission / reception clock. A bus request delay invalidating means for invalidating the request interval delay may be provided. However, it is assumed that a plurality of line adapters are connected to a modem or DSU having a different line speed together with a common bus of a fixed priority system.

FIG. 1 is a block diagram showing a basic configuration of a line adapter according to one embodiment of the present invention.

The line adapter 4 includes a transmission / reception buffer 401 connected to the common bus 1 and a transmission / reception buffer
01 and a transmission data line 404, a reception data line 405, a transmission / reception clock line 406, and a signal line 403 connected to the transmission / reception buffer 401, which are connected to the modem or DSU described later. A line control unit 402 for serially / parallel-converting and transmitting data via the common bus 1 and a bus request delay process for delaying a bus request interval using a transmission / reception clock from a transmission / reception clock line 406; A bus request processing unit 420 for performing a bus request delay invalidating process for invalidating a delay of a bus request interval when the number of transfer words is small based on a transmission / reception clock, and a bus request processing unit 420 connected to the common bus 1 Signals required for delay processing and bus request delay invalidation processing are transmitted, and the transmission / reception buffer 4
And a DMA controller 407 for performing the control of the control unit 01.

The bus request processing unit 420 includes a 6-bit counter 421 for counting the transmission / reception clock from the transmission / reception clock line 406, and a 6-bit counter 4
A transmission / reception clock suppression circuit 428 which controls the input of the transmission / reception clock to the output line 423 by controlling the input of the transmission / reception clock to the output line 423, and a D / A of a DMA controller 407 described later.
DM held in MA transfer word count holding register 410
Output control (OR-NOT) circuit 429 for sending "1" to output line 430 if the number of A transfer words is 15 words or less.
And the output from the output line 430 and the most significant bit transmitted to the most significant bit line 422 of the 6-bit counter 421 described above, and a logical sum (OR) circuit for performing a logical sum operation (OR) and transmitting the result to the output line 425 424, the output from the output line 425 and the bus request line 41 from the DMA controller 407.
AND operation (AND) with the bus request signal output to 2
And a bus request suppressing circuit 426 for sending the signal to the output line 427.

The DMA controller 407 has a transmission / reception buffer address holding register 408, a main memory address holding register 409, and a DMA transfer word number holding register 410. When the main memory address and the number of DMA transfer words are given and the DMA transfer is instructed, they are stored in the transmission / reception buffer address holding register 408, the main memory address holding register 409, and the DMA transfer word number holding register 410, respectively. The bus request signal transmitted to the bus request line 412 is "1".

FIG. 2 is a timing chart showing the waveforms of the processing signals (the reference numerals of those signal lines are given in the figure) in each part of the line adapter 4 during data transfer.

In this DMA controller 407,
When the number of DMA transfer words is 16 or more, the DMA transfer word number holding register 410 inputs a bit indicating 16 or more words to the output control circuit 429, and the output signal transmitted from the output control circuit 429 to the output line 430 is “ 0 "
Becomes At this time, the bus request signal on the bus request line 412 becomes “0”, thereby resetting the 6-bit counter 421, the most significant bit on the most significant bit line 422 becomes “0”, which is the output of the OR circuit 424. The output signal (bus request suppression signal) on the output line 425 becomes “0”. As a result, the output signal (bus request signal) on the output line 427 sent from the bus request suppression circuit 426 to the common bus 1 for inputting the bus request suppression signal becomes “0”.

When the bus request signal to the common bus 1 becomes "0", the suppression of the transmission / reception clock from the transmission / reception clock line 406 in the transmission / reception clock suppression circuit 428 is released, and the counter clock on the output line 423 is changed to a 6-bit counter. 421 is input to start counting. In this output line 423, the transmission / reception data is transferred by one bit with one counter clock.

The 6-bit counter 421 counts up, and the most significant bit on the most significant bit line 422 becomes "1" (ie, 8 bits * 4 bytes = 32).
When the clock is counted), the bus request suppression signal on the output line 425 of the AND circuit 424 becomes “1”, and the bus request suppression circuit 426 to which the bus request suppression signal is input is released, and is sent to the common bus 1. Output line 427
Becomes "1". When the bus request signal to the common bus 1 becomes “1”, the transmission / reception clock on the transmission / reception clock line 406 is suppressed by the transmission / reception clock suppression circuit 428, and the 6-bit counter 421 stops counting up.

As described above, regarding the bus request signal transmitted to common bus 1 on output line 427, 6-bit counter 421 sets the counter clock on output line 423 to three.
It will be delayed by the time for counting two clocks.

Further, if the bus is secured, the bus response line 41
3, the DMA controller 407 detects this, and outputs the address to the main memory from the main memory address holding register 409 to the common bus 1 and also sends the address to the sending / receiving buffer 401 to the sending / receiving buffer 401. 408, an address is given, the data of the transmission / reception buffer 401 is output to the common bus 1, and
Word (4 bytes) data is transferred. When the main storage device receives the data, the bus response signal on the bus response line 413 becomes "0", and upon detecting this, the DMA controller 407 sets the bus request signal on the bus request line 412 to "0" and then holds the transmission / reception buffer address. The register 408 and the main storage address holding register 409 are respectively incremented (increased) and the DMA transfer word number holding register 410 is decremented (decreased). If the result of decrementing the DMA transfer word number holding register 410 is not "0", the DMA transfer is repeated by setting the bus request signal on the bus request line 412 to "1".

When the number of DMA transfer words is 15 or less, the output signal on the output line 430 is "1".
And the bus request suppression signal on the output line 425 becomes “1”, and the bus request signal on the bus request line 412 by the bus request suppression circuit 426 is not suppressed, so that the bus request signal on the output line 427 to the common bus 1 is not delayed. .

As an example of the case where the data transfer performance changes in accordance with the circuit speed, assuming that the maximum data transfer performance of the common bus 1 is 20 MB / S (0.2 μS / 1 word), for example, Is 64Kbps, the data transfer delay time is 32 ÷ 64Kbps = 500μ
S, and the data transfer performance is 4 bytes ÷ (500 + 0.
2) The data transfer delay time is 32 when = 0.008 MB / S or when the line speed is 1.544 Mbps.
÷ 1.544 Mbps = 20 μS, and data transfer performance is 4 bytes ÷ (20 + 0.2) = 0.198 MB / S
There are cases where

As an example of the case where the performance degradation is prevented when the number of transfer words is small, for example, if the total time of the DMA pre-processing and post-processing to the DMA controller 407 by the information processing apparatus is 200 μS, If the rotation speed is 1.544 Mbps and the number of DMA words is 10 words, the bus request signal on the bus request line 412 to the common bus 1 is 40 bytes without delay (0.2 / 10 words + 200) = 0. 198 MB / S. Incidentally, if the bus request signal on the output line 427 to the common bus 1 is delayed without considering the number of DMA transfer words, the bus request signal becomes 40 bytes {[(20 + 0.
2) / 10 words + 200] = 0.100 MB / S, and the data transfer performance is halved.

That is, in the line adapter 4, the bus request processing unit 420 delays the time interval of the bus request signal transmitted from the DMA controller 407 to the bus request line 412 according to the line speed and the number of words to be transferred. Limit the traffic (bandwidth) of 1 and shorten the delay time for high line speeds, increase the delay time for low line speeds, and reduce the delay time to 0 (zero) if the number of transfer words is less than a certain number.
Shows that it can be

FIG. 3 is a block diagram showing a basic configuration of a communication control processing device provided with the line adapter 4 described above.

This communication control processing device comprises an information processing device 2, a main storage device 3, and a plurality of line adapters 4 ₁ to 4 _n connected to a common bus 1 of a fixed priority system.

The modem 5 is connected to the line adapters 4 ₁ to 4 _n−1 , and the DSU 6 is connected to the line adapter 4 _n .

The line adapters 4 ₁ to 4 _n−1 have the same configuration as that of the line adapter 4 described above, but the transmission / reception buffer 401 stores and forwards data to and from the main storage device 3 by several hundred kilobytes. The transmission and reception data can be transferred by the DMA transfer of the system.

In this communication control processor, when one frame is completely received from the line to the transmission / reception buffer 401 by the line adapters 4 ₁ to 4 _n in the reception process, one frame is transferred from the transmission / reception buffer 401 to the main storage device 3. The received data is DMA-transferred. In the case of transmission processing, one frame of transmission data is DMA-transferred from the main storage device 3 to the transmission / reception buffer 401, and then one frame is transmitted from the transmission / reception buffer 401 to the line.

The DMA transfer is started by the information processing apparatus 2 instructing the DMA controller 407 via the common bus 1 the address of the main memory 3, the address of the transmission / reception buffer 401, and the number of transfer words (4 bytes). , D
The MA controller 407 issues a bus request to the common bus 1 and, as soon as the bus is secured, transfers data of the bus width (one word) and repeats this for the specified number of transfer words.

The line adapters 4 ₁ to 4 _n use the transmission / reception clock on the transmission / reception clock line 406 from the modem 5 or DSU 6 to obtain the data transfer performance of the common bus 1 according to the line speed as described above. To delay the bus request interval. When the number of words to be transferred is small, the delay of the bus request interval is invalidated.

[0035]

As described above, according to the present invention, when a plurality of line adapters are connected to the common bus of the fixed priority system to perform data transfer control, the plurality of line adapters are adapted to the line speed. In order to obtain the data transfer performance of the common bus, the bus request interval is delayed by using the transmission / reception clock from the modem or DSU, or the bus request interval is disabled when the number of transfer words is small based on the transmission / reception clock. In addition, DMA data transfer performance corresponding to the line speed can be obtained, and even when the number of transfer words is small, deterioration of the data transfer performance can be prevented.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a basic configuration of a line adapter according to an embodiment to which a data transfer control method of the present invention is applied.

FIG. 2 is a timing chart showing waveforms of processing signals (in the figure, reference numbers of those signal lines are attached) in each unit at the time of data transfer of the line adapter shown in FIG. 1;

FIG. 3 is a block diagram showing a basic configuration of a communication control processing device provided with the line adapter shown in FIG.

[Explanation of symbols]

1 common bus 2 information processing apparatus 3 main storage device 4, 4 ₁ to 4 _n line adapter 5 Modem 6 DSU 401 receive buffer 402 line control unit 407 DMA controller 420 bus request processing unit

Claims (3)

[Claims] When a plurality of line adapters connected to a modem or a DSU having different line speeds are connected to a common bus of a fixed priority system to perform data transfer control, the plurality of line adapters respond to the line speeds. A bus request delay processing step of delaying a bus request interval by using a transmission / reception clock from the modem or the DSU in order to obtain data transfer performance of the common bus, and when the number of transfer words is small based on the transmission / reception clock, A bus request delay invalidating step of invalidating a delay of a bus request interval. 2. A plurality of line adapters connected to a modem or a DSU having different line speeds and connected to a common bus of a fixed priority system to obtain data transfer performance of the common bus according to the line speed. Bus request delay processing means for delaying a bus request interval using a transmission / reception clock from the modem or the DSU, and a bus request for invalidating the delay of the bus request interval when the number of transfer words is small based on the transmission / reception clock. A line adapter comprising delay invalidation processing means. 3. A communication control processing device comprising: the line adapter according to claim 2; an information processing device and a main storage device connected to the common bus.