JPH1021188A - Information processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To equally apply the right of access to a plurality of modules con nected to a shared bus by preferentially applying the bus access right correspond ing to a bus access request for response from a module. SOLUTION: Concerning a round-robin circuit, a bus ground signal is outputted to a #2 module 12-2 and in the state of enabling the acceptance of new command by a #3 module 12-3, the command issued by the #2 module 12-2 is accepted. The bus ground signal is outputted to the #3 module 12-3 for sending out reply and after the module to which the reply is returned is turned into the state of enabling the acceptance of command, this signal is outputted while shifting the priority so that the round-robin circuit equally applies the access right to the access request based on non-reply. Thus, just after the #3 module 12-3 sends out the reply, the command of the #2 module 12-2 issuing the command is accepted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an information processing apparatus, and more particularly to an information processing apparatus having a bus using a split transfer system. In recent years, efficient operation of information processing devices has been desired, and a plurality of modules are connected to a shared bus, commands and the like are transferred between the plurality of modules via the shared bus, and resources of the plurality of modules are used. An information processing apparatus that enables efficient operation by being effectively used has been developed.

[0002]

2. Description of the Related Art FIG. 5 is a block diagram showing an information processing apparatus in which a plurality of modules are connected by a shared bus. This type of information processing apparatus 1 includes a plurality of modules 2-1 to 2-N and a plurality of modules 2-1 to
2-N, a shared bus 3 connecting a plurality of modules 2-1
Arbiter 4 for arbitrating the right to use the shared bus 3 from .about.2-N.

The plurality of modules 2-1 to 2-N are configured to access the shared bus 3 as needed and to access other modules. A plurality of modules 2-1 to 2-N are connected to the shared bus 3, and access from the plurality of modules 2-1 to 2-N to the shared bus 3 is performed in packet units, that is, a so-called split system. A transfer method is adopted. At this time, the access from the plurality of modules 2-1 to 2-N to the shared bus 3 is arbitrated by the arbiter 4 so that only a single packet always exists on the shared bus 3.

In such a bus system of the split transfer system, for data transfer between a plurality of modules 2-1 to 2-N, first, a requesting module requests the arbiter 4 for a bus access right. The arbiter 4 arbitrates a request for a bus access right requested from a plurality of modules within a predetermined time, and gives the bus access right to the requested module.

[0005] Upon acquiring the bus access right, the request source module issues a command to the access destination bus module, and once releases the shared bus 3. At this time, the arbiter 4 gives a bus access right to the next module. The module receiving the command outputs a bus access request to the arbiter 4 after the command processing.

In the module receiving the command, when the bus access right is given by the arbiter 4, next, a normal reply (response) for notifying the requesting module of the processing result of the command is transferred. When a command is received and the processing device in the own module is operating and cannot receive the command, a busy reply is returned to the module that issued the command. Upon receipt of the busy reply, the command issuing module requests the bus access right from the arbiter 4 immediately or after a certain period of time has elapsed, and upon acquiring the bus access right from the arbiter 4, issues the same command again.

As described above, a plurality of modules 2-
Data transfer is performed via the shared bus 3 in the 1-N. At this time, the arbiter 4 includes a plurality of modules 2-1.
-N is assigned to the shared bus 3 in a fixed order when the requests for the access right to the shared bus 3 are congested from a plurality of modules 2-1 to 2-N. Commands issued by modules are accepted, but commands issued by lower priority bus modules are likely to be busy and not accepted due to higher priority bus module commands issued earlier. It will not be accepted forever. Therefore, there is a round robin method in which the priority is changed every time.

[0008]

However, in the conventional round robin system in which the order of granting the bus use right is shifted every time in this type of information processing apparatus, when commands are issued in a concentrated manner to the same bus module, , They are not accepted equally.

For example, in a system composed of nine bus modules # 1 to # 9, consider a case where access to the module # 1 is concentrated from other modules. Further, it is assumed that the bus grant signals are given in the order of # 1 to # 9 by the round robin arbitration method.

Here, when the priority of giving the bus grant signal is # 1 → # 2 →... # 8 → # 9, the module # 9 issues commands first to the modules # 2 to # 8. However, when the module # 1 cannot receive a command, it cannot be busy to receive the command.

In the next cycle, even if the priority order for giving the bus grant signal becomes # 9 → # 1 → # 2 →... The state is reached when the reply to the command currently being processed is returned. Therefore, when the # 1 module receives the grant and returns the reply, and when the new command can be accepted, the bus is accessed first. Only the # 2 module is possible.

Accordingly, even if the # 9 module has a higher absolute priority, the possibility of accessing the # 1 module is lower than that of the # 2 to # 8 modules. As described above, simply giving a bus grant signal in the round-robin arbitration scheme cannot equally grant access rights to all modules when access to a given module is concentrated from other modules. There was a problem.

The present invention has been made in view of the above points, and has as its object to provide an information processing apparatus capable of equally giving access rights to a plurality of modules connected to a shared bus.

[0014]

According to a first aspect of the present invention, there is provided an information processing apparatus having a plurality of modules connected to a shared bus, the information processing apparatus being provided in the plurality of modules, for returning a response to another module. A response notifying means for notifying the arbitration means that the request is a bus access request; A bus access right is given priority to an access request, and a bus access right is changed while giving a bus access right to a bus access request other than a bus access request in response to another module while changing the priority order of the module. Arbitration means for granting the right.

According to the first aspect, when a bus access request for a response is made from the module, the arbitration means is notified of the bus access request for the response from the module. When the bus access request is notified, the module gives the bus access right preferentially to the bus access request for the response, so that the response is preferentially performed, and the reception of the command from the module can be prioritized, At this time, the priority of the bus access request other than the response is sequentially changed in the order of the preset arrangement, and the bus access right is equally given to a plurality of modules. The access rights from modules can be equalized, so that even if access requests are concentrated on a particular module, Le can be performed to access equally.

The arbitration means may assign a bus access right to a bus access request other than a bus access request for responding to another module, and may assign the bus access right to the plurality of modules. Are sequentially changed in a preset order.

According to the second aspect, when the bus access right is given to a bus access request other than the bus access request for responding to another module, the priority to give the bus access right is assigned to the plurality of modules in advance. Since the change is performed sequentially in a set order, that is, in a so-called round-robin manner, the priority to which the bus access right is given is changed every time, and the bus access right can be equally given to a plurality of modules.

The arbitration means may determine whether the bus access request supplied from the plurality of modules in response to the notification from the response notification means is a bus access request for a response to another module. A determination circuit for determining,
First holding means for holding a determination result of the determination circuit and a bus access request for a response to the another module; a determination result of the determination circuit; a bus access request for a response to the other module; And a bus access request for responding to the other module, which monitors a bus access request for responding to the other module, which is retained by the first retaining means. Bus access suppressing means for suppressing a bus access request other than a bus access request for a response to the other module held in the second holding means when there is a bus access request other than the second bus access request; A bus access request other than a bus access request for a response to the other module held in the holding circuit is monitored, and a bus access request for a response to the other module is monitored. A holding unit control unit that permits the first and second holding units to hold a new bus access request when a bus access request other than a bus access request is resolved; and a holding unit that is held by the first holding unit. First arbitration means for arbitrating a bus access request for a response to the other module and sequentially granting a bus access right;
Second arbitration means for changing the priority order in which the bus access right is given to a bus access request other than the bus access request for responding to the other module held in the holding means, and giving the bus access right while changing the priority order; It is characterized by having.

According to the third aspect, it is determined whether or not the bus access request from the module is a bus access request for a response to another module in response to the notification from the module notifying means, and the other module is notified of the request. Is held in the first holding means, the other bus access requests are held in the second holding means, and the bus access requests held in the first holding means are sequentially held. When the bus access is permitted and the bus access request held by the first holding means is released, this is detected, and the bus access request held by the second holding means is sequentially enabled for the bus access request. At this time, by sequentially changing the priority of granting the bus access and permitting the module to access the bus, it is possible to respond to a bus access request for a response. Priority access is granted, then it becomes possible to accept the command, sequentially changing the priority giving the bus access right in the order set in advance the plurality of modules for normal bus access request,
Since bus access is provided by a so-called round-robin method, even if access requests are concentrated on a specific module, other modules can access equally.

Preferably, the first and second holding means hold a bus access right supplied in a predetermined period, and the bus access held in the temporary holding circuit in the next period. And a holding circuit for holding the right.

According to the fourth aspect, the first and second holding means are constituted by a temporary holding circuit and a holding circuit, so that access to a bus access request output during a certain period is permitted. , The next bus access request can be input, and therefore, efficient access can be performed.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a block diagram of an embodiment of the present invention. The information processing apparatus 11 of the present embodiment is connected to and shared by N modules 12-1 to 12-N and modules 12-1 to 12-N that perform data processing. Data bus 13 for transferring commands, data, etc. between the modules, modules 12-1 to 12-
N, and arbiter 14 for arbitrating bus access requests to data bus 13 from modules 12-1 to 12-N, and arbiter 14 from modules 12-1 to 12-N.
Bus request signal line 15 for transmitting a bus request signal for requesting use of the data bus 13 to the arbiter 14 from the modules 12-1 to 12-N.
3 is a reply display signal line 16 for identifying whether or not the use request is a use request for a reply (response) to another module, and from the arbiter 14 to the modules 12-1 to 12-12.
-N is provided with a bus grant signal line 17 for supplying a bus grant signal for granting a bus use permission.

Each of the modules 12-1 to 12-N supplies a bus access request to the arbiter 14 to acquire the right to use the shared bus 13 when accessing another module. Modules 12-1 to 12-N are arbiter 1
The access to the shared bus 13 is permitted by the access permission from the server 4, and commands and the like are supplied to other modules. FIG.
1 shows a block diagram of a module according to an embodiment of the present invention.

The modules 12-1 to 12-N include an internal circuit 18 for processing data, a bus request generating circuit 19 for generating a bus request signal for requesting the arbiter 14 to use the bus in response to a request from the internal circuit 18, It comprises a reply display signal generation circuit 20 for generating a reply display signal according to whether or not a request from the internal circuit 18 is a response for returning a reply to another module.

The internal circuit 18 processes the data, and when an access request to another module is generated by the processing, the internal circuit 18 instructs a bus request generation circuit 19 to generate a bus request signal. Bus request generation circuit 19
Generates a bus request signal that becomes high level “1” at the time of request in response to a bus request signal generation command from the internal circuit 18, and supplies the bus request signal to the bus request signal line 15. At the same time, the reply display signal generation circuit 20
Monitors the internal circuit 18, determines whether the access request generated in the internal circuit 18 is a reply, generates a reply display signal that becomes high level “1” at the time of reply, and supplies it to the reply display signal line 16. .

The bus request line 15 and the reply display signal line 16 are provided in each of the modules 12-1 to 12-N, and are connected to the arbiter 14 for each of the modules 12-1 to 12-N. FIG. 3 is a block diagram of an arbiter according to one embodiment of the present invention.

The arbiter 14 has a bus module 12-1.
Selecting circuit 22 for selecting a bus request signal for reply from a bus request signal supplied from each of the bus modules 12-1 to 12-N, and a bus request supplied from each of the bus modules 12-1 to 12-N A non-reply selection circuit 23 for selecting a bus request signal for non-replies other than a reply from a signal according to a reply indication signal, a reply holding circuit 24 for holding the bus request signal selected by the reply selection circuit 22, a non-reply selection The non-reply holding circuit 25 for holding the bus request signal selected by the circuit 23, the reply arbitration circuit 26 for sequentially selecting the bus request signal held in the reply holding circuit 24, and the bus request signal held in the reply holding circuit 24 Monitor for non-replies Control circuit 27 for controlling the hold timing of the reply hold circuit 24 and the non-reply hold circuit 28 together with the turning on or off the output of the bus request signal held in Lee holding circuit 25, a non-reply hold circuit 2
The request signal held in the non-reply holding circuit 2
5, a round-robin circuit 28 that circulates and outputs the output every cycle, a non-reply arbitration circuit 29 that sequentially outputs the output of the round robin circuit 28, an output of the reply arbitration circuit 26, and an output of the non-reply arbitration circuit 29. It comprises an output circuit 30 for outputting as a grant signal.

The arbiter 14 has modules 12-1 to 12
-N and the modules 12-1 to 12-N supplied from the bus request signal line 15 via the bus request signal line 15.
Is supplied via the reply display signal line 16 to the reply selection circuit 22 and the non-reply selection circuit 23 first.

The reply selection circuit 22 includes a module 12-
AND gates 22-provided corresponding to 1-12 -N
1 to 22-N. The bus request signal line 1 of the module 12-1 is connected to one end of the AND gate 22-1.
5-1 is connected, and a bus request signal generated in the module 12-1 is supplied.
One reply indication signal line 16-1 is connected, and the reply indication signal generated by the module 12-1 is supplied. When the bus request signal supplied from the module 12-1 is for a reply, the AND gate 22-1 turns on when the reply indication signal is at a high level "1", and sends the bus request signal to the reply holding circuit 24. If the bus request signal is other than a reply, the reply display signal becomes low level '0', so it is turned off,
The bus request signal is suppressed.

Also, AND gates 22-2 to 22-N
Corresponds to the bus request signal and the reply indication signal from the corresponding modules 12-2 to 12-N.
The same operation as that of the ND gate 22-1 is performed. The non-reply selection circuit 23 includes AND gates 23-1 to 23-N provided corresponding to the modules 12-1 to 12-N. A bus request signal line 15-1 of the module 12-1 is connected to one end of the AND gate 23-1, and a bus request signal generated in the module 12-1 is supplied. A reply display of the module 12-1 is provided to the other end. The signal line 16-1 is inverted and input to the module 12-1.
Is supplied. When the bus request signal supplied from the module 12-1 is for a reply, the AND gate 23-1 turns off because the reply display signal becomes high level '1', and the bus request signal is suppressed. If the bus request signal is other than a reply, the reply display signal becomes low level “0”, so that it is turned on, and the bus request signal is supplied to the reply holding circuit 24.

Also, AND gates 23-2 to 23-N
Corresponds to the bus request signal and the reply indication signal from the corresponding modules 12-2 to 12-N.
The same operation as that of the ND gate 23-1 is performed. The reply holding circuit 24 has a temporary holding circuit 24a and a holding circuit 24b for holding the bus request signal selected by the reply selection circuit 22. The bus request signal selected by the reply selection circuit 22 is first supplied to and held in the temporary holding circuit 24a in accordance with a control signal from the control circuit 27. The bus access signal held in the temporary holding circuit 24a is changed according to a control signal from the control circuit 27.
b, and the temporary holding circuit 24a newly holds the bus access signal.

The bus access signal held in the holding circuit 24b is supplied to the reply arbitration circuit 26. The reply arbitration circuit 26 supplies the bus access signals to the output circuit 30 in a preset order from the bus access signals held in the holding circuit 24b.

The non-reply holding circuit 25 includes a temporary holding circuit 25a and a holding circuit 25b for holding the bus request signal selected by the non-reply selection circuit 23. The bus request signal selected by the non-reply selection circuit 23 is first held in the temporary holding circuit 25a in accordance with the control signal from the control circuit 27. Temporary holding circuit 25a
Is supplied to the holding circuit 25b in accordance with the control signal from the control circuit 27 and is held therein.
The temporary holding circuit 25a newly holds a bus access signal. Further, the bus access signal held in the holding circuit 25b is supplied to the control circuit 27.

The control circuit 27 includes a holding circuit 2 on the reply side.
4b, an OR gate 27a for monitoring the bus request signal, and an AN for controlling the supply of the bus request signal held in the non-reply side holding circuit 25b to the round robin circuit 28 according to the output signal of the OR gate 27a.
The D gates 27b-1 to 27b-N, the output of the OR gate 27a and the bus request signal held in the non-reply-side holding circuit 25b are supplied, and the output of the OR gate 27a and the bus request signal held in the non-reply-side holding circuit 25b. And a NOR gate 27c for generating a control signal for controlling the holding timing of the signals of the reply holding circuit 24 and the non-reply holding circuit 25 in accordance with the bus request signal.

The bus access signal held in the reply holding circuit 24b is supplied to the OR gate 27a. When the bus access signal for reply is held from the modules 12-1 to 12-N, the OR gate 27a is turned on. 27a
Becomes high level '1'. AND gate 27b
-1 to 27b-N are supplied at one end with the output of the OR gate 27a inverted and supplied to the other end with a non-reply holding circuit 25b.
Are supplied.

The AND gates 27b-1 to 27b-N are
If the output of the OR gate 27a is high level "1", that is, if at least one bus access signal for reply is held in the reply holding circuit 24b, it is turned off and held in the non-reply holding circuit 25b. When the supply of the bus access signal to the round robin circuit 28 is stopped, and the output of the OR gate 27a is at low level "0", that is, when the reply holding circuit 24b has no bus access signal for reply, it turns on. Then, the bus access signal held in the holding circuit 25b on the non-reply side is supplied to the round robin circuit 28.

The NOR gate 27c has an OR gate 27
a and the bus access signal held in the non-reply side holding circuit 25 is supplied, and the output of the OR gate 27a and the NOR logic of the bus access signal held in the non-reply side holding circuit 25b are taken and output. . The NOR gate 27c sets the output of the OR gate 27a to low level "0", that is, there is no bus access signal for reply in the reply holding circuit 24b and the bus access signal held in the non-reply holding circuit 25b. When all signals are low level '0', high level '1'
In other cases, a control signal of low level '0' is output.

The holding circuits 24 and 25 include a NOR gate 27c.
, The holding and shifting of the bus access signal are repeated. That is, the holding circuit 24 is connected to each module 12-
The bus request signals from 1 to 12-N are temporarily held in the temporary holding circuit 24a, and when all requests in the holding circuit 24b have been processed, the bus request signals temporarily held in the temporary holding circuit 24a are processed. Shift to the holding circuit 24b. The holding circuit 25 includes the modules 12-1 to 12-N
From the temporary holding circuit 25a
When all the requests in the holding circuit 25b are processed, the bus request signal temporarily held in the temporary holding circuit 25a is shifted to the holding circuit 25b.

As described above, the holding circuits 24 and 25 for holding the bus request signal are constituted by the temporary holding circuits 24a and 25a and the holding circuits 24b and 25b for supplying the bus request signal to the arbitration circuits 26 and 29. By shifting the bus request signal sequentially from 24a, 25a to holding circuits 24b, 25b and taking arbitration, a bus grant can be given efficiently.

The non-reply bus request signal is supplied to the round robin circuit 28. In the round robin circuit 28, every time a bus request signal is taken into the holding circuit 25b from the temporary holding circuit 25a, the input to the arbitration circuit 29 is shifted by one.

For example, # 1 is a bus request signal from the module 12-1, # 2 is a bus request signal from the module 12-2, # 3 is a bus request signal from the module 12-3,... To module 12-
Assuming that the request signal is a bus request signal from N, the outputs (# 1, # 2, # 3,..., #N) of the holding circuit 25b are initially unchanged (# 1, # 2, # 3,. n) to the arbitration circuit 29 in the order, and when the bus request signal is held again, (# 2, # 3..., #
(n, # 1) is transmitted by shifting one bit.
Thereafter, the shift amount is increased by one each time the data is held again.

At this time, the shifting direction may be set separately to the opposite direction. Outputs from the reply and non-reply arbitration circuits 26 and 29 are output from the output circuit 3.
0 is supplied. The output circuit 30 includes N OR gates 30
-1 to 30-N.

One end of the OR gate 30-1 is supplied with the reply bus grant signal of the module 12-1 from the reply arbitration circuit 26, and the other end of the OR gate 30-1 is supplied with the module 1 from the non-reply arbitration circuit 29.
The non-reply bus grant signal 2-1 is supplied, the OR logic is obtained, the signal is supplied to the bus grant signal line 17-1 as a bus grant signal, and supplied to the module 12-1.

Similarly to the OR gate 30-1, one end of the OR gates 30-2 to 30-N is supplied with the reply bus grant signal of the modules 12-2 to 12-N from the reply arbitration circuit 26, and the other end. From the non-reply arbitration circuit 29 to the module 12-2
１２12-N are supplied to the bus grant signal lines 17-2〜17-N as the bus grant signal, and the OR logic of the non-reply bus grant signals is supplied to the bus grant signal lines 17-2〜17-N. Supplied.

The modules 12-1 to 12-N determine that the access permission has been granted when the bus grant signals supplied from the bus grant signal lines 17-1 to 17-N are at the high level "1". It sends commands, replies, etc. to the data bus 13. FIG. 4 shows a timing chart of one embodiment of the present invention.

The specific operation will be described with reference to an example of a time chart shown in FIG. FIG. 4A shows a timing chart when the # 1, # 2, and # 4 modules simultaneously issue commands to the # 3 module. The round robin circuit 28 includes # 2, # 4, and # 1 modules 12-2 and 12-.
Assuming that the priorities are set in the order of 4, 12-1,
First, a bus grant signal is output to the # 2 module 12-2. At this time, if the # 3 module 12-3 is in a state capable of accepting a new command, the # 2 module 12-2
-2 issued command is accepted.

Similarly, if the # 3 module 12-3 can accept a new command, the commands are accepted in the order of # 4, # 1 modules 12-4, and 12-1. Similarly, FIG. 4B shows that the modules 12-1, 12-2, and 12-4 of # 1, # 2, and # 4 are trying to issue commands to the # 3 module 12-3 at the same time, and The timing chart when the module 12-3 has also issued a request for reply transmission is shown.

At time t11, the bus grant signal first
This is output to the # 3 module 12-3 which is a reply transmission, the access to the reply has been completed, and the module to which the reply has been returned is ready to accept the command. On the other hand, the round robin circuit 28 outputs the data while shifting the priority so that the access right is equally given. That is, the shift is performed at times t12, t13, and t14, and in this example, the bus grant signal is output in the order of # 2 module 12-2 →→ # 4 module 12-4 → # 1 module 12-1.

As described above, the command of the # 2 module 12-2 which has issued the command immediately after the # 3 module 12-3 has transmitted the reply is accepted. If this is a system in which the entire conventional system is simply shifted by the round robin circuit 28, the bus grant signals are # 2, # 3, #
Since the output is performed in the order of # 4 and # 1, the # 3 module 12
-3 issues a command immediately after sending a reply #
The commands of the four modules 12-4 are received. As described above, the # 2 module 12-2 receives the command of the other module despite the highest arbitration priority, but in this embodiment, the reply is returned first, A new command (non-reply) is issued after a new command can be accepted in the module (here, # 3 module 12-3) to which the reply is returned, and the entire module is round robin. Therefore, even when access to a certain module is concentrated, the access right can be equally given.

[0050]

As described above, according to the first aspect of the present invention, when a bus access request for a response is made from a module, the arbitration means is notified of the bus access request for a response from the module. In the arbitration means, when a bus access request for a response is notified from the module, a priority is given to the bus access request for the response from the module. Can be given priority, and at this time, for bus access requests other than responses, the priority is sequentially changed in the order of a preset arrangement,
Since access rights are given equally to a plurality of modules, access rights to a specific module from other modules can be equalized. Therefore, even when access requests are concentrated on a specific module, other modules can be equalized. It has features such as access.

According to the second aspect, when a bus access right is given to a bus access request other than a bus access request for responding to another module, a priority to give the bus access right is assigned to the plurality of modules in advance. Since the change is performed sequentially in a set order, that is, in a so-called round-robin manner, the priority to which the bus access right is given is changed every time, and the bus access right can be equally given to a plurality of modules. It has the features of

According to the third aspect, it is determined whether or not the bus access request from the module is a bus access request for a response to another module according to the notification from the module notifying means, and the other module is notified of the request. Is held in the first holding means, the other access requests are held in the second holding means, and the bus access requests held in the first holding means are sequentially stored in the bus. When the access is permitted and the bus access request held in the second holding unit is released, this is detected, and the bus access request held in the second holding unit is sequentially permitted in response to the bus access request. At this time, by sequentially changing the priority of granting the bus access and permitting the module to access the bus, priority is given to the bus access request for response. After the access is permitted and the command can be accepted, the priority of giving the bus access right to the normal bus access request is sequentially changed in a preset order of the plurality of modules, so-called, Since the bus access is provided by the round robin method, even if access requests are concentrated on a specific module, other modules can access equally.

According to the fourth aspect, the first and second holding means are constituted by a temporary holding circuit and a holding circuit, so that access to a bus access request output during a certain period is permitted. In this case, the next bus access request can be input, and the access can be performed efficiently.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a block diagram of a module according to an embodiment of the present invention.

FIG. 3 is a block diagram of an arbiter according to an embodiment of the present invention.

FIG. 4 is an operation timing chart of one embodiment of the present invention.

FIG. 5 is a block diagram of an information processing apparatus having a split-type bus.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Information processing apparatus 12-1 to 12-N module 13 Data bus 14 Arbiter 15 Bus request signal line 16 Reply display signal 17 Bus grant signal line 18 Internal circuit 19 Bus request generation circuit 20 Bus request signal generation circuit 21 Reply display signal generation Circuit 22 Reply selection circuit 23 Non-reply selection circuit 24 Reply holding circuit 25 Non-reply holding circuit 26, 29 Arbitration circuit 30 Output circuit

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor: Tamotsu Matsuo 2-6-6 Jomi, Chuo-ku, Osaka-shi, Osaka Fujitsu Kansai Digital Technology Co., Ltd. In-house (72) Inventor: Mamoru Sakakura, Nakahara-ku, Kawasaki-shi, Kanagawa 4-1-1 Odanaka Fujitsu Limited

Claims (4)

[Claims] 1. An information processing apparatus comprising a plurality of modules connected to a shared bus, wherein the arbitration unit is notified of a bus access request provided in the plurality of modules and for returning a response to another module. A response notifying unit, and when the response notifying unit receives a notification that is a bus access request for returning a response to another module, giving priority to the bus access right to the bus access request for the response to the other module. Arbitration means for giving a bus access right while changing the priority of a module giving the bus access right to a bus access request other than a bus access request in response to another module. Information processing device. 2. The arbitration means, when granting a bus access right to a bus access request other than a bus access request for responding to another module, assigns the bus access right to the plurality of modules in a predetermined order. 2. The information processing apparatus according to claim 1, wherein the information is sequentially changed. 3. The arbitration unit determines whether the bus access request supplied from the plurality of modules is a bus access request for a response to another module in response to the notification from the response notification unit. A judging circuit; first holding means for holding a judgment result of the judging circuit and a bus access request for a response to the another module; and a judging result of the judging circuit for responding to the other module. A second holding unit for holding a bus access request other than the bus access request of the above, and a bus access request for responding to the other module held by the first holding unit, and monitoring the other module When there is a bus access request for a response to the other module, a bus other than the bus access request for a response to the other module held in the second holding means Bus access suppressing means for suppressing an access request; monitoring a bus access request other than a bus access request for a response to the other module held in the second holding circuit; and responding to the other module. A holding unit control unit that allows the first and second holding units to hold a new bus access request when a bus access request other than the bus access request for the first time is canceled; First arbitration means for arbitrating a bus access request held for a response to the other module and sequentially giving a bus access right; and a response to the other module held in the second holding means Second arbitration means for giving a bus access right while changing a priority order for giving a bus access right to a bus access request other than a bus access request for The information processing apparatus according to claim 1, wherein the door. 4. The temporary holding circuit for holding a bus access right supplied for a predetermined period, the first and second holding means for storing the bus access right held by the temporary holding circuit for a next period. 4. The information processing apparatus according to claim 3, further comprising a holding circuit for holding.