JPH1021071A - Processor operating method processing plural instructions - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain an operation method for making a microprocessor process more than one instructions extremely efficiently by minimizing increase in the complexity of its architecture. SOLUTION: This operating method 20 includes several steps. Namely, one of instructions is received (step 22). It is judged whether the received instruction contains an operand prefix for discriminating a 3rd operand (steps 24 and 26). In response to a judgement showing that the received instruction contains the operand prefix, two operands selected out of a 1st operand, a 2nd operand, and a 3rd operand are used to execute this instruction so that one of the 1st, 2nd, and 3rd operands is not selected, thereby generating a result (step 28). Further, this result is stored in the unselected operand.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to microprocessor technology, and more particularly, to a circuit, system and method for extending a two-operand instruction to a three-operand instruction using an instruction prefix.

[0002]

BACKGROUND OF THE INVENTION Significant advances have been made in microprocessor design to improve microprocessor performance, as measured by the number of instructions executed over a given time interval. One such advance is the recent introduction of "superscalar" type microprocessors, which achieve parallel instruction computation using a single instruction pointer. Typically, superscalar microprocessors have multiple execution units, such as a multiple integer arithmetic unit (ALU) and a floating point unit (FPU), to execute program instructions. As such, multiple machine instructions may be executed concurrently in a superscalar microprocessor, with a clear benefit to the overall performance of the device and its system applications.

[0003] Another popular technique used in modern microprocessors to improve performance involves "pipeling" of instructions.
As is well known in the art, microprocessor instructions each perform a number of sequential operations, such as instruction fetch, instruction decode, retrieving operands from registers or memory, executing instructions, and rewriting instruction results. Generally accompanies. The pipeline of instructions in a microprocessor is
Refers to staging of an instruction sequence such that multiple instructions in the sequence of instructions are processed simultaneously at different stages in the internal sequence. For example, if the pipelined microprocessor is executing instruction n in a given microprocessor clock cycle, the four-stage pipelined microprocessor will simultaneously (ie, in the same machine cycle) execute instruction n + 1 (ie, , The next instruction in the series)
, Decode instruction n + 2, and fetch instruction n + 3. Through the use of pipelining, the performance of a microprocessor can be effectively executed at a rate of one sequence of instructions per clock cycle.

[0004] Although the use of both pipelined and superscalar techniques has caused many modern microprocessors to execute instructions at a rate higher than one per machine clock cycle, many limitations still arise, and these imply overall performance. Lower. For purposes of embodiments of the present invention, 1
One important example occurs in architectures that were first developed several years ago and are necessarily limited to two-operand instructions (eg, the X86 architecture). For example, pseudocode for an add instruction in an instruction set of such an architecture may take the following form:

[0005]

ADD operand 1, operand 2 Instruction (1)

Instruction (1), when executed, operates as shown diagrammatically below.

[0007]

[Equation 2] Operand 1 ← Operand 1 + Operand 2

Instruction (1) therefore adds operand 1 to operand 2 and a subsequent rewrite stage stores the sum of the results in operand 1. Note that there are some restrictions on such instructions. For example, operand 1 operates as both a source operand and a destination operand, ie, one of the addends for the addition operand is retrieved from operand 1 and then the resulting sum is also stored in operand 1. Therefore, one disadvantage is that the value originally stored in operand 1 is rewritten by the result of the addition, and therefore, unless the initial value copies it somewhere first, Note that there is a risk of loss.
In other words, to preserve the value of the first operand,
Prior art instruction sets require the processing of two separate instructions with a total of three operands, as follows.

[0009]

## EQU00003 ## MOV Operand 3, Operand 1 Instruction (2)

[0010]

ADD operand 3, operand 2 instruction (3)

Instructions (2) and (3), when executed, operate as shown schematically below.

[0012]

[Equation 5] Operand 3 ← Operand 1

[0013]

[Equation 6] Operand 3 ← Operand 3 + Operand 2

Therefore, the instruction (2) has the operand 1
Is copied into operand 3 and then instruction (3) performs an addition to calculate the same sum as in instruction (1) above, but instead of operands 1 and 2, Operands 3 and 2 are used. The same sum is calculated by instruction (3) because at this point operands 2 and 3 of instruction (3) have the same values as operands 2 and 1 have.
Is the same due to instruction (2). Therefore, a total of three operands are required, along with a total of two different instructions, to cause the addition operation and to preserve both augmented values.

In the last few years, microprocessor architectures, such as reduced instruction set computer (RISC) architectures, have included three operand instructions. For example, many RI
Instructions in the SC architecture have the following general format:

[0016]

ADD operand 3, operand 2, operand 1 Instruction (4)

In most RISC machines, operand 3 is the destination operand, while operands 2 and 1 are the source operands. Thus, for instruction (4), execution of this instruction makes operands 1 and 2 the source operands for the augend, while the sum is stored in operand 3 as the destination. Since the order of these operands can be changed, either operand 1 or operand 2 can be the destination and operand 3 can be the source. However, it should be noted that in any case, and unlike older architectures, a single operand in a three-operand architecture will not serve as both a source operand and a destination operand.

Therefore, the RISC architecture has three
Although allowing for an operand instruction, this instruction is only available in certain architectures and according to the format described above. However, there are currently many other architectures that do not include such instructions or even comparable instructions. For example, the X86 architecture currently boasts a very large market share,
Still does not include such orders. In fact, adding too many instructions to such an architecture based on a completely new opcode would place a considerable burden on the decoding hardware,
And also will deplete, if not exceed, the amount of opcode space left in such an architecture.

[0019]

From the above point of view, it is bit comparable to currently prevalent architectures and minimizes the increase in complexity based on considerations such as instruction decoding and opcode space. There is a need to develop a three-operand instruction architecture that minimizes this.

[0020]

SUMMARY OF THE INVENTION A preferred embodiment of the present invention is directed to a method, circuit and system for processing a plurality of instructions.
In one embodiment, a method receives one instruction from a plurality of instructions, the instruction including a first operand and a second operand. Next, it is determined whether the received instruction includes an operand prefix identifying the third operand. Responsive to determining that the received instruction includes an operand prefix, the first operand, the second operand,
And two operands selected from among a third operand and a first operand, a second operand,
And executing one of the instructions so that one of the third operands is not selected and produces a result. The result is then stored in the operands that were not selected. Other circuits, systems, and methods are also disclosed and claimed.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG.
Is shown diagrammatically. The encoding of instruction 10 is broken down into four parts, which include prefix 12, opcode 14, first operand 16, and second operand 1
There are eight. As described below, the instruction 10 may include additional information, among which there are other types of prefixes, which are not shown in FIG. 1 for simplicity. Including the prefix 12 in the format of the instruction 10 results in a total of three operands in a single instruction, which operands 16 and 18 as well as the third associated with the prefix 12
There is an operand. Turning now to these operands, in the following discussion, first the operands 16 and 18 following the opcode 14 and then the prefix 1
Handle the third operand associated with 2.

In one embodiment, operands 16 and 18 are preferably source operands;
Specified as in the known X86 instruction set. As used herein, the term simply operand may refer to either a source operand or a destination operand. The source operand is the operand from which data is retrieved to perform the operation, while the destination operand is the operand whose data is stored as a result of the operation. Further, the source operand may represent actual data for the operation (ie, immediate data), or
Alternatively, a processor resource (eg, a register or a memory) that stores actual data may be specified. Therefore, in the example where operands 16 and 18 are preferably established in the same way as the X86 instruction set, operand 16 is the source operand and destination (as with instruction (1) above). Operand 18 can be both operands
Is typically limited to the source operand. Given the above explanation, consider an example. First, for a two-operand ADD immediate data instruction, operand 16 is both a source operand and a destination operand and specifies a processor resource, while operand 18 is stored in the resource specified by operand 16. Immediate data that is affected by the data. As another example, two-operand ADD
For register-to-register instructions, operand 16 is also both a source operand and a destination operand, ie, as a source, operand 16 stores data that is added to the data in the resource specified by source operand 18. Operand 16 specifies a resource, and as a destination operand, specifies a resource to store the sum. Still further, while operands 16 and 18 are shown in a general sense in FIG.
ModRM bytes and / or SIBs (scale, index, base,
That is, it may be specified using a known variable value such as a scale, index, reference) byte.

Turning now to prefix 12, this encodes enough information to represent the third operand. Note that prefix 12 may have a length of more than one byte. In one embodiment, the third operand included within prefix 12 is the destination operand, so the following example involves a prefix that includes the destination operand for a deeper understanding thereof. However, as described below, alternative embodiments in which the operands contained within prefix 12 are source operands are also comprehensible by those skilled in the art and, as described above, may be immediate data or processor. Resources may be specified. In the case of a prefix operand as a source operand, processor resources are either identified directly or by some alternative scheme, such as based on the ModRM and / or SIB systems described above. In any case, decoding and execution of instruction 10, as described in detail below, enables a three-operand operation to be performed with a single instruction.

FIG. 2 is a flowchart 2 of an embodiment of the method of the present invention.
Indicates 0. It responds to instructions such as instruction 10 shown in FIG. Step 22 receives instructions from a sequence of instructions arranged in a typical sequential manner into a processor pipeline. For example, step 22 receives instruction 10 of FIG. 1, or alternatively receives some other type of instruction that has no prefix or has a prefix intended for some other operation. In any case, the timing of receiving instructions is dictated by the order of the program code, but as is known in the art, instruction fetching, decoding, execution, and other steps may occur simultaneously or out of order. There are even things. For example, some instructions may actually be fetched at once. As another example, in superscalar operation, certain instructions may be executed concurrently or may not even follow their sequential order. Thus, step 22 simply represents that the instruction is retrieved anyway and then analyzed according to the subsequent steps.

Step 24 determines whether the instruction received in step 22 includes an instruction prefix. Preferably, step 24 occurs during the pre-decode stage of the operation and may be accomplished using known decoding techniques. In fact, one advantage of this embodiment is that the various instruction sets, including the X86 instruction set, already include a prefix used for purposes other than specifying the third operand. . Therefore, microprocessors based on these instruction sets should already contain enough hardware to determine if a prefix is present and to decode it if it is encountered. Therefore, those skilled in the art can further modify such a system to decode the instruction prefixes described herein with little additional hardware. Returning to step 24, if the answer is no, flow returns to step 22 to analyze the next sequential instruction. Note that the return to step 22 is for the purposes of the present embodiment, ie, in response to a three-operand prefix instruction. Thus, in practice, many other steps or methods may occur for instructions that do not include an instruction prefix, but such methods need not be dealt with in detail here.

Returning to step 24, if the determination in this step is affirmative, flow proceeds to step 26. Step 26 analyzes the prefix to determine the type. If the instruction prefix specifies a third operand, flow proceeds to step 28. On the other hand, if the instruction prefix specifies a prefix other than the third operand, flow proceeds to step 30.

Step 30 operates solely in response to other known prefixes. For example, in the X86 architecture, REP, REPE / REPZ, REPN
An instruction prefix, such as E / REPNZ or LOCK, may be encountered at step 26, in which case the flow proceeds to step 30 and other steps (not shown) responsive to prefixes known in the art. Again, because these types of instruction prefixes are not three-operand prefixes, and furthermore, the processing of such instruction prefixes is well known in the art, so the methods involved need not be dealt with in detail here. In any event, once the instruction is completed by the prior art, flow returns from step 30 to step 22 to process the next received instruction.

Referring back to step 26, if the determination in this step is affirmative, flow proceeds to step 28. Step 28 completes the third operand prefix instruction according to the additional information provided by the third operand prefix. To demonstrate an example of the completion of such an instruction, and a clear difference from the prior art, the first operand is preserved and the third operand, which is the result of the operation on the first and second operands, is finalized. Recall the prior art example above, where two instructions are required to be stored in the prior art.

[0029]

## EQU8 ## MOV Operand 3, Operand 1 Instruction (2)

[0030]

ADD operand 3, operand 2 instruction (3)

However, in this embodiment, FIG.
Instruction 10 will take the form as shown by the following instruction (4).

[0032]

## EQU10 ## Operand 3, ADD operand 1, Operand 2 Instruction (4)

Thus, using instruction (4), which is a form of instruction 10 of FIG. 1, prefix 12 includes operand 3, which specifies the destination resource that stores the result of the opcode operation. In contrast, operands 16 and 18 are source operands. Thus, in the current example, the prefix 12 is
Operand 3 receives the sum of the data represented by operands 1 and 2. Again, operand 2 is
Operand 1 preferably specifies a processor resource, whereas it is immediate data or an operand that specifies a processor resource. To accomplish this operation, the operand stage accesses operands 1 and 2 to retrieve the source operand, and the execution unit is controlled differently than prior art rewrite operations. In particular, instead of writing the result of the addition to operand 1 as the destination operand, the result is stored in the resource identified by the prefix operand. Thus, if instruction (3) did not include "operand 3", the appropriate execution unit would add operands 1 and 2 and place the result in operand 1 (or if operand 1 was a register). And register renaming
If g) had been performed, it would be stored in a renamed register). However, in sharp contrast, completion of instruction (3) is implemented such that the storage unit writes the result to operand 3 instead of operand 1. Furthermore, not only is a prefix decoding architecture present in this case, but also because the storage circuit is available in this case, 2
Where only three operands would work, only a little additional hardware is needed
Those skilled in the art will recognize that operands can be included. Therefore, with only a small increase in complexity, it is possible to execute and achieve the instruction (4) more efficiently, while reducing the instruction by 50% compared to the prior art.

The above embodiment considers an instruction prefix that specifies the destination operand to be accessed during rewriting, while the two source operands follow the opcode and are accessed during the opcode stage as in the prior art. Note that
This preferred embodiment results in minimal changes to the architecture for machines already configured to handle two-operand instructions. Further, in an alternative embodiment, the instruction 10 of FIG. 1 may include additional bits, or may be specified externally to the instruction (such as a flag or the like), so that if the specification , The third operand prefix is ignored, in which case the prefix is not considered and the instruction operates according to the two-operand meaning as in the prior art. Still further, regardless of the preferred embodiment having an instruction prefix identifying the destination operand, those skilled in the art will be able to modify the above embodiment so that the instruction prefix is replaced by the source operand instead of the destination operand. Alternative embodiments may be provided in which the operands are specified and one of the operands following the instruction opcode specifies the destination operand. In such alternative embodiments, and with the prefix operand as the source operand, the prefix operand can either contain immediate data or specify a processor resource that stores data for the instruction. Therefore, during the operand stage, one of the two operands is accessed from the instruction prefix operand, and a subsequent rewrite stage stores the result in one of the two operands located within the instruction after the opcode. Will.

It should also be noted that the embodiments described above result in at least two instruction formats not previously present in the X86 microprocessor. For example, consider the schematic designation of the following two instructions.

[0036]

[Equation 11] Memory ← (register) operand (immediate data) Instruction (5)

[0037]

[Expression 12] Memory ← (register) Operand (register) Instruction (6)

Instruction (5), under this implementation, specifies that the memory location is specified as the destination operand in the instruction prefix, and that the operation between the first value in the register and the second value, which is immediate data, is performed. Is shown schematically to receive the results of Again, if it was the preceding X86 instruction set, instead, store the result of the operation in the same register that is the source operand (or in an appropriate rename register), and store the second instruction in its memory location in the source register. Would require copying the contents. Similarly, instruction (6), under this embodiment, specifies that the memory location is specified as the destination operand in the instruction prefix, and that the first value in the register is different from the second value in a register different from this register. It is shown schematically that the result of the operation is received. Again, the prior art typically requires two instructions to accomplish this operation.

Having described the above embodiment, FIG. 3 shows a block diagram of a microprocessor embodiment that can include this embodiment. Referring to FIG. 3, an exemplary data processing system 102 including an exemplary superscalar pipelined microprocessor 110 in which the preferred embodiment is implemented.
Will be described. Of course, it is contemplated that the present embodiment may be utilized with microprocessors of various architectures, so that the system 102 and the microprocessor 11
The 0 architecture is described here only as an example. Accordingly, it is believed that, with reference to the present specification, those of ordinary skill in the art will be able to readily implement the present embodiments within such other microprocessor architectures.

The microprocessor 110 shown in FIG.
Are connected to other system devices via a bus B. In this example, bus B is shown as a single bus, but bus B also represents multiple buses with different speeds and protocols, as is known in conventional computers utilizing the PCI local bus architecture. Of course, the single bus B is shown here merely as an example and for simplicity. System 102 is implemented by a communication port 103 (including a modem port, a modem, a network interface, etc.), a graphic display system 104 (including a video memory, a video processor, a graphic monitor), and typically a dynamic random access memory (DRAM). And the main memory system 105 including the stack 107 and the input device 1
06 (including a keyboard, a position input device, and an interface circuit therefor) and the disk system 10
8 (including hard disk drives, floppy disk drives, and CD-ROM drives). Thus, the system 102 of FIG.
It is considered to correspond to a conventional desktop computer or workstation, as is now widespread in the art. Of course, other system implementations of microprocessor 110 may also benefit from this embodiment, as will be appreciated by those of ordinary skill in the art.

The microprocessor 110 includes a bus interface unit (hereinafter, referred to as BIU) 112 connected to the bus B, and controls communication between the microprocessor 110 and other elements in the system 102. And implement. BIU 112 includes appropriate control and clock electronics to perform this function, includes a write buffer to increase operating speed, and includes timing electronics to synchronize internal microprocessor operation with bus B timing constraints. Microprocessor 1
10 also includes clock generation and control electronics 120, which in this exemplary microprocessor 110 generates an internal clock phase based on the bus clock from bus B, Is selectively programmed in this example as a multiple of the frequency of the bus clock.

As can be seen in FIG. 3, the microprocessor 110 has three levels of internal cache memory, of which the highest level 2 cache 114 is
Are connected to BIU 112. In this example, level 2
Cache 114 is a unified cache and BI
It is configured to receive all cacheable data and cacheable instructions via U112,
Much of the bus traffic emitted by microprocessor 110 is accomplished via level 2 cache 114. Of course, the microprocessor 110
Bus traffic bypassing cache 114 may also be implemented by treating certain bus reads and writes as "non-cacheable." As shown in FIG. 3, the level two cache 114 is connected to two level one caches 116, the level one data cache 116d is dedicated to data, while the level one instruction cache 116i is dedicated to instructions. Power consumption by the microprocessor 110 is minimized by accessing only the level 2 cache 114 only during the appropriate one cache loss of the level 1 cache 116. Further, on the data side, a microcache 118 is provided as a level 0 cache, and in this example, is a completely dual port cache.

As shown in FIG. 3 and described above, microprocessor 110 is of the superscalar type.
In this example, multiple execution units are provided within microprocessor 110 to allow up to four instructions to be executed simultaneously in parallel for a single instruction pointer entry. These execution units are two ALUs 14 that handle conditional jumps, integer operations, and logical operations.
2 ₀ , 142 ₁ , and also includes the FPU 130, two load-store units 140 ₀ , 140 ₁ , and a microsequencer 148. Two load-storage units 140
Utilizes two ports to the microcache 118 for true parallel access to the microcache 118, and also performs load and store operations on registers in the register file 139. Data micro address conversion buffer (referred to as data μTLB) 138
To convert a logical address to a physical address in a conventional manner.

These multiple execution units are controlled via a multiple seven stage pipeline. These stages are as follows.

F Fetch: This stage generates an instruction address and reads an instruction from the instruction cache or instruction memory. PD0 Predecode stage 0: This stage determines the length and start position of up to three fetched X86 type instructions. PD1 Predecode stage 1: This stage extracts the X86 instruction bytes and records them in fixed format for decoding. DC Decode: This stage converts X86 instructions into atomic operations (hereinafter AOps). SC Schedule: This stage assigns up to four AOps to the appropriate execution units. OP Operand: This stage retrieves the register operand pointed to by AOp. EX Execution: This stage runs the execution unit according to the AOp and the retrieved operand. WB rewrite: This stage stores the result of the execution in a register or memory.

Referring again to FIG. 3, the pipeline stages described above are performed by various functional blocks within microprocessor 110. Extraction unit 126
Is the instruction micro address translation buffer (instruction μTLB
The instruction μTLB 122 converts the logical instruction address to a physical address in a conventional manner and supplies it to the level 1 instruction cache 116i. Instruction cache 11
6i generates the instruction data flow and outputs the
6, which in turn supplies the instruction codes to the predecode stage in the desired order. Purely theoretical execution is controlled primarily by the retrieval unit 126 in a manner described in further detail below.

The pre-decoding of the instruction is performed in two parts within the microprocessor 110: a predecode 0 stage 128 and a predecode 1 stage 132.
Is divided into These two stages work as separate pipeline stages and work together to a maximum of 3
It locates up to one X86 instruction and supplies them to decoder 134. For this reason, the predecode stage of the pipeline in microprocessor 110
3 instruction widths. As described above, the pre-decode 0 stage 128 determines the size and location of up to three X86 instructions (which, of course, are of variable length), and thus, has three instruction recognition units ( recogni
zer) and a predecode 1 stage 132
Records multibyte instructions in a fixed-length format to facilitate decoding.

The decode unit 134 in this example includes four instruction decoders, each of which is capable of receiving fixed length X86 instructions from the predecode one stage 132 and generating one to three AOps. AOp is substantially equivalent to a RISC instruction. 4
Three of the three decoders operate in parallel, placing up to nine AOps in a decode queue on the output of decode unit 134 to await scheduling.
The fourth decoder is a reserve for special cases. Scheduler 136 reads up to four AOps from the decode queue on the output of decode unit 134 and assigns these AOps to the appropriate execution units. In addition, operand unit 144 receives and prepares operands for execution. As shown in FIG. 3, the operand unit 144 includes the multiplexer 14
5, the sequencer 144 and the microcode R
A register operand which receives an input from the OM 146 and is used for execution of an instruction is extracted. Further, according to this example, the operand unit performs an operand transfer to send the result ready to be stored to a register, and also performs address generation for load and store type AOps. .

The microsequencer 148, in combination with the microcode ROM 146, controls the ALU 142 and the load-store unit 140 in executing the microcode entry AOp, which is typically the latest AOp to execute in one cycle. In this example, the microsequencer 148 has a microcode ROM 14 to implement this control on microcoded microinstructions.
Control is performed sequentially through these microinstructions stored in 6. Examples of microcoded microinstructions include:
For the microprocessor 110, a complex instruction or a rarely used X86 instruction, i.e., an instruction to modify a segment or control register that handles exceptions and interrupts, and (REP instruction and push all registers) (PUSH) and pop (POP)
There are multi-cycle instructions (like those that do).

The microprocessor 110 also has a JT
An electronic circuit 124 is included to control the operation of the AG scan test and certain built-in self-test functions to ensure the validity of operation of the microprocessor 110 upon completion of manufacture and upon reset or other events.

As will be appreciated by those skilled in the art from the description of the preceding figures as well as the description of FIG. 3, a circuit embodiment that achieves the functions described with reference to FIGS. Can also be incorporated in components similar to those shown. For example, instruction decoding is performed using predecode stage 132 as well as predecode stages 128 and 132. As another example, execution is achieved using a number of execution units such as ALUs 142 ₀ and 142 _1. Further, as another example, the results of the execution are stored in a number of different storage elements, such as register file 139, or main memory subsystem 105.
Various related functions may be further performed by the appropriate electronics shown in FIG.

[0052]

As can be appreciated from the above description, the above-described embodiment significantly improves the prior art with minimal design complexity. Instruction processing is 50 in various cases.
%. Further, such as having an operand specified as a destination operand in the instruction prefix or alternatively as a source operand,
Various alternative embodiments have been described above. Other examples will certainly be comprehensible to those skilled in the art. For example, while the above embodiment benefits from the X86 architecture,
Other microprocessors may benefit as well. Thus, while the invention has been described in detail, various substitutions, modifications, or alternative embodiments thereof may be made from the above description without departing from the scope of the invention, which is defined by the appended claims. Can be achieved.

With respect to the above description, the following items are further disclosed.

(1) A method for operating a processor to process a plurality of instructions, the method comprising the step of receiving one of the plurality of instructions, wherein the instructions comprise a first operand and a second operand The receiving step, determining whether the received instruction includes an operand prefix, wherein the operand prefix identifies a third operand, the determining step, wherein the received instruction identifies an operand prefix. Executing the received instruction to produce a result in response to the determination that the first operand, the second operand, and the third operand
Using the two operands selected from the operands and preventing one of the first operand, the second operand, and the third operand from being selected; and performing the unselected. Storing the result in an operand.

2. The method of claim 1, wherein said third operand includes a destination operand, and wherein said storing comprises storing said result in said destination operand.

3. The method of claim 1, wherein said third operand comprises a non-register destination operand.

(4) The method of claim 3, wherein said non-register destination operand comprises a memory destination operand.

(5) The method of claim 3, wherein said first operand comprises a register operand and said second operand comprises a register operand.

The method of claim 3, wherein said first operand comprises a register operand and said second operand comprises an immediate data value.

The method of claim 3, wherein the instruction further comprises an opcode and at least one offset byte following the non-register destination operand and preceding the opcode.

(8) The method of claim 1, wherein said instruction including an operand prefix is an X86 instruction.

(9) The method of claim 1, wherein execution of said instruction without said operand prefix and including said operand prefix comprises execution of a two operand instruction.

(10) A method of operating a processor to process a plurality of X86 instructions, the method comprising receiving one X86 instruction from the plurality of instructions, wherein the X86 instruction includes a first operand and And receiving the X86 instruction to determine whether the received X86 instruction includes an operand prefix, wherein the operand prefix includes a third operand.
The determining, identifying the operand as a destination operand, using the first operand and the second operand to produce a result in response to the determination that the received instruction includes an operand prefix. Executing the instruction in the destination operand, and storing the result in the destination operand.

(11) The method according to item 10, wherein
The method wherein execution of the X86 instruction including the operand prefix without using an operand prefix comprises execution of a two operand instruction.

(12) A method, circuit, and system for processing a plurality of instructions. In method embodiment 20, the method receives one instruction from the plurality of instructions (2
2). Next, the method determines whether the received instruction includes an operand prefix identifying a third operand (24, 26). In response to determining that the received instruction 10 includes an operand prefix 12, the method uses two operands selected from a first operand, a second operand, and the third operand, And executing the instruction to produce a result such that one of the first operand, the second operand, and the third operand is not selected (28). Next, the method stores the result in the operands that were not selected. Other circuits, systems, and methods are also disclosed and claimed.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a three-operand instruction having an operand prefix, an opcode, and two operands following the opcode.

FIG. 2 is a flow chart of a preferred embodiment of the method of the present invention for detecting and processing three-operand instructions.

FIG. 3 is a functional block diagram of an exemplary data processing system in which a preferred embodiment of the method of the present invention is implemented.

[Explanation of symbols]

10 3 operand instruction 12 prefix 14 opcode 16 first operand 17 second operand 102 data processing system 110 superscalar pipelined microprocessor 112 bus interface unit (BIU) 114 level 2 cache 116 d level 1 data cache 116 i level 1 instruction cache 118 micro Cache 120 Clock generation and control electronics 122 Instruction microaddress translation buffer (instruction μT
LB) 124 JTAG scan test and built-in self-test control electronics 126 Extraction unit 128 Predecode 0 stage 130 Floating point unit 132 Predecode 1 stage 134 Decode unit 136 Scheduler 138 Data micro address conversion buffer (data μTLB) 139 Register file 140 ₀ , 140 ₁ load-storage unit 142 ₀ , 142 ₁ multi-integer arithmetic unit (AL
U) 144 Operand unit 145 Multiplexer 146 Microcode ROM 148 Microsequencer

Claims (1)

[Claims] 1. A method for operating a processor to process a plurality of instructions, the method comprising: receiving one of the plurality of instructions, the instructions comprising a first operand and a second operand. Receiving, comprising: determining whether the received instruction includes an operand prefix, wherein the operand prefix identifies a third operand; determining that the received instruction includes an operand prefix. Executing the received instruction to produce a result in response to the determination of two operands selected from the first operand, the second operand, and the third operand. And the first operand, the second operand, and the third operand Out one but to not be selected, the method comprising steps, and storing the result in the unselected in operand to the execution.