JPH10210464A - Sent image, decoding device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent visual deterioration from appearing on a screen, even when the receiving image data must be partly disused or displayed again by monitoring the changed variable of the receiving image data on a time base and performing the control to selectively disuse or display again the receiving image data, having a small changed variable on the time base based on the monitoring result. SOLUTION: A changed variable detection part 106 and a buffer remaining capacity calculation part 107 monitor the changed variable of an image on a time base and the buffer remaining capacity respectively. Based on these monitoring signals, a decoding control part 108 estimates the occurrence of overflow or underflow of a buffer memory 103 and also estimates the change of the image. Then unavoidable display disturbances are caused to the image that has a small change on the time base. In other words, the receiving image data having a small changed amount on the time base is selectively disused or displayed again, when the receiving image data must be partly disused or displayed again. Thus, visual deterioration can be suppressed against occurrence of the display disturbance.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to video signal processing, and more particularly to a video decoding apparatus for expanding and displaying media such as a compressed moving image operated by a clock independent of a clock of a transmission line.

[0002]

[Prior art]

Literature: "Practical MPEG Textbook", 1995, ASCII Publishing Bureau Conventionally, there is the above-mentioned literature as a compressed moving image transmission literature. This document describes various technologies and problems related to compressed moving image transmission. For example, in the case of an application or the like for entering a public network from a LAN,
It has been pointed out that the supply of the network clock cannot always be expected, and that when the supply of the network clock cannot be received, there are the following problems. That is, in the transmission of a compressed moving image in a state where the network clock is not supplied, if the clocks on the transmission side and the reception side operate independently, the data processing speed differs according to the speed difference. It has been pointed out that.

[0003] However, when the data processing speeds differ as described above, the amount of buffer memory used to temporarily store received data greatly differs depending on the relationship between the processing speeds on the encoder side and the decoding side. For example, if the processing of the encoder is fast, the decoding processing cannot catch up and increases, and in the opposite case, it decreases. In addition, when the buffer becomes empty, there is no new image to be displayed, so "display twice" is required. On the other hand, when the buffer is full, the input new image cannot be held and "dropped frame" Is generated, and visual deterioration is conspicuous.

In order to prevent such a situation, it is necessary to use a clock synchronized between transmission and reception.

In this regard, in the MPEG2 system, a program clock reference value (ProgramClock Reference) is used.
, Hereinafter referred to as PCR).
Ensures clock synchronization. The literature also describes this method. Hereinafter, this method will be described.

[0006] The encoder transmits the PCR created from the reference clock to the decode, counts its own clock in the decode, and compares the count with the transmitted PCR value. If this coincides, it means that clock synchronization is ensured. By controlling the frequency of the clock so that the two values match by a PLL circuit or the like, the clock for transmission and reception can be synchronized.

FIG. 2 shows this configuration. A compressed image take to which a synchronization signal corresponding to PCR is added is input terminal 201.
, And is separated by the sync separation unit 202 into compressed image data and a sync signal. The image data is stored in the buffer memory 203 under the control of the sync separation unit 202. PLL
The unit 204 reproduces a clock based on the synchronization signal from the synchronization separation unit 202. The image data is read from the buffer memory 203 by a read control signal based on this clock, and is decompressed by the video
06. It is read from the display memory 206 at the timing of the display system, and outputs a video signal from the output terminal 207.

As described above, by using the PLL circuit,
Since the clocks in transmission and reception are the same, that is, the amount of writing to the buffer memory (control from the synchronization separation unit 202) and the amount of reading (control of reading from the video decoding unit 205) are the same, the amount of data stored in the buffer is constant. And the above-mentioned overflow does not occur.

[0009]

As described above, the synchronization signal is added to the compressed image data, and the PLL based on the synchronization signal is added.
By configuring the circuit, the clock can be matched between transmission and reception. As a result, "dropped frames" and "display twice" in image display can be prevented.

[0010] However, in a network such as an ATM network in which the transmission delay fluctuates, the transmitted synchronization signal has jitter.

When the delay fluctuation increases, not only the fluctuation cannot be absorbed by the PLL circuit but also the PLL circuit may not lock. In this case, since the clocks between the transmission and reception do not match, the amount of accumulation in the reception buffer increases or decreases in accordance with the speed difference, and "frame drop" due to overflow or "display twice" of the same image due to underflow occurs. Occur. In particular, when there is a large change in the image on the time axis, if "dropped frames" or "display twice", that is, if the display is disturbed, the image quality deteriorates noticeably.

In the conventional technique, a PLL circuit may not be used in order to avoid an increase in the circuit scale due to the addition of a PLL circuit and a residual jitter in a reproduced clock. In this case, the problem of display disorder remains unsolved.

[0013]

According to the present invention, there is provided a receiving buffer for temporarily storing received image data, and a receiving buffer for storing received image data read from the receiving buffer, the clock being different from a clock on a transmitting side. A transmission image decoding apparatus comprising: a decoding means for decoding by means of the following:

That is, (1) a change amount monitoring means for monitoring a change amount on the time axis in the received image data, and (2) a change amount when a part of the received image data needs to be discarded or redisplayed. Decoding control means for controlling the decoding means to selectively discard or redisplay received image data having a small amount of change on the time axis based on the detection result of the monitoring means. In the present invention, even when it is necessary to discard or redisplay a part of the received image data, the received image data with a small amount of change on the time axis can be selectively discarded or redisplayed. Even if such processing is performed on the screen, it is possible to prevent visual deterioration from appearing on the corresponding screen.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION

(A) First Embodiment A first embodiment of a decoding device according to the present invention will be described below.

(A-1) Configuration of the First Embodiment Even if "frame drop" or "display twice" is performed, in the case of a still image which always displays the same image, the image quality is deteriorated even if the display is disturbed. However, if there is a large change in the displayed image on the time axis, it will stand out as image quality degradation.

Therefore, in the video decoding according to this embodiment, when it is necessary to perform “dropping frames” or “display twice”, the video decoding is performed on an image having little change on the time axis. Even if an overflow or the like occurs in the buffer, deterioration of visual image quality is minimized.

FIG. 1 is a flow chart showing the overall configuration of the decoding device according to the first embodiment of the present invention.

As shown in FIG. 1, the decoding device comprises an input terminal 101, a sync separation section 102, a buffer memory 10
3. PLL unit 104, video decoding unit 105, change amount detection unit 106, buffer remaining amount calculation unit 107, decoding control unit 10
8, a display memory 109, and a video signal output terminal 110.

Here, an input terminal 101 is a terminal for inputting compressed image data to which a synchronization signal is added, and the input compressed moving image data is supplied to the synchronization separation unit 102 from the input terminal 101. The synchronization separation unit 102 is means for separating the compressed image data and the synchronization signal. Of the separated signals, the compressed image data is input to the buffer memory 103, and the synchronization signal is input to the PLL unit 104. The compressed image data is stored in the buffer memory 103. Further, the PLL unit 104 reproduces the transmission clock based on the synchronization signal.

The video decoding unit 105 includes a buffer memory 10
3 is a means for expanding the compressed image data read from the third image data. The change amount detection unit 106 is a unit that detects a change in the image on the time axis. The buffer remaining amount calculation unit 107 is a unit for calculating the amount of data stored in the buffer memory 103. The decoding control unit 108 controls the decoding display timing of the video decoding unit 105 based on the decoding end signal from the video decoding unit 105, the image change information from the change amount detection unit 106, and the remaining buffer amount from the remaining buffer calculation unit 107. It is a means to do. The display memory 109 is a memory that holds decoded image data and outputs the decoded image data at display system timing. The video output terminal 110 is a video signal output terminal.

The decoding device according to the embodiment comprises the above means. Among them, the unique means not included in the conventional decoding device shown in FIG.
The three means are a buffer remaining amount calculation unit 107 and a decoding control unit 108. Hereinafter, means specific to such an embodiment will be described.

First, the configuration of the change amount detection unit 106 is shown in FIG. This change amount detection unit 106
3 is a means for detecting the amount of data transferred from 3 to the video decoding unit 105. FIG. 3 shows a configuration for detecting a change in the image on the time axis from the amount of compressed data for one frame of the image.

As shown in FIG. 3, the change amount detecting section 106
Is a read control signal (memory address) input terminal 30
1, a decoding end signal input terminal 302, registers 303 and 305, a subtractor 304, and a change amount output terminal 306.

Here, the register 303 is a register for holding a read address using the decoding end signal as a trigger signal, and the subtractor 304 is for calculating a difference between the read amount one cycle before and a new read amount. is there. In addition,
The register 305 is used to hold the output value of the subtractor 306 using the decoding end signal as a trigger signal.

Next, the configuration of the buffer remaining amount calculation unit 107 will be described. The buffer remaining amount calculation unit 107 is a unit used to monitor the remaining amount of the buffer memory 103, and inputs a write control signal (memory address) and a read control signal (memory address) to a subtracter, Is required.

Next, the configuration of the decoding control unit 108 is shown in FIG. FIG. 4 shows only a portion for controlling the overflow. A similar circuit is separately required for underflow.

As shown in FIG. 4, the decoding control unit 108
Plural input / output terminals (buffer remaining amount input terminal 401, change amount input terminal 402, decoding end signal input terminal 403, data output instruction terminal 415, decoding start instruction output terminal 416)
, Comparators 404 and 405, and a plurality of gate circuits (NA
ND gate 406, AND gates 407, 410, registers 408, 409, 411, 412, NOR gate 4
12, OR gate 414).

Here, the comparator 404 is a comparator for comparing the remaining buffer amount with the threshold value A, and the comparator 405 is a comparator for comparing the change amount with the threshold value B. Note that the NAND gate 406 is the NAN of the two comparators 404 and 405.
It is a means to obtain D. The register 408 is means for delaying the decoding end signal by one clock cycle. Further, the register 409 includes a NAND gate 406
Is held by the decoding end signal. Further, the AND gate 410 is a means for receiving the outputs of the registers 408 and 409 as inputs and obtaining a logical product thereof. In addition, the shift register 411 includes the AND gate 41
Used to delay the output of 0. Further, the register 412 is means for delaying the output of the NAND gate 406 by one cycle of the clock.

(A-2) Operation of First Embodiment (A-2-1) Basic Operation Next, the operation of the decoding device will be described. First, basic operation contents will be described.

When the decoding device inputs the compressed image data to which the synchronization signal has been added to the input terminal 101, the decoding device supplies the input to the synchronization separation unit 102, and separates the compressed image data and the synchronization signal. Next, the decoding device writes the separated compressed image data into the buffer memory 103 at the operation timing of the synchronization separation unit 102, and outputs the synchronization signal to the PLL unit 1
04, and the PLL section 104 reproduces the transmission side clock. The reproduced clock is supplied to the video decoding unit 105.

The decoding device reads the data stored in the buffer memory 103 by using the reproduction clock, and decompresses the data by the video decoding unit 105. When the decompression of one image is completed, a decoding end signal is output and the decompressed image is transferred to the display memory 109 and output at the timing of the display system.

The basic operation of the decoding apparatus has been described above.

(A-2-2) Operation at the Time of Overflow Next, the decoding control operation of the video decoding unit 105, which is a functional unit unique to the decoding apparatus according to the present embodiment, will be described. It should be noted that the change amount detection unit 10 is closely related to this control.
6 and a buffer remaining amount calculation unit 107.
The change amount detection unit 106 is used to detect the change amount of the image on the time axis, and the buffer remaining amount calculation unit 10
Reference numeral 7 is used to calculate a change in the remaining buffer amount that occurs when the PLL unit 104 is not locked to the transmission side clock due to a transmission delay change or the like.

First, the operation of the change amount detector 106 and the buffer remaining amount calculator 107 will be described.

The change amount detection unit 106 is a means for monitoring the amount of change in the image by obtaining the amount of compressed data per frame of the image. The total read amount (memory address) at the end of the frame processing is held.
Then, the subtractor 304 calculates the difference between the total read amount (memory address) obtained by adding the data for one new frame and the total read amount stored in the register 303 up to the previous time, and compresses the image per frame. Get the data. The output of the subtractor 304 is converted into a signal of one decoding cycle by a register 305 using a decoding end signal as a trigger signal, and is output from an output terminal 306 as a change amount of an image on a time axis.

On the other hand, the buffer remaining amount calculation unit 107 obtains the difference between the amount of data written (ie, the memory address on the write side) and the amount of data read (ie, the memory address on the read side) to obtain the buffer. Calculate the remaining amount and output this.

The decoding control unit 108 inputs the decoding end signal output from the video decoding unit 105 together with the change amount and the remaining buffer amount, and generates a decoding start command and a data output command. Here, the decoding start instruction is stored in the buffer memory 103.
The data output command is a command for transferring the decoded image to the display memory 109 for display.

The operation of the decoding control unit 108 executed when the buffer overflows will be described below with reference to FIG.

The decoding control section 108 compares the output of the buffer remaining amount calculation section 107 with a certain threshold value A in the comparator 404, thereby obtaining a threshold value A having a buffer remaining amount.
Is determined. Here, the comparator 4
When the buffer remaining amount exceeds the threshold value A, an alarm signal of “H” level is output to notify that the buffer overflow is near. For example, the decoding processing period of the sixth to ninth frames in FIG. 5 corresponds to this state. Note that a fixed value obtained from the buffer capacity, the reception data rate, and the like is used as the threshold value A.

Further, the decoding control unit 108 includes a comparator 405
By comparing the output of the change amount detection unit 106 with a certain threshold value B, it is determined whether or not the image currently being processed is an image with small image quality deterioration even if the "frame dropped". Also in this case, the comparator 405 outputs an “H” level signal in the case of an image that can be “dropped frame”. For example, in FIG. 5, the decoding processing periods of the fourth and ninth frames indicate this state. Note that a fixed value obtained from the display image size or the like is used as the threshold value B.

Therefore, when the output of the comparator 404 is at the “H” level and the output of the comparator 405 is at the “H” level (that is, the remaining buffer amount exceeds the threshold A, and
If the image can be "dropped", the output is "L"
The level is reached, and it is notified to a subsequent circuit that "dropping out" is required and "dropping out" can be actually performed. Subsequent circuits start the "dropping" operation based on the "L" level signal.

Actually, in order to perform "dropout", the data output command for the image to be dropped is canceled, and a decoding start command to display the next image in place of the "dropout" image is issued. It is necessary to output it ahead of time. Therefore, the AND gate 407 is used for the former purpose.

The AND gate 407 masks (ie, ANDs) the signal obtained by delaying the decoding end signal by one cycle with the output of the NAND gate 406 so that the data output instruction is not transmitted. That is, if the amount of change is equal to or smaller than the threshold B while the buffer remaining amount exceeds the threshold A, the AND gate 407 controls the video decoding unit 105 so that the decompressed image is not output from the video decoding unit 105. A signal is output.

On the other hand, a shift register 411 is used for the latter purpose. The shift register 411 functions to delay the decoding end signal by the time required for the data transfer so as to start a new decoding after the data transfer to the display memory 109 is completed. If no “dropped frame” occurs, this signal becomes a decoding start command. The register 412 and the NOR gate 413 find the falling edge of the output of the NAND gate 406 and generate a decoding start instruction to be added. In the OR gate 414, the normal decoding start instruction of the output of the shift register 411 includes NO
A pulse output from the R gate 413 is added. In this way, a decoding start instruction for starting decoding ahead of time is generated.

By performing the above control, when the remaining buffer capacity becomes large, one image having a small amount of received data is not written in the display memory 109, and instead, the next image is decoded. The data is transferred to the display memory, and a "frame drop" occurs at the time of display.

(A-2-3) Operation at the time of underflow On the other hand, in the case of a buffer underflow, the same circuit is masked so as not to output the "H" pulse in response to the decoding start instruction. This is realized by outputting a data output instruction twice for one decoding process.

(A-3) Effect of the First Embodiment In transmitting a compressed moving image, if the clocks on the transmitting side and the receiving side are independent, the remaining amount of the receiving buffer increases or decreases according to the speed difference. . Reproduction of the clock by the PLL circuit makes it possible to keep the remaining amount of the buffer constant. However, the PLL may not be locked depending on the delay variation of the transmission line. In this case, the clock becomes independent, so that the remaining buffer capacity increases and decreases. Here, when the buffer memory overflows or underflows, the "frame drop" or "2"
Degree display "occurs, and the display is disturbed. Such display disturbance is noticeable in an image having a large change on the time axis, but is not significant in an image having a small change.

Therefore, the decoding device having the above configuration is used.

FIG. 6 explains the effect brought about by the first embodiment. Here, a state where the clock frequency of the receiving side is lower than the clock frequency of the transmitting side and a buffer overflow occurs is shown. The upper row shows the state of the buffer. When the remaining amount of the buffer indicated by the polygonal line exceeds the overflow level, "dropping out" occurs. The lower part shows the received image and the display image. Since the receiving side clock frequency is low, the number of display frames is lower than the number of received frames.

In the conventional method, "dropping out" occurs when a buffer overflow occurs. For this reason, "dropped frame" occurs in the received image "5" and the received image "10" in FIG. These images have a large difference from the immediately preceding received images “4” and “9”. For this reason, in the display image, a discontinuous portion appears in the movement of the black circle (arrow portion),
Image quality is degraded.

Therefore, in the first embodiment, as described above, when an image whose change amount is smaller than the threshold value B is received in a state where the buffer remaining amount exceeds the threshold value A, the image is dropped. To control. That is, in FIG. 6, the amount of change of the received image “4” with respect to the received image “3” and the amount of change of the received image “8” with respect to the received image “7” are smaller than the threshold value B. Since the size is large, the received images “4” and “8” are “dropped”. As a result, a display image as shown in FIG. 6 is obtained, and no unnaturalness appears in the movement of the black circle.

As described above, according to the first embodiment,
The amount of change of the image on the time axis is monitored by the change amount detection unit 106, the remaining amount of the buffer is monitored by the buffer remaining amount calculation unit 107, and the decoding control unit 108 controls the buffer memory 1 based on these signals.
The occurrence of overflow or underflow of 03 and the change of the image are estimated, and the inevitable display disturbance is performed on the image with little change on the time axis. As a result, it is possible to suppress visual deterioration when display disturbance occurs.

In the first embodiment, the fact that the compressed image data is usually created based on the difference data between the frames of the image is used, and the change of the image on the time axis is calculated from the received data amount. I guess. For this reason, the above effect is obtained with a simple configuration as shown in FIG. The change of the image on the time axis can be known from other than the received data amount.
For example, there is a method of actually calculating an inter-frame difference using a motion vector value, a transform coefficient, and a decoded image obtained when decoding compressed image data. In the embodiment of the present invention, the amount of received data is described as a target. However, changes in an image may be estimated using these other methods.

(B) Second Embodiment Hereinafter, a second embodiment of the decoding device according to the present invention will be described.

(B-1) Configuration of the Second Embodiment In the first embodiment, image change information on the time axis,
The buffer remaining amount is independently compared with a threshold value by a comparator to perform control such as "dropping out frames". In the second embodiment, however, the two types of information are handled integrally and " The case of performing control such as "drop" will be described.

As the overall configuration of the second embodiment, the configuration shown in FIG. 1 is used as in the first embodiment, but a different configuration is used as the decoding control unit 108.

FIG. 7 shows a decoding control unit 1 according to the second embodiment.
08 is shown. FIG. 7 shows parts corresponding to those in FIG. 4 with corresponding reference numerals, and is configured by the same circuit components except that a ROM 704 is used instead of the comparators 404 and 405 and the NAND 406. .

Here, the ROM 704 stores control information determined according to the remaining amount of the buffer and the amount of change, so that adaptive "drop-out" control according to the relationship between the two amounts can be realized. . For example, when the remaining buffer amount is large, "dropout" is executed when the change amount is relatively large, and when the buffer amount is small, "dropout" is executed even when the change amount is extremely small. It is supposed to be.
Note that FIG. 7 shows only the control part for the overflow as in the case of FIG. 4, and a similar circuit is separately required for the underflow.

Incidentally, the decoding control unit 108 shown in FIG.
A buffer remaining input terminal 701, an image change amount input terminal 702 on the time axis, a decoding end signal input terminal 703,
ROM 704 that inputs the remaining buffer and the amount of change, A that receives the output of register 708 and the output of ROM 704
ND gate 707, register 708 for delaying the decoding end signal by one clock cycle, register 709 for holding the output of ROM 704 with the decoding end signal, register 7
AND gate 71 which receives the outputs of 08 and 709 as inputs
0, a shift register 711 that delays the output of the AND gate 710, a register 712 that delays the output of the ROM 704 by one clock cycle, and a NOR gate 71 that receives the output of the ROM 704 and the inverted output of the register 712 as inputs.
3. The output of the NOR gate 713 and the shift register 711
An OR gate 714 that receives the output of the data input, an output terminal 715 for a data output instruction, and an output terminal 716 for a decoding start instruction.

(B-2) Operation of the Second Embodiment The basic operation of the second embodiment is described in the first embodiment.
This is the same as the embodiment. Therefore, here, only the operation of the decoding control unit 108 having a different circuit configuration will be described.

Also in the second embodiment, the decoding control unit 1
08 generates a decoding start command and a data output command from the change amount, the remaining buffer amount, and the decoding end signal. A circuit block specific to the second embodiment provided for this purpose is a ROM block.
The ROM 704 generates an original signal for generating “dropped frame” from the amount of change and the remaining amount of the buffer.

When this signal is at the "L" level, a "frame drop"
Happens. The AND gate 707 masks a signal obtained by delaying the decoding end signal by one cycle with this signal (AND)
By doing so, the data output instruction is not sent. The AND gate 710 masks (AND) a signal obtained by delaying the decoding end signal by one cycle with a signal obtained by delaying this signal by one decoding cycle.

The shift register 711 includes the display memory 10
The operation of delaying the decoding end signal for the time required for the data transfer so that a new decoding is started after the data transfer to the N.9 is completed. Register 712 and NOR gate 713
Now, find the falling edge of the output of the ROM 704,
The OR gate 714 adds a new pulse to the output of the shift register 709 to generate a decoding start instruction.

As described above, in the second embodiment, the ROM
It is characterized in that the control of “dropped frames” is performed in 704 based on the relationship between the change amount and the remaining buffer amount. With this configuration, it is possible to adaptively determine the "dropped frame" for the remaining buffer amount. For example, at the stage where the remaining buffer amount is relatively small, "dropout" is performed even if the amount of change is extremely small, and at the stage where the remaining buffer amount is large, "dropout" is executed even when the change amount is relatively large.

(B-3) Effect of Second Embodiment As described above, according to the second embodiment, the decoding control unit 10
8, the control such as “dropping frames” is adaptively performed based on an arbitrary relationship between both the remaining buffer amount and the change amount, so that the image quality degradation is a visually noticeable still image or visually noticeable. It is also possible to set an execution reference for “dropping frames” based on whether the moving image is difficult. For example,
In the case of an image that is close to a still image, even if the change of the image is very small, “dropout” is executed, so that the visual deterioration can be made less noticeable.

(C) Other Embodiments In the above embodiment, the case where the compressed image data is transmitted via the transmission path has been described. However, the present invention is not limited to this. It can be applied to the case of receiving.

In the above-described embodiment, the case where a moving image is transmitted has been described. However, the present invention can be applied to a case where an encoded still image is decoded.

[0069]

As described above, according to the present invention, a receiving buffer for temporarily storing received image data and a decoding for decoding the received image data read from the receiving buffer with a clock different from the clock on the transmitting side. When it is necessary to discard or redisplay a part of the received image data in the transmission image decoding apparatus including the decoding means, the received image data having a small amount of change on the time axis is selectively discarded or redisplayed. By doing so, it is possible to prevent the visual characteristics of the display screen from deteriorating during the execution of the processing.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an embodiment of a transmission image decoding device.

FIG. 2 is a block diagram illustrating a configuration of a conventionally used transmission image decoding device.

FIG. 3 is a block diagram illustrating a configuration of a change amount detection unit in FIG. 1;

FIG. 4 is a block diagram illustrating a configuration of a decoding control unit according to the first embodiment.

FIG. 5 is a time chart showing an operation relationship of each unit in FIG. 1;

FIG. 6 is an explanatory diagram showing a relationship between a buffer remaining amount and a display image.

FIG. 7 is a block diagram illustrating a configuration of a decoding control unit according to a second embodiment.

[Explanation of symbols]

102: synchronization separation unit; 103: buffer memory; 104
... PLL unit, 105 ... Video decoding unit, 106 ... Change amount detection unit, 107 ... Buffer remaining amount calculation unit, 108 ... Decoding control unit, 109 ... Display memory, 404, 405 ... Comparator, 4
06 ... NAND gate, 704 ... ROM.

Claims (4)

[Claims] 1. A transmission image decoding apparatus comprising: a reception buffer that temporarily stores received image data; and a decoding unit that decodes the received image data read from the reception buffer using a clock different from a clock on a transmission side. A change amount monitoring means for monitoring a change amount on the time axis in the received image data; and when it becomes necessary to discard or redisplay a part of the received image data, based on a detection result of the change amount monitoring means. And a decoding control means for controlling the decoding means so as to selectively discard or redisplay received image data having a small amount of change on the time axis. 2. The apparatus according to claim 1, further comprising: a data remaining amount monitoring unit that monitors a data remaining amount of the reception buffer, wherein the decoding control unit determines the received image based on a monitoring result of the change amount monitoring unit and the data remaining amount monitoring unit. 2. The transmission image decoding apparatus according to claim 1, wherein the necessity of discarding or redisplaying the data is determined. 3. The transmission image decoding apparatus according to claim 1, wherein the change amount monitoring unit calculates a change amount of the image on the time axis from a data amount of the received image data. 4. The decoding control means according to claim 1, wherein said decoding control means stores control information for each of an arbitrary combination of a buffer remaining amount and a change amount in a control information storage means. 3. The transmission image decoding device according to item 1.