JPH10209871A - D/a converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the D/A converter that provides an analog output signal via a buffer amplifier in which a D/A conversion speed is stably increased. SOLUTION: Digital input signals D0-Dn-1 are given in parallel to a plurality of D/A converter sections 21 and a reference voltage being an equal division of a voltage between a high level reference power supply VDD and a low level reference power supply GND is fed to a plurality of the D/A converter sections 21. A plurality of buffer amplifiers 22 receive analog signals outputted from the D/A conversion sections 21. A selection circuit 3 selects and outputs an analog output signal Aout corresponding to the digital signal among output signals of a plurality of the buffer amplifiers 22 based on a signal Dn of high- order bits of the digital input signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a D / A converter for converting a digital signal into an analog signal.

In recent years, digital processing techniques for converting an analog signal into a digital signal for processing have been used in increasingly diverse fields. In connection with this, in the D / A converter used for digital control, the speed of the digital processing system has been required to increase the conversion speed.

[0003]

2. Description of the Related Art An example of a conventional D / A converter is shown in FIG. Digital signals D0 to Dn are input to an (N + 1) -bit D / A conversion unit 1, and the D / A conversion unit 1 converts the digital signals D0 to Dn into analog signals, and supplies the analog signals to a buffer amplifier 2 composed of an operational amplifier. Output.

[0004] The buffer amplifier 2 amplifies an input analog signal and outputs it as an analog signal Aout having sufficient load driving capability. A phase compensation capacitor Cc is connected between the input and output terminals of the inverting amplifier constituting the output stage of the buffer amplifier 2.

In the D / A converter configured as described above,
For example, assuming that the power supply VDD is supplied as a high-potential-side reference power supply and the ground GND level is supplied as a low-potential-side reference power supply, for example, as shown in FIG. ”To all“ 1 ”, the output signal A1 of the D / A converter 1
, The rising speed of the analog output signal Aout depends on the operation speed of the buffer amplifier 2, and the transition delay time until the analog output signal Aout changes from 0 V to VDD. t
Requires one.

[0006]

The analog output signal Aou
In order to reduce the transition delay time t1 of t, it is necessary to improve the operation speed of the buffer amplifier 2. In order to improve the operation speed of the buffer amplifier 2, it is effective to reduce the capacitance value of the phase compensation capacitance Cc. That is, as shown in FIG. 12, as the capacitance value of the phase compensation capacitor Cc decreases, the gain of the output signal of the buffer amplifier 2 with respect to the high-frequency input signal can be improved, and the operation speed can be improved. .

However, when the frequency of the input signal increases, the phase delay of the output signal with respect to the input signal increases due to the delay of the buffer amplifier, and this output signal is fed back.

When the gain of the buffer amplifier 2 is equal to or greater than 0 dB when the phase delay of the output signal exceeds 180 degrees, a positive feedback operation is performed and the buffer amplifier 2 oscillates.

Therefore, if the operation of the buffer amplifier 2 is to be speeded up, it is easy to oscillate, and it has been difficult to improve the output speed of the analog output signal Aout.
An object of the present invention is to provide a D / A converter that outputs an analog output signal via a buffer amplifier and that can stably increase the D / A conversion speed.

[0010]

FIG. 1 is a diagram for explaining the principle of claim 1. That is, the plurality of D / A converters 21 receive the digital input signals D0 to Dn-1 in parallel, and simultaneously input the high-potential-side reference power supply VDD and the low-potential-side reference power supply GND.
Is supplied. The analog signals output from the D / A converter 21 are input to the plurality of buffer amplifiers 22, respectively. Selection circuit 23
Selects an analog output signal Aout corresponding to the digital input signal from the output signals of the plurality of buffer amplifiers 22 based on the upper bit signal Dn of the digital input signal.

According to a second aspect of the present invention, the buffer amplifier includes an operational amplifier having an N-channel MOS transistor as an input transistor in a D / A converter operating in a high-potential reference voltage range among the plurality of D / A converters. And an operational amplifier having a P-channel MOS transistor as an input transistor is connected to the D / A converter operating in the reference voltage range on the low potential side.

According to a third aspect of the present invention, in the buffer amplifier, an operational amplifier having an NPN transistor as an input transistor is connected to a D / A converter operating in a high-potential reference voltage range among the plurality of D / A converters. The D / A converter operating in the low-potential-side reference voltage range is connected to an operational amplifier using a PNP transistor as an input transistor.

According to a fourth aspect of the present invention, the plurality of D / A converters are 2 ^m and a digital input signal excluding the upper m bits of the n-bit digital input signal is inputted.
The selection circuit selects and outputs an analog output signal corresponding to the digital input signal from among the output signals of the plurality of buffer amplifiers based on a higher-order m-bit digital input signal.

According to the first aspect, when selection of the output signal of the buffer amplifier 22 is switched by the selection circuit 23 based on the digital input signals D0 to Dn, the analog output signal Aout output from the selection circuit 23 is changed. Is instantaneously switched to an analog output signal within the range of the reference voltage of the D / A converter 21 connected to the buffer amplifier 22, and then the output of the buffer amplifier 22 based on the output signal of the D / A converter 21 The signal is output as an analog output signal Aout based on the digital input signals D0 to Dn.

According to the second and third aspects, when an output signal of each operational amplifier is selected based on a digital input signal, a D / A converter that makes a full swing within a reference voltage range is configured. According to the fourth aspect, the output signal of the buffer amplifier based on the output signals of the 2 ^m D / A converters is selected based on the upper m bits of the digital input signal.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) FIG. 2 shows an embodiment of the present invention.
1 shows a first embodiment of a + 1-bit D / A converter.

First and second D / A converters 11a, 11
b is input with n-bit digital input signals D0 to Dn-1. The power supply VDD is supplied to the first D / A converter 11a as a high-potential-side reference voltage, and VDD / 2 is supplied as a low-potential-side reference voltage. The power supply VDD / 2 is supplied to the second D / A converter 11b as a high-potential-side reference voltage, and the ground GND level is supplied as a low-potential-side reference voltage.

The analog output signal of the first D / A converter 11a changes in the range of VDD / 2 to VDD based on the digital input signals D0 to Dn-1, and is formed by an operational amplifier. The signal is input to the buffer amplifier 12a.

The analog output signal of the second D / A converter 11b changes in the range from ground GND level to VDD / 2 based on the digital input signals D0 to Dn-1,
The signal is input to a second buffer amplifier 12b composed of an operational amplifier.

The first and second buffer amplifiers 12
a and 12b have the same operation speed as that of the buffer amplifier of the conventional example, and have the first and second D / A converters 11 and 12b.
a, b buffer the analog output signal,
The output signals OUT1 and OUT2 are output to the selection circuit 13.

The digital input signal Dn of the most significant bit is input to the selection circuit 13, and if the digital input signal Dn is at H level, the first buffer amplifier 12a
Is output as the analog output signal Aout, and if the digital input signal Dn is at the L level, the output signal OUT2 of the second buffer amplifier 12b is output as the analog output signal Aout.

As shown in FIG. 3, for example, as shown in FIG. 3, the selection circuit 13 conducts a transfer gate 14 which is turned on depending on whether the digital input signal Dn is at H level or L level.
a and 14b.

In the D / A converter configured as described above, when the most significant bit of the digital input signal Dn is “1”, the output signal OUT 1 of the first buffer amplifier 12 a is output by the selection circuit 13. The selected analog output signal Aout which changes in the range of VDD / 2 to VDD is output.

When the most significant bit of the digital input signal Dn is "0", the output signal OUT2 of the second buffer amplifier 12b is selected by the selection circuit 13, and the level of VDD / 2 is changed from the ground GND level. An analog output signal Aout varying in the range is output.

The operation when the digital input signals D0 to Dn shift from all "0" to all "1" will be described with reference to FIG. 4. When the digital input signals D0 to Dn are all "0", D / A The output signal OUT2 of the ground GND level output from the second buffer circuit 12b based on the output signal of the converter 11b is selected by the selection circuit 13 and output as the analog output signal Aout.

When the digital input signals D0 to Dn switch from all "0" to all "1", the selection circuit 13
As a result, the analog output signal Aout is switched from the output signal OUT2 of the second buffer amplifier 12b to the output signal OUT1 of the first buffer amplifier 12a.

Then, the analog output signal Aout is instantaneously raised from the ground GND level to the VDD / 2 level. Next, the output signal of the D / A converter 11a is raised to the VDD level, and the output signal OUT1 of the first buffer amplifier 11a is changed from the VDD / 2 level to the VDD level based on the output signal of the D / A converter 11a. The output signal OUT1 is output as an analog output signal Aout.

Then, the analog output signal Aout becomes VDD /
A transition delay time t2 from the transition from the second level to the VDD level is の of the transition delay time t1 of the conventional example. Therefore, when the digital input signals D0 to Dn switch from all "0" to all "1", the transition delay time until the analog output signal Aout transitions from the ground GND level to the VDD level is substantially t2, Can be reduced to almost half.

Also, when the digital input signals D0 to Dn switch from all "1" to all "0", the analog output signal Aout is first instantaneously lowered from the VDD level to the VDD / 2 level, and then the second output signal is output. An analog output signal Aout based on the digital input signals D0 to Dn is output based on the output signal OUT2 of the buffer amplifier 12b.

With the D / A converter configured as described above, the following operational effects can be obtained. (A) When the most significant bit signal Dn of the digital input signals D0 to Dn is inverted from “0” to “1”, the output signal OUT2 of the second buffer amplifier 12b, which is output as the analog output signal Aout, becomes the second signal. One buffer amplifier 1
The output signal OUT1 is instantaneously switched to the output signal 2a, and the analog output signal Aout is instantly switched from the potential between the ground GND level and the VDD / 2 level to the potential between the VDD / 2 level and the VDD level.

Next, the output signal O of the first buffer amplifier 12a based on the output signal of the first D / A converter 11a
Since the UT 1 is output as the analog output signal Aout, the D / A conversion speed can be increased without increasing the operating speed of the buffer amplifiers 12a and 12b. In particular, when the analog output signal Aout shifts from the vicinity of the ground GND level to the vicinity of the VDD level based on the digital input signals D0 to Dn, the D / A conversion speed is significantly increased. (B) When the signal Dn of the most significant bit of the digital input signals D0 to Dn is inverted from “1” to “0”, the output signal OUT1 of the first buffer amplifier 12a output as the analog output signal Aout is output. Second buffer amplifier 1
2b, the output signal OUT2 is instantaneously switched, and the analog output signal Aout is instantaneously switched from the potential between the VDD level and the VDD / 2 level to the potential between the ground GND level and the VDD / 2 level.

Next, the output signal O of the second buffer amplifier 12b based on the output signal of the second D / A converter 11b
Since the UT 2 is output as the analog output signal Aout, the D / A conversion speed can be increased without increasing the operation speed of the buffer amplifiers 12a and 12b. In particular, based on the digital input signals D0 to Dn, the analog output signal Aout changes from the vicinity of the VDD level to the ground G.
When shifting to the vicinity of the ND level, the D / A conversion speed is significantly increased. (Second Embodiment) FIG. 5 shows a case where the first buffer amplifier 12a is composed of an operational amplifier composed of a MOS transistor and an N-channel MOS transistor is an input transistor. The buffer amplifier 12b of FIG. 1 is constituted by an operational amplifier composed of a MOS transistor, and a P-channel MOS transistor is used as an input transistor.

The first buffer amplifier 12a shown in FIG.
The power supply VDD is supplied to the sources of the P-channel MOS transistors Tr1 and Tr2, and the gates of both transistors Tr1 and Tr2 are connected to each other.

The gates of the transistors Tr1 and Tr2 are
The drain of the transistor Tr1 and the drain of the N-channel MOS transistor Tr3 are connected, and the drain of the transistor Tr2 is connected to the drain of the N-channel MOS transistor Tr4.

The sources of the transistors Tr3 and Tr4 are:
It is connected to the ground GND via the current source 15a. The drains of the transistors Tr2 and Tr4 are connected to the inverting amplifier 1
6a, and the output signal OUT1 is output from the inverting amplifier 16a. The inverting amplifier 16a
Operates so as to lower the output voltage OUT1 when the input voltage increases and to increase the output voltage OUT1 when the input voltage decreases.

The output signal of the first D / A converter 11a is input to the gate of the transistor Tr4 as an input signal IN1, and the output signal OUT1 of the inverting amplifier 16a is input to the gate of the transistor Tr3.

In the first buffer amplifier 12a configured as described above, when the voltage level of the input signal IN1 decreases and the gate-source voltage of the transistor Tr4 falls below the threshold, the transistor Tr4 is turned off. , The output signal OUT1 equal to the voltage level of the input signal IN1 is not output.

However, since a signal in the range from VDD / 2 level to VDD level is input as the input signal IN1, the gate-source voltage of the transistor Tr4 does not fall below the threshold value of the transistor Tr4. The first buffer amplifier 12a can be used at an input level that allows normal and high-speed operation.

The second buffer amplifier 12b shown in FIG.
The sources of the P-channel MOS transistors Tr5 and Tr6 are connected to the power supply VDD via the current source 15b. The drain of the transistor Tr5 is connected to the gates of the N-channel MOS transistors Tr7 and Tr8 and the drain of the transistor Tr7, and the sources of the two transistors Tr7 and Tr8 are connected to ground GND.

The drain of the transistor Tr6 is connected to the drain of the transistor Tr8 and to the input terminal of the inverting amplifier 16b. The inverting amplifier 16b operates similarly to the inverting amplifier 16a, and outputs an output signal OUT2 from the inverting amplifier 16b.

The output signal of the second D / A converter 11b is input as an input signal IN2 to the gate of the transistor Tr6, and the output signal OUT2 of the inverting amplifier 16b is input to the gate of the transistor Tr5.

In the second buffer amplifier 12b thus configured, when the voltage level of the input signal IN2 rises and the gate-source voltage of the transistor Tr6 falls below the threshold, the transistor Tr6 is turned off. , The output signal OUT2 equal to the voltage level of the input signal IN2 is not output.

However, the ground G is used as the input signal IN2.
Since a signal in the range from the ND level to the VDD / 2 level is input, the gate-source voltage of the transistor Tr6 does not fall below the threshold value of the transistor Tr6, and the second buffer amplifier 12b operates normally. And it can be used at an input level that can operate at high speed.

Therefore, by using the first and second buffer amplifiers 12a and 12b as described above, a D / A converter that fully swings between the ground GND level and the VDD level can be configured. . (Third Embodiment) FIG. 7 shows a case where the first buffer amplifier 12a is constituted by an operational amplifier composed of a bipolar transistor and an NPN transistor is used as an input transistor. Amplifier 1
2b shows a case in which an operational amplifier composed of bipolar transistors is used, and a PNP transistor is used as an input transistor.

The first buffer amplifier 12a shown in FIG.
The power supply VDD is supplied to the emitters of the PNP transistors Tr9 and Tr10, and the bases of both transistors Tr9 and Tr10 are connected to each other.

The bases of the transistors Tr9 and Tr10 are connected to the transistor Tr9 and the NPN transistor Tr1.
The collector of the transistor Tr10 is connected to the collector of an NPN transistor Tr12.

The emitters of the transistors Tr11 and Tr12 are connected to the ground GND via the current source 15c. The collectors of the transistors Tr10 and Tr12 are connected to the input terminal of the inverting amplifier 16c, and the output signal OUT1 is output from the inverting amplifier 16c. The inverting amplifier 16c outputs the output voltage O when its input voltage increases.
UT1 is lowered, and when its input voltage is lowered, it operates to raise output voltage OUT1.

The output signal of the first D / A converter 11a is input to the gate of the transistor Tr12 as an input signal IN3, and the output signal OUT1 of the inverting amplifier 16c is input to the gate of the transistor Tr11.

In the first buffer amplifier 12a configured as described above, when the voltage level of the input signal IN3 decreases and the base-emitter voltage of the transistor Tr12 falls below the threshold, the transistor Tr12 is turned off. , Output signal OU equal to the voltage level of input signal IN3.
T1 is not output.

However, since a signal in the range of VDD / 2 level to VDD level is input as the input signal IN3, the base-emitter voltage of the transistor Tr12 does not fall below the threshold value of the transistor Tr12. The first buffer amplifier 12a can be used at an input level that allows normal and high-speed operation.

The second buffer amplifier 12b shown in FIG.
The emitters of the PNP transistors Tr13 and Tr14 are connected to a power supply VDD via a current source 15d. The collector of the transistor Tr13 is an NPN transistor Tr15
, Tr16 and the collector of the transistor Tr15, and the emitters of both transistors Tr15, Tr16 are connected to ground GND.

The collector of the transistor Tr14 is connected to the collector of the transistor Tr16 and to the input terminal of the inverting amplifier 16d. The inverting amplifier 16d operates similarly to the inverting amplifier 16c, and outputs an output signal OUT2 from the inverting amplifier 16d.

The output signal of the second D / A converter 11b is input to the base of the transistor Tr14 as an input signal IN4, and the output signal OUT2 of the inverting amplifier 16d is input to the base of the transistor Tr13.

In the second buffer amplifier 12b thus configured, when the voltage level of the input signal IN4 rises and the voltage between the base and the emitter of the transistor Tr14 falls below the threshold, the transistor Tr14 is turned off. , Output signal OU equal to the voltage level of input signal IN4.
T2 is not output.

However, the ground G is used as the input signal IN4.
Since a signal in the range of ND level to VDD / 2 level is input, the base-emitter voltage of the transistor Tr14 does not fall below the threshold value of the transistor Tr14, and the second buffer amplifier 12b normally operates. And it can be used at an input level that can operate at high speed.

Therefore, by using the first and second buffer amplifiers 12a and 12b as described above, a D / A converter that fully swings between the ground GND level and the VDD level can be configured. . (Fourth Embodiment) FIG. 6 shows four n-2 bits D /
A conversion units 17a to 17d and buffer amplifiers 18a to 1
8d and the selection circuit 19, an n + 1 bit D /
1 shows an embodiment in which an A converter is configured.

That is, the D / A converters 17a to 17
In d, the digital input signals D0 to Dn excluding the upper two bits of the digital input signals D0 to Dn of n + 1 bits
-2 is input.

The power supply VDD is supplied to the D / A converter 17a as a high-potential-side reference voltage, and 3VDD / 4 is supplied as a low-potential-side reference voltage. To the D / A converter 17b, 3VDD / 4 is supplied as a high-potential-side reference voltage, and VDD / 2 is supplied as a low-potential-side reference voltage.

The D / A converter 17c is supplied with VDD / 2 as a high-potential-side reference voltage and VDD / 4 as a low-potential-side reference voltage. VDD / 4 is supplied to the D / A conversion section 17d as a high-potential-side reference voltage, and the ground GND level is supplied as a low-potential-side reference voltage.

The output signals of the D / A converters 17a to 17d are buffered by buffer amplifiers 18a to 18d and output to the selection circuit 19. The buffer amplifiers 18a and 18b use the circuit shown in FIG. 5 or FIG. 7, and the buffer amplifiers 18c and 18d use the circuit shown in FIG. 6 or FIG.

The selection circuit 19 receives digital input signals Dn−1 and Dn of the upper 2 bits. And
When the digital input signals Dn and Dn-1 are "1, 1", the output signal of the buffer amplifier 18a is selected and output as the analog output signal Aout.

When the digital input signals Dn and Dn−1 are “1, 0”, the selection circuit 19 outputs
8b is selected and output as an analog output signal Aout.

When the digital input signals Dn and Dn-1 are "0, 1", the selection circuit 19
8c is selected and output as an analog output signal Aout.

When the digital input signals Dn and Dn−1 are “0, 0”, the selection circuit 19
The 8d output signal is selected and output as an analog output signal Aout.

In the D / A converter configured as described above,
Any one of the output signals of the four buffer amplifiers 18a to 18d is selected and output by the selection circuit 19 based on the higher-order 2 bits of the digital input signals Dn and Dn-1. The output signal Aout can be set to a level closer to the analog output signal Aout to be output based on the digital input signals D0 to Dn.

Therefore, the operation speed can be further improved as compared with the first to third embodiments. Also,
If the number of D / A converters and buffer amplifiers is further increased, the operation speed can be further improved. At this time, if the number of D / A converters and buffer amplifiers is 2 ^m , the upper m bits of the digital input signals D0 to Dn are input to the selector, and the output of any one of the 2 ^m buffer amplifiers is output. A signal may be selected, and digital input signals D0 to Dn-m of lower nm bits may be input to each D / A converter.

The technical ideas that can be grasped from the above embodiment other than the above-described claims are described below together with their effects. (1) In claim 4, the plurality of D / A converters are 2
^m , and a digital input signal excluding the upper m bits of the n bits of the digital input signal is input. The selection circuit outputs the output signals of the plurality of buffer amplifiers based on the higher m bits of the digital input signal The buffer amplifier selects and outputs an analog output signal corresponding to the digital input signal from among the D / A converters. The D / A converter outputs a high-potential output voltage among the plurality of D / A converters. An operational amplifier using an N-channel MOS transistor as an input transistor was connected, and an operational amplifier using a P-channel MOS transistor as an input transistor was connected to the D / A converter that outputs a low potential output voltage. D fully swinging between the high-potential-side reference voltage and the low-potential-side reference voltage
The operating speed of the / A converter can be improved. (2) In claim 4, the plurality of D / A converters are 2
^m , and a digital input signal excluding the upper m bits of the n bits of the digital input signal is input. The selection circuit outputs the output signals of the plurality of buffer amplifiers based on the higher m bits of the digital input signal The buffer amplifier selects and outputs an analog output signal corresponding to the digital input signal from among the D / A converters. The D / A converter outputs a high-potential output voltage among the plurality of D / A converters. An operational amplifier using an NPN transistor as an input transistor was connected, and an operational amplifier using a PNP transistor as an input transistor was connected to a D / A converter that outputs a low potential output voltage. The operation speed of the D / A converter that makes a full swing between the high-potential-side reference voltage and the low-potential-side reference voltage can be improved.

[0068]

As described above in detail, the present invention relates to a D / A converter which outputs an analog output signal via a buffer amplifier, and which can stably increase the D / A conversion speed. Can be provided.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a block diagram showing a first embodiment.

FIG. 3 is a circuit diagram illustrating a selection circuit according to the first embodiment.

FIG. 4 is a waveform chart showing the operation of the first embodiment.

FIG. 5 is a circuit diagram illustrating a buffer amplifier according to a second embodiment.

FIG. 6 is a circuit diagram illustrating a buffer amplifier according to a second embodiment.

FIG. 7 is a circuit diagram illustrating a buffer amplifier according to a third embodiment.

FIG. 8 is a circuit diagram illustrating a buffer amplifier according to a third embodiment.

FIG. 9 is a block diagram showing a fourth embodiment.

FIG. 10 is a circuit diagram showing a conventional example.

FIG. 11 is a waveform chart showing the operation of the conventional example.

FIG. 12 is a diagram illustrating frequency characteristics and phase characteristics of a buffer amplifier.

[Explanation of symbols]

 Reference Signs List 21 D / A converter 22 Buffer amplifier 23 Selection circuit D0 to Dn-1 Digital input signal Aout Analog input signal VDD High-potential-side reference power supply GND Low-potential-side reference power supply

Claims (4)

[Claims] 1. A D / A converter for converting a digital input signal into an analog signal by a D / A conversion unit and outputting the analog signal as an analog output signal via a buffer amplifier, wherein the digital input signal is A plurality of D / A converters that are supplied in parallel and are supplied with a reference voltage obtained by equally dividing the potential difference between the high-potential-side reference power supply and the low-potential-side reference power supply; A plurality of buffer amplifiers to each of which an analog signal is input, based on a signal of an upper bit of the digital input signal,
A selection circuit for selecting and outputting an analog output signal corresponding to the digital input signal from the output signals of the plurality of buffer amplifiers. 2. The method according to claim 1, wherein the buffer amplifier includes a plurality of D / Ds.
D / which operates in the reference voltage range on the high potential side in the A conversion unit
An operational amplifier using an N-channel MOS transistor as an input transistor is connected to the A converter, and an operational amplifier using a P-channel MOS transistor as the input transistor is connected to the D / A converter operating in the reference voltage range on the lower potential side. The D / A converter according to claim 1, wherein: 3. The buffer amplifier according to claim 1, wherein the plurality of D /
D / which operates in the reference voltage range on the high potential side in the A conversion unit
An operational amplifier having an NPN transistor as an input transistor is connected to the A converter, and an operational amplifier having a PNP transistor as an input transistor is connected to the D / A converter operating in the low potential side reference voltage range. The D / A converter according to claim 1. 4. The method according to claim 1, wherein the plurality of D / A conversion units are 2 ^m , and a digital input signal excluding upper m bits of the n-bit digital input signal is input. 2. The D / A converter according to claim 1, wherein an analog output signal corresponding to the digital input signal is selected and output from output signals of the plurality of buffer amplifiers based on the digital input signal.