JPH10209395A - Semiconductor storage device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable a semiconductor memory device to reduce variation in contact resistance, and ensure an enough withstand voltage between a storage node and a substrate, and an electric capacity. SOLUTION: A capacitor cell 10 is composed of a columnar storage 12 of polycrystalline silicon, a capacitor insulating film 13 is composed of Si3 N4 , and an upper electrode 14 composed of aluminum. The columnar storage 12 is composed of a base 12a of polycrystalline silicon doped with phosphorus in concentration of 4×10<20> cm<-3> , an inner part 12b of polycrystalline silicon doped with phosphorus in concentration of 1×10<20> cm<-3> , an upper part 12c of polycrystalline silicon doped with phosphorus in concentration of 7×10<20> cm<-3> , and a side part 12d of polycrystalline silicon layer doped with phosphorus in concentration of 7×10<20> cm<-3> .

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly, to a semiconductor memory device having a stacked capacitor cell.

[0002]

2. Description of the Related Art The performance and functions of semiconductor devices have been improved by miniaturization of processing accuracy and higher integration. Although the miniaturization of the device dimensions needs to be accompanied by the miniaturization in the film thickness direction, in actuality, the electrical characteristics and reliability of the device may be deteriorated.

In a semiconductor storage capacitor, since the surface area of the storage node of the storage element decreases with miniaturization, variation in electric capacitance value is likely to occur.

[0004] This phenomenon will be described with reference to a sectional view showing a storage node of a conventional semiconductor memory device shown in FIG.

In FIG. 4, reference numeral 100 denotes a columnar capacitor cell formed on a substrate 101 made of silicon. The capacitor cell 100 includes a storage node 102 made of polycrystalline silicon, a capacitance insulating film 103 made of Si ₃ N ₄ , and an upper electrode 104 made of aluminum. Reference numeral 107 denotes a substrate contact portion at an interface where the storage node 102 and the substrate 101 are joined. 101a is the storage node 102 to the substrate 101
Is an n-type diffusion layer formed by diffusing impurity phosphorus. 10
Reference numeral 5 denotes a gate electrode of an FET which is another element different from the storage element made of polycrystalline silicon. Reference numeral 106 denotes an insulating oxide film which insulates the gate electrode 105 from the substrate 101, the upper electrode 104, and the storage node 102, respectively. is there.

[0006]

However, in the conventional semiconductor memory device, if the impurity concentration of the polycrystalline silicon in the substrate contact portion 107 becomes smaller as the miniaturization proceeds, the variation in the contact resistance becomes larger, and the substrate contact portion 107 becomes larger. If the impurity concentration of the polycrystalline silicon is high, the electric breakdown voltage between the storage node 102 and the substrate 101 decreases.

If the storage node 102 is formed by optimizing the impurity concentration of the substrate contact portion 102a, a sufficient majority carriers cannot be secured in the storage node 102 even when a voltage is applied to the upper electrode 104. Since the polycrystalline silicon is depleted, the electric capacitance value decreases, and as a result, the reliability of the storage device decreases.

In view of the above problems, it is an object of the present invention to reduce the variation in contact resistance, secure the electrical breakdown voltage between the storage node and the substrate, and secure the electrical capacitance value. is there.

[0009]

In order to achieve the above object, the present invention optimizes the impurity concentration of a substrate contact portion in a storage node and the impurity concentration of a charge storage portion other than the substrate contact portion in a storage node. It becomes something.

According to a first aspect of the present invention, there is provided a semiconductor memory device comprising a semiconductor substrate and a semiconductor formed on a top surface of the semiconductor substrate in a column shape perpendicular to the top surface and storing electric charges. A storage node, a bottomed cylindrical capacitor insulating film formed over the entire upper surface and side surfaces of the storage node, and an upper electrode formed over the entire upper surface and outer surface of the capacitive insulating film. The impurity concentration at the bottom of the storage node is optimized such that the contact resistance at the junction with the semiconductor substrate is stable and the electrical breakdown voltage is secured, and the impurity concentration at the top or side of the storage node is , The impurity concentration is higher than the impurity concentration at the bottom of the storage node.

According to the first aspect of the present invention, the impurity concentration at the bottom of the storage node is optimized, and the impurity concentration at the top or side of the storage node facing the upper electrode is the impurity concentration at the bottom of the storage node. Since the concentration is higher than the concentration, a majority carrier can be sufficiently secured.

According to a second aspect of the present invention, there is provided a semiconductor memory device comprising a semiconductor substrate and a pillar formed on an upper surface of the semiconductor substrate and perpendicular to the upper surface of the semiconductor substrate. A columnar storage node, a bottomed cylindrical capacitor insulating film formed over the entire upper surface and side surfaces of the storage node, and an upper electrode formed over the entire upper surface and outer surface of the capacitive insulating film. Wherein the impurity concentration at the bottom of the storage node is 1 × 10 ²⁰ cm ^{−3 to} 7 × 10 ²⁰ cm ⁻³ , and the impurity concentration at the side and the top of the storage node is 4 × 1
0 ²⁰ cm ⁻³ to 8 × 10 ²⁰ cm ⁻³ and higher than the impurity concentration at the bottom of the storage node.

According to the second aspect of the present invention, the impurity concentration at the bottom of the storage node is 1 × 10 ²⁰ cm ^{−3 to} 7 × 10 ²⁰ c.
m ⁻³ , the impurity concentration at the bottom of the storage node is optimized, and the impurity concentration at the side and at the top of the storage node facing the upper electrode is 4 × 10 ²⁰
Since the impurity concentration is between cm ^{−3 and} 8 × 10 ²⁰ cm ⁻³ and is higher than the impurity concentration at the bottom of the storage node, the top or side of the storage node can sufficiently secure majority carriers.

According to a third aspect of the present invention, in addition to the configuration of the second aspect, a configuration in which the silicon constituting the storage node is amorphous, a mixed crystal of amorphous and crystalline, polycrystalline or single crystal is added. .

According to a fourth aspect of the present invention, in addition to the configuration of the second or third aspect, a configuration in which the impurity added to the storage node is phosphorus, arsenic, boron, or antimony is added.

The solving means invention is taken of claim 5, the method of manufacturing a semiconductor memory device, on a semiconductor substrate, an impurity concentration ^{1 × 10 20 cm -3 ~7 ×} 10 20 cm -3 first of Depositing a silicon film, and forming an impurity concentration of 4 × 10 ²⁰ cm ⁻³ to 8 × 10 over the entire surface of the first silicon film.
Depositing a second silicon film having an impurity concentration of ²⁰ cm ^-3 and higher than the impurity concentration of the first silicon film; and forming a mask pattern in a storage node formation region on the second silicon film. Forming a columnar storage node by performing a series of etchings on the first and second silicon films using the mask pattern; and forming a capacitor insulating layer on the entire upper surface and side surfaces of the columnar storage node. Depositing a film, depositing a conductive film over the entire surface of the capacitive insulating film, forming a mask pattern in an upper electrode formation region on the conductive film, and forming the mask pattern on the conductive film using the mask pattern. And forming an upper electrode by etching.

According to the structure of claim 5, on the semiconductor substrate,
After depositing a first silicon film having an impurity concentration of 1 × 10 ²⁰ cm ^{−3 to} 7 × 10 ²⁰ cm ^−3, an impurity concentration of 4 × 10 ²⁰ cm ⁻³ to over the entire surface of the first silicon film. 8x1
In order to deposit a second silicon film of 0 ²⁰ cm ⁻³ and higher than the impurity concentration of the first silicon film, the impurity concentration at the bottom of the storage node is optimized, and the storage node facing the upper electrode is The upper part or side part can secure a majority carrier.

According to a sixth aspect of the present invention, there is provided a method for manufacturing a semiconductor memory device, comprising the steps of: forming a semiconductor memory device on a semiconductor substrate having a first impurity concentration of 1 × 10 ²⁰ cm ^{−3 to} 7 × 10 ²⁰ cm ⁻³ ; Depositing a silicon film on the first silicon film, and forming an impurity concentration of 0.1 × 10 ²⁰ cm ⁻³ to 1 over the entire surface of the first silicon film.
Depositing a second silicon film of × 10 ²⁰ cm ^-3 ;
A third silicon film having an impurity concentration of 4 × 10 ²⁰ cm ⁻³ to 8 × 10 ²⁰ cm ⁻³ over the entire surface of the second silicon film and higher than the impurity concentration of the first silicon film is formed. Depositing and forming a mask pattern in a storage node formation region on the third silicon film, and then performing a series of etchings on the first, second and third silicon films using the mask pattern And a fourth silicon film having an impurity concentration of 4 × 10 ²⁰ cm ⁻³ to 8 × 10 ²⁰ cm ⁻³ over the entire surface of the semiconductor substrate and larger than the impurity concentration of the first silicon film. Forming a columnar storage node by performing etch-back on the fourth silicon film, and covering the entire upper surface and side surfaces of the columnar storage node. Depositing an insulating film, depositing a conductive film over the entire surface of the capacitive insulating film, forming a mask pattern in an upper electrode formation region on the conductive film, and then using the mask pattern to form the conductive film. Forming an upper electrode by etching the film.

According to a sixth aspect of the present invention, the storage node on the semiconductor substrate is a first silicon having an impurity concentration of 1 × 10 ²⁰ cm ^{−3 to} 7 × 10 ²⁰ cm ⁻³ in order from the substrate surface, The concentration is 0.1 × 10 ²⁰ cm ⁻³ to 1 × 10
²⁰ cm ⁻³ second silicon film and its impurity concentration is 4 ×
Third silicon films each having a density of 10 ²⁰ cm ⁻³ to 8 × 10 ²⁰ cm ⁻³ and larger than the impurity concentration of the first silicon film are deposited and etched except for a storage node formation region. The impurity concentration at the side is 4 × 10 ²⁰
After depositing a fourth silicon film having a density of cm ⁻³ to 8 × 10 ²⁰ cm ⁻³ and higher than the impurity concentration of the first silicon film serving as a bottom portion, the fourth silicon film is etched back. Accordingly, the impurity concentration at the bottom of the storage node is optimized, and the upper or side portion of the storage node facing the upper electrode can sufficiently secure majority carriers.

[0020]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) A first embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a configuration sectional view of a semiconductor memory device according to the first embodiment of the present invention. In FIG. 1, reference numeral 10 denotes a columnar capacitor cell formed on a substrate 11 made of silicon. The capacitor cell 10 includes a columnar storage node 12 made of polycrystalline silicon, a bottomed cylindrical capacitor insulating film 13 made of Si ₃ N ₄ adhered to the storage node 12, and a bottomed tube adhered to the capacitor insulating film 13. And an upper electrode 14 made of cylindrical aluminum. The storage node 12 has a density of 4 × 10 ²⁰
The bottom portion 12a of the storage node 12 made of polycrystalline silicon doped with phosphorus controlled to be cm ⁻³ and the polycrystalline silicon doped with phosphorus whose concentration is controlled to 1 × 10 ²⁰ cm ^−3. and internal 12b of the storage node 12, the upper 12c of the storage node 12 with phosphorus that is controlled in concentration 7 × 10 ²⁰ cm ^-3 is formed of polycrystalline silicon doped, the concentration of 7 × 10 ²⁰ cm ^-3 And a side portion 12 d of the storage node 12 of a polycrystalline silicon layer which is controlled by phosphorus. Reference numeral 11a denotes an n-type diffusion layer formed by diffusing impurity phosphorus from the storage node 12 into the substrate 11. 15 is another element F different from the storage element made of polycrystalline silicon.
Reference numeral 16 denotes an ET gate electrode, and reference numeral 16 denotes an insulating oxide film that insulates the gate electrode 15 from the substrate 11, the upper electrode 14, and the storage node 12.

The storage node 12 has a bottom portion 12 a on the gate electrode 15 side of the storage node 12 insulated from the gate electrode 15 by an insulating oxide film 16.
Contact portion 17 which is an interface between substrate 11 and bottom portion 12a
To the substrate 11. An n-type diffusion layer 11a is formed in the contact region of the substrate 11 by a heat treatment at 900 ° C. for about 30 minutes via the contact portion 17. Since the bottom portion 12a of the storage node 12 is optimized by controlling the impurity concentration of phosphorus to 4 × 10 ²⁰ cm ⁻³ , the n-type diffusion layer 11a diffuses into the upper portion of the substrate 11 with the controlled phosphorus concentration. Therefore, the contact resistance between storage node 12 and substrate 11 is formed stably, and the electrical breakdown voltage between storage node 12 and substrate 11 can be ensured.

The upper part 12c and the side part 12d of the storage node 12 are opposed to the upper electrode 14 via the capacitive insulating film 13 to form an electric capacitance. The top 12c and side 12d of the storage node 12 are
Since the impurity concentration is higher than that of 2a and the inside 12b, a sufficient number of carriers can be secured, so that electrical depletion of the storage node 12 can be prevented. Thereby, the electric capacity of the capacitor cell 10 can be sufficiently ensured.

In the present embodiment, the substrate 11 made of silicon is used below the contact region joined to the storage node 12, but the same effect can be obtained by using a diffusion layer such as a well, a source, and a drain. Needless to say, it can be obtained.

Further, an insulating oxide film 1 is used for insulating the gate electrode.
6, the same effect can be obtained by using another insulating film made of a member capable of electrically insulating the substrate 11, the storage node 12, and the gate electrode 15 from each other.

Although the capacitor insulating film 13 is made of Si ₃ N ₄ , a SiO ₂ or ONO layer (after oxidizing the silicon film of the storage node 12, an Si ₃ N ₄ layer is formed on the oxide film) , A composite film obtained by oxidizing the Si ₃ N ₄ layer) or Ta ₂ O
It goes without saying that a similar effect can be obtained even if an insulating layer such as ₅ is used.

Although aluminum is used for the upper electrode 14, it goes without saying that the same effect can be obtained by using silicide or another metallic material.

Although the FET gate electrode 15 of another element is made of polycrystalline silicon, the same effect can be obtained by using a source electrode, a drain electrode, or another material such as silicide. Needless to say.

Although polycrystalline silicon is used for the storage node 12, it goes without saying that the same effect can be obtained by using amorphous silicon, mixed crystal silicon of amorphous and crystal, or single crystal silicon.

Although phosphorus is used as an impurity for the silicon film of the storage node 12, it goes without saying that the same effect can be obtained by using arsenic, boron or antimony.

The shape of the storage node 12 is cylindrical. However, the present invention is not limited to this.

(Second Embodiment) Hereinafter, a second embodiment of the present invention will be described with reference to the drawings.

FIG. 2 is a sectional view in the order of steps showing a method for manufacturing a semiconductor memory device according to a second embodiment of the present invention.

First, as shown in FIG. 2A, an insulating oxide film 22A, a polycrystalline silicon film 23A, and a TEOS oxide film 24 are formed on the entire surface of a substrate 21 made of silicon.
After sequentially depositing A, a first resist pattern 25 transferred to a predetermined pattern using photolithography is formed on the TEOS oxide film 24A in a gate electrode formation region of an FET which is another element different from the storage element by using photolithography. Form.

Next, as shown in FIG.
The oxide film 24A and the polycrystalline silicon film 23A are continuously etched to form a gate electrode 23B and a cap TEOS 24B. After that, the first resist pattern 25 is removed, and a TEOS oxide film 26A is deposited on the entire surface of the substrate 21.

Next, as shown in FIG.
The oxide film 26A is etched back to form an oxide film spacer 26B on each side of each gate electrode 23B. Thereafter, by removing the insulating oxide film 22A in the region for forming the contact portion with the storage node using dilute hydrofluoric acid, the gate oxide films 22B are formed under the respective gate electrodes 23B. Next, at a temperature of 530 ° C., a first amorphous silicon film 28 doped with phosphorus, whose concentration is controlled to 4 × 10 ²⁰ cm ⁻³ , is deposited to a thickness of 50 nm over the entire surface of the substrate 21. A second phosphorus-doped amorphous silicon film 2 whose concentration is controlled to 7 × 10 ²⁰ cm ⁻³ continuously in the apparatus.
9 to a thickness of 650 nm. Next, a second resist pattern 30 transferred to a predetermined pattern is formed in the storage node formation region by using photolithography.

Next, as shown in FIG. 2D, the first amorphous silicon film 28 and the second amorphous silicon film 29 are successively etched, and the first amorphous silicon film 28 and the second amorphous silicon film 29 are etched. Bottom portion 31a and upper portion 31b made of second amorphous silicon film 29
To form a cylindrical storage node 31. Then, at a temperature of 900 ° C. and 3
By performing heat treatment for about 0 minutes, an n-type diffusion layer 21a is formed in the contact portion 27 of the substrate 21 from the bottom 31a of the storage node 31 via the contact portion 27.
Thereafter, an insulating film 32A made of Si ₃ N ₄ and an upper electrode forming film 33A made of aluminum were sequentially deposited over the entire surface of the substrate 21, and then transferred to a predetermined pattern in the upper electrode forming region using photolithography. The third resist pattern 34 is formed, and the upper electrode forming film 33A and the insulating film 32A are continuously etched to form the upper electrode 33B and the capacitor insulating film 32B. Thereafter, as shown in FIG. 2E, the third resist pattern 34 is removed to form a capacitor cell.

When etching the upper electrode forming film 33A, the insulating film 32A may not be etched, or only a part of the insulating film 32A may be etched. If it is formed, a similar effect can be obtained.

As described above, according to this embodiment, the first amorphous silicon film 28 has a phosphorus concentration of 1 × 10 ²⁰ c.
m ^{−3 to} 7 × 10 ²⁰ cm ⁻³ and a film thickness of 30 nm to 200
The second amorphous silicon film 29 has a phosphorus concentration of 4 × 10 ²⁰ cm ⁻³ to 8 × 10 ²⁰ cm ⁻³ and an impurity concentration higher than that of the first amorphous silicon film 28. Is 200 nm to 900 nm, the contact resistance between the storage node 31 and the substrate 21 in the contact portion 27 is formed stably, and the electrical breakdown voltage between the storage node 31 and the substrate 21 can be ensured.

Further, the second amorphous silicon film 2
9, the upper part 31b of the storage node 31
Since the impurity concentration is higher than that of the bottom portion 31a made of the amorphous silicon film 28, more majority carriers can be secured, so that depletion of carriers in the storage node 31 can be prevented. As a result, the electric capacity of the capacitor cell can be sufficiently ensured,
Reliability of the storage device can be improved.

Although the substrate 21 made of silicon is used below the contact portion 27 joined to the storage node 31, the same effect can be obtained by using a diffusion layer such as a well, a source, and a drain. Needless to say.

Also, as the oxide film spacer 26B, TE
Although the OS oxide film is used, it is needless to say that the same effect can be obtained by using another insulating film that can be electrically insulated from the substrate 21 and the gate electrode 23B.

Although Si ₃ N ₄ is used for the capacitive insulating film 32 B, it goes without saying that the same effect can be obtained by using an insulating film made of SiO ₂ , ONO layer, Ta ₂ O ₅ or the like.

Although aluminum is used for the upper electrode 33B, it goes without saying that the same effect can be obtained by using silicide or another metallic material.

Although amorphous silicon is used for the bottom portion 31a and the upper portion 31b of the storage node 31, it goes without saying that the same effect can be obtained by using single crystal silicon, mixed crystal silicon of amorphous and crystal, or single crystal silicon. .

Although phosphorus is used as an impurity of the silicon film forming the storage node 21, it goes without saying that the same effect can be obtained by using arsenic, boron or antimony.

The shape of the storage node 21 is cylindrical, but the present invention is not limited to this, and it goes without saying that the same effect can be obtained with a prism.

(Third Embodiment) Hereinafter, a third embodiment of the present invention will be described with reference to the drawings.

FIG. 3 is a cross-sectional view illustrating a method of manufacturing a semiconductor memory device according to a third embodiment of the present invention. FIG.
First, as shown in FIG. 3A, an insulating oxide film 4 is formed over a whole surface of a substrate 41 made of silicon.
2A, polycrystalline silicon film 43A, TEOS oxide film 44A
Are sequentially deposited, a first resist pattern 45 transferred to a predetermined pattern is formed on the TEOS oxide film 44A by photolithography in a gate electrode formation region of the FET, which is another element different from the storage element, by using photolithography. I do.

Next, as shown in FIG.
The oxide film 44A and the polycrystalline silicon film 43A are continuously etched to form a gate electrode 43B and a cap TEOS44B. After that, the first resist pattern 45 is removed, and a TEOS oxide film 46A is deposited on the entire surface of the substrate 41.

Next, as shown in FIG.
The oxide film 46A is etched back to form an oxide film spacer 46B on each side of each gate electrode 43B. After that, using diluted hydrofluoric acid, the insulating oxide film 42 which is a contact portion forming region with the storage node is formed.
By removing A, a gate oxide film 42B is formed below each gate electrode 43B. Next, the temperature 530
At 50 ° C., a phosphorus-doped first amorphous silicon film 48 having a concentration controlled to 4 × 10 ²⁰ cm ⁻³ is deposited to a thickness of 50 nm over the entire surface of the substrate 41 and continuously formed in the same apparatus. Then, a phosphorus-doped second amorphous silicon film 49, whose concentration is controlled to 1 × 10 ¹⁹ cm ⁻³ , is deposited to a thickness of 500 nm, and the entire surface of the second amorphous silicon film 49 is Is 8 × 10
A phosphorus-doped second amorphous silicon film 49 controlled to ²⁰ cm ^-3 is deposited to a thickness of 50 nm.
Here, the second amorphous silicon film 48 is
By decreasing the concentration of the amorphous silicon film 49, the growth rate of the second amorphous silicon film 49 becomes 2-3 times higher than that of the first amorphous silicon film 48. Next, a second resist pattern 51 transferred to a predetermined pattern is formed in the storage node formation region using photolithography.

Next, as shown in FIG. 3D, after the first amorphous silicon film 48, the second amorphous silicon film 49, and the third amorphous silicon film 50 are successively etched, Then, the second resist pattern 51 is removed. Thereafter, a fourth amorphous silicon film 52 doped with phosphorus, whose concentration is controlled to 8 × 10 ²⁰ cm ⁻³ , is deposited on the entire surface of the substrate 41 at a temperature of 530 ° C. to a thickness of 100 nm. Is etched back with a thickness of 100 nm to form side portions 53d. As a result, a bottom portion 53a made of the first amorphous silicon film 48, an inner portion 53b made of the second amorphous silicon film 49, and the like are formed. A columnar storage node 53 composed of an upper portion 53c made of the third amorphous silicon film 50 and a side portion 53d made of the fourth amorphous silicon film 42 is formed.

Next, as shown in FIG.
Then, a heat treatment is performed at a temperature of 900 ° C. for about 30 minutes to form an n-type diffusion layer 41 a on the contact portion 47 of the substrate 41 from the bottom 53 a of the storage node 53 via the contact portion 47. Thereafter, an insulating film 54A made of Si ₃ N ₄ and an upper electrode forming film 55A made of aluminum were sequentially deposited over the entire surface of the substrate 41, and then transferred to a predetermined pattern in the upper electrode forming region using photolithography. A third resist pattern 56 is formed, and an upper electrode forming film 55A and an insulating film 54A
To the upper electrode 55B.
And a capacitor insulating film 54B. Then, FIG.
As shown in (3), the third resist pattern 56 is removed to form a capacitor cell.

When the upper electrode forming film 55A is etched, the insulating film 54A need not be etched, and even if only a part of the insulating film 54A is etched, the capacitive insulating film 54B is formed. If it is, the same effect can be obtained.

As described above, according to this embodiment, the first amorphous silicon film 48 has a phosphorus concentration of 1 × 10 ²⁰ c.
m ^{−3 to} 7 × 10 ²⁰ cm ⁻³ and a film thickness of 30 nm to 200
and the third and fourth amorphous silicon films 49 have a phosphorus concentration of 0.1 × 10 ²⁰ cm ^{−3 to} 7 × 10 ²⁰ cm ⁻³ and a thickness of 30 nm to 700 nm. 50 and 52 with phosphorus concentration of 4 × 10 ²⁰ c
If the impurity concentration is set to m ⁻³ to 8 × 10 ²⁰ cm ⁻³ and the impurity concentration is higher than that of the first amorphous silicon film 48 and the film thickness is set to 50 nm to 150 nm, the contact portion 47 is formed.
In this case, the contact resistance between the storage node 53 and the substrate 41 is stably formed, and the electrical breakdown voltage between the storage node 53 and the substrate 41 can be ensured.

Further, the third amorphous silicon film 5
The upper portion 53c of the storage node 53 made of zero and the side portion 53d of the storage node 53 made of the fourth amorphous silicon film 52 have higher impurity concentrations than the bottom portion 53a made of the first amorphous silicon film 48. As we can secure more majority carriers,
Depletion of carriers in the storage node 53 can be prevented. As a result, the electric capacity of the capacitor cell can be sufficiently ensured.

Although the substrate 41 made of silicon is used below the contact portion 47 joined to the storage node 53, the same effect can be obtained by using a diffusion layer such as a well, a source, and a drain. Needless to say.

As the oxide film spacer 46B, TE
Although the OS oxide film is used, it goes without saying that the same effect can be obtained by using another insulating film that can be electrically insulated from the substrate 41 and the gate electrode 43B.

Although Si ₃ N ₄ is used for the capacitance insulating film 54 B, it goes without saying that the same effect can be obtained by using an insulating film made of SiO ₂ , ONO layer, Ta ₂ O ₅ or the like.

Although aluminum is used for the upper electrode 55B, it goes without saying that the same effect can be obtained by using silicide or another metallic material.

Although amorphous silicon is used for the bottom portion 53a and the upper portion 53b of the storage node 53, it goes without saying that the same effect can be obtained by using single crystal silicon, mixed crystal silicon of amorphous and crystal, or single crystal silicon. .

Although phosphorus is used as an impurity of the silicon film forming the storage node 53, it goes without saying that the same effect can be obtained by using arsenic, boron or antimony.

Further, the shape of the storage node 53 is cylindrical, but the present invention is not limited to this.

Here, although not directly related to the present invention, the film forming conditions of phosphorus-doped amorphous silicon are shown below as an example.

Apparatus name Vertical reduced pressure CVD gas SiH ₄ , PH ₃ , N ₂ Vacuum degree 100 Pa

[0066]

According to the semiconductor memory device of the first aspect of the present invention, since the impurity concentration at the bottom of the storage node is optimized, the contact resistance between the bottom of the storage node and the diffusion layer above the substrate is varied. And the electrical breakdown voltage between the storage node and the diffusion layer can be ensured. Further, since the impurity concentration at the top or the side of the storage node facing the upper electrode is higher than the impurity concentration at the bottom of the storage node, a sufficient number of carriers can be secured. Can be sufficiently secured. Thereby, the reliability of the semiconductor memory device can be improved.

According to the semiconductor memory device of the second aspect of the present invention, the effect of the semiconductor memory device of the first aspect of the present invention is obtained, and the impurity concentration at the bottom of the storage node is 1
Since it is from × 10 ²⁰ cm ^{−3 to} 7 × 10 ²⁰ cm ⁻³ , the impurity concentration at the bottom of the storage node is definitely optimized. The impurity concentration on the side and the top of the storage node facing the upper electrode is 4 × 10 ²⁰ cm ⁻³ to 8 × 10 ^20.
Since the impurity concentration is cm ⁻³ and higher than the impurity concentration at the bottom of the storage node, majority carriers can be reliably secured at the top or side of the storage node.

According to the semiconductor memory device of the third aspect of the present invention, the silicon constituting the storage node is made of amorphous, a mixed crystal of amorphous and crystalline, polycrystalline or single crystal. Is reliably optimized by being doped with impurities, so that the contact resistance is reliably stabilized, and the top or side of the storage node can be surely provided with majority carriers by being doped with impurities. .

According to the semiconductor memory device of the fourth aspect, since the impurity added to the storage node is phosphorus, arsenic, boron or antimony, the impurity concentration at the bottom of the storage node is reliably optimized. Therefore, the contact resistance can be reliably stabilized, and the majority carriers on the upper portion or the side portion of the storage node can be surely increased.

According to the method of manufacturing a semiconductor memory device of the present invention, since the impurity concentration at the bottom of the storage node is controlled to be optimized, the diffusion at the bottom of the storage node and the upper portion of the substrate is performed. The variation in the contact resistance between the storage node and the layer is reduced, and the electrical breakdown voltage between the storage node and the diffusion layer can be sufficiently ensured. Also, since the impurity concentration at the top or side of the storage node facing the upper electrode is controlled to be higher than the impurity concentration at the bottom of the storage node, majority carriers are sufficiently secured, so that the capacitor cell Sufficient electrical capacity can be secured. as a result,
The reliability of the semiconductor memory device can be improved.

[Brief description of the drawings]

FIG. 1 is a configuration sectional view of a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating a method of manufacturing a semiconductor memory device according to a second embodiment of the present invention in order of process.

FIG. 3 is a cross-sectional view illustrating a method of manufacturing a semiconductor memory device according to a third embodiment of the present invention in the order of steps.

FIG. 4 is a configuration sectional view of a conventional semiconductor memory device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Capacitor cell 11 Substrate 12 Storage node 13 Capacitive insulating film 14 Upper electrode 15 Gate electrode 16 Insulating oxide film 17 Contact part 21 Substrate 22A Insulating oxide film 22B Gate oxide film 23A Polycrystalline silicon film 23B Gate electrode 24A TEOS oxide film 24B Cap TEOS 25 First resist pattern 26A TEOS oxide film 26B Oxide film spacer 27 Contact part 28 First amorphous silicon film 29 Second amorphous silicon film 30 Second resist pattern 31 Storage node 31a Bottom 31b Upper 32A Insulating film 32B Capacitive insulating film 33A Upper electrode forming film 33B Upper electrode 34 Third resist pattern 41 Substrate 42A Insulating oxide film 42B Gate oxide film 43A Polycrystalline silicon film 43B Gate Electrode 44A TEOS oxide film 44B Cap TEOS 45 First resist pattern 46A TEOS oxide film 46B Oxide film spacer 47 Contact part 48 First amorphous silicon film 49 Second amorphous silicon film 50 Third amorphous silicon film 51 Second Resist pattern 52 Fourth amorphous silicon film 53 Storage node 53a Bottom 53b Inside 53c Top 53d Side 54A Insulating film 54B Capacitive insulating film 55A Upper electrode forming film 55B Upper electrode 56 Third resist pattern

Claims (6)

[Claims] 1. A semiconductor substrate, a storage node formed on an upper surface of the semiconductor substrate in a columnar shape perpendicular to the upper surface, and made of a semiconductor for accumulating electric charge, and an entire upper surface and side surfaces of the storage node A bottomed cylindrical capacitance insulating film formed; and a bottomed cylindrical upper electrode formed over the entire upper surface and outer surface of the capacitance insulating film; the impurity concentration at the bottom of the storage node is Optimized so that the contact resistance at the junction with the semiconductor substrate is stable and the electrical breakdown voltage is ensured, and the impurity concentration at the top or side of the storage node is:
A semiconductor memory device having an impurity concentration higher than a bottom portion of the storage node. 2. A semiconductor substrate, a columnar storage node formed on a top surface of the semiconductor substrate in a column shape perpendicular to the top surface, and made of silicon for accumulating electric charge; and a top surface and side surfaces of the storage node. A capacitive insulating film having a bottomed cylindrical shape formed over the entire surface; and an upper electrode formed over the entire upper surface and the side surface of the capacitive insulating film. The impurity concentration at the bottom of the storage node is 1 × 10 ²⁰
cm ^{−3 to} 7 × 10 ²⁰ cm ⁻³ , and the impurity concentration on the side and the top of the storage node is 4 × 10 ²⁰ cm ⁻³ to 8
A semiconductor memory device characterized by being × 10 ²⁰ cm ⁻³ and higher than the impurity concentration at the bottom of the storage node. 3. The semiconductor memory device according to claim 2, wherein the silicon constituting the storage node is amorphous, a mixed crystal of amorphous and crystalline, polycrystalline or single crystal. 4. The semiconductor memory device according to claim 2, wherein said impurity added to said storage node is phosphorus, arsenic, boron or antimony. 5. An impurity concentration of 1 × 10 on a semiconductor substrate.
Depositing a first silicon film of ²⁰ cm ^{−3 to} 7 × 10 ²⁰ cm ⁻³ , and an impurity concentration of 4 × 10 ²⁰ cm ⁻³ to 8 × 10 ²⁰ over the entire surface of the first silicon film. depositing a second silicon film having an impurity concentration of cm ^-3 and higher than the impurity concentration of the first silicon film; and forming a mask pattern in a storage node formation region on the second silicon film; Forming a columnar storage node by performing a series of etchings on the first and second silicon films using the mask pattern; and depositing a capacitive insulating film over the entire upper surface and side surfaces of the storage node. Forming a conductive pattern over the entire surface of the capacitive insulating film; forming a mask pattern in an upper electrode formation region on the conductive film; Forming an upper electrode by etching the conductive film using a metal pattern. 6. An impurity concentration of 1 × 10 on a semiconductor substrate.
Depositing a first silicon film of ²⁰ cm ^{−3 to} 7 × 10 ²⁰ cm ⁻³ , and an impurity concentration of 0.1 × 10 ²⁰ cm ⁻³ to 1 × over the entire surface of the first silicon film. Depositing a second silicon film of 10 ²⁰ cm ^-3 , wherein the impurity concentration is 4 × 10 ²⁰ cm ^-3 to 8 × 10 ²⁰ cm ^-3 over the entire surface of the second silicon film; Depositing a third silicon film having an impurity concentration higher than that of the first silicon film; forming a mask pattern in a storage node formation region on the third silicon film; Performing a series of etching on the first, second, and third silicon films; and forming an impurity concentration of 4 × 1 over the entire surface of the semiconductor substrate.
After depositing a fourth silicon film of 0 ²⁰ cm ⁻³ to 8 × 10 ²⁰ cm ⁻³ and higher than the impurity concentration of the first silicon film, etch back is performed on the fourth silicon film. Forming a columnar storage node in a row, depositing a capacitive insulating film over the entire upper surface and side surfaces of the columnar storage node, depositing a conductive film over the entire capacitive insulating film, Forming a mask pattern in an upper electrode formation region on the film, and then etching the conductive film using the mask pattern to form an upper electrode. A method for manufacturing a storage device.