JPH10209226A - Semiconductor member and semiconductor chip - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily handle plural semiconductor chips, small and excellent in element characteristics, by arraying plural semiconductor substrates on the same plane, and, over them, providing plural metal films so arranged that both ends are on adjoining semiconductor substrates. SOLUTION: Plural semiconductor substrates 1 arrayed on the same plane, and plural metal films 5 and 6 whose both ends are placed on adjoining semiconductor substrates 1 among plural semiconductor substrates 1 while connecting the adjoining semiconductor substrates 1, are provided. For example, plural semiconductor substrates 1 where, respectively, an FET semiconductor element part comprising source, drain, and gate electrodes is formed, are to be semiconductor member 50 connected together with a gate electrode metal film 5 and a source/drain electrode metal film 6. By cutting off, as required, metal films 5 and 6 at around center of them, a semiconductor chip can be taken out one by one.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor member and a semiconductor chip, and more particularly to a semiconductor member and a semiconductor chip provided with a semiconductor element such as a field effect transistor used in a high frequency region.

[0002]

2. Description of the Related Art FIG. 9 is a perspective view showing the structure of a semiconductor chip described in Japanese Patent Application Laid-Open No. 2-168632, and particularly shows a state where the semiconductor chip is connected to a signal transmission line. In the figure, 100 is a semiconductor chip on which a MESFET element (not shown) is formed, 101
Is a semiconductor substrate, 102 is a source electrode, 103 is a gate electrode, 103a is a gate portion, 103b is a columnar member, 104
Is a drain electrode, 105 is a lead portion for a gate electrode, 10
6 is a drain electrode lead portion, 107 is an input side strip line, 108 is an output side strip line, 109 is an input side strip line substrate, 110 is an output side strip line substrate, 130 is a via hole, and 201 is an input side signal. A transmission line 202 is an output-side signal transmission line.

Next, the structure will be described. The semiconductor chip 100 includes a gate electrode 103 and a drain electrode 10
4 includes a gate electrode lead portion 105 and a drain electrode lead portion 106 extending outward from the chip end, respectively.
Electrical connection with the signal transmission lines 201 and 202 is made by pressing the gate electrode lead portions 105 and the drain electrode lead portions 106 and the signal transmission lines 201 and 202, respectively. Further, the gate electrode 103 is a gate portion 1 of the FET.
Immediately before reaching 03a, the source electrode 102 three-dimensionally intersects with the source electrode 102 and does not contact the source electrode 102.
A columnar member 103b extends downward from the gate electrode 103 floating above the source electrode 102, and is connected to the gate portion 103a of the FET. Also, the source electrode 10
2 is connected to the back surface electrode (not shown) of the substrate 101 through the via hole 130.

Next, a method of manufacturing the semiconductor chip 100 will be described. First, an active layer (not shown) is formed in each of regions (not shown) where a plurality of semiconductor chips are to be formed on a wafer (not shown). Next, a source electrode 102 and a drain electrode 104, which are ohmic electrodes, and a gate electrode 103, which is a Schottky electrode, are individually formed in each of the regions where a plurality of semiconductor chips are formed. At this time, the drain electrode 104 and the gate electrode 103
In this case, lead portions 106 and 105 extending outside the region where the semiconductor chip is formed are provided.

Subsequently, the wafer is pasted on a wafer holding table (not shown) with wax or the like with the back side thereof facing upward, and a resist pattern is formed on a region of the back surface of the wafer where semiconductor chips are to be formed. Using this as a mask, the wafer is etched from the back side to separate a plurality of semiconductor chips. As a result, the drain electrode 104 and the gate electrode 103 have the lead portions 106 and 105 extending outside the semiconductor substrate 100. At this time, a pattern for forming a via hole is also provided in advance on the resist pattern, and the via hole 130 is formed at the same time.

[0006] Finally, plating is applied to the back surface of the semiconductor chip and the inside of the via hole 130, and a plurality of chips are peeled off from the wafer holder, respectively.
Get 0.

In this conventional semiconductor chip, the gate electrode 103 and the drain electrode 104 are provided with a gate electrode lead portion 105 and a drain electrode lead portion 106 which extend outside the end of the semiconductor substrate 101, respectively. The semiconductor chip 100 and the signal transmission line 201,
Electrical connection with the gate electrode 202 and the strip electrodes 107 and 108 can be made by bonding the gate electrode lead 105 and the drain electrode lead 106 to the strip lines 107 and 108, respectively. Therefore, when the semiconductor chip 100 is mounted on a signal transmission line, a package, or the like, the bonding of the electrode pads on the chip and the electrode pads on the package, which is performed in a normal semiconductor chip, becomes unnecessary, and assembly is not required. The process can be very easy. Further, since wire bonding is not required, variations in the characteristics of the semiconductor device due to variations in the length and position of the wires at the time of wire bonding can be prevented, and the yield can be improved.
Further, the need for a bonding pad having a relatively large area on the semiconductor chip is eliminated, the parasitic capacitance generated by the bonding pad can be reduced, the high-frequency characteristics can be improved, and the size of the semiconductor chip can be reduced.

[0008]

However, in a conventional semiconductor chip, a wafer for forming a gate electrode lead portion 105 and a drain electrode lead portion 106 extending outside the edge of the semiconductor substrate 101 is placed on the back surface. In the step of etching from the side, each of the plurality of semiconductor chips has been completely separated. For this reason, a plurality of semiconductor chips separated from each other collide with each other to damage the chip, a portion of the electrode extending outside the substrate 101 is bent, and the yield is reduced. When storing and storing a plurality of semiconductor chips, it is necessary to collect a plurality of semiconductor chips separated from each other, arrange them in a storage container or the like, and handle a plurality of semiconductor chips at once. There is a problem that handling of a plurality of semiconductor chips is extremely difficult, for example, it is impossible.

Further, as shown in FIG. 9, a conventional semiconductor chip includes substrates 109, 1 of signal transmission lines 201, 202.
By allowing the substrate 101 of the semiconductor chip 100 to be fitted between the semiconductor chip 100 and the height of the surface of the substrate 101 to be substantially the same as the height of the surface of the transmission line, the lead for the gate electrode of the semiconductor chip 100 is formed. Section 105, drain electrode lead section 106 and transmission lines 201 and 202
As shown in FIG. 10, the semiconductor chip 100 is connected to the strip line 107 at the bottom 203 of the package. 107,
The semiconductor chip 100 is disposed on the package bottom 203 so as to face the surface on which the gate electrode 108 is formed.
6 and the strip lines 107, 1 on the package bottom 203.
08 in a portion outside the chip. 10, the same reference numerals as those in FIG. 9 denote the same or corresponding parts, and 203 denotes the bottom of the package, and the via hole 130, the source electrode 102 and the substrate 1
The electrodes and the like on the back side of 01 are omitted here. When the semiconductor chip is mounted on the package bottom 203 in this manner, the structure of the portion on which the semiconductor chip is mounted does not need to be a special structure in which the semiconductor chip 100 can be fitted.

However, in the conventional semiconductor chip, if the length of the electrode extending outside the substrate 101 of the chip 100, that is, the length of the lead portion 105 for the gate electrode and the lead portion 106 for the drain electrode becomes longer, the length of the wafer per chip becomes larger. Since the occupied area increases, the number of chips obtained from a wafer decreases, and productivity decreases, the length of an electrode extending outside the chip is limited. Therefore, the length of the electrodes extending outside the chip becomes very short, and the semiconductor chip 100 is disposed on the package bottom 203 as shown in FIG.
There is a problem that it is sometimes very difficult to connect the strip lines 107 and 108 of the package.

In a conventional semiconductor chip, the area of the semiconductor substrate is made very small by eliminating bonding pads and the like from the semiconductor substrate of the chip, and the electrodes and the like extending outside the semiconductor chip are also very fine. It has become. For this reason, when the semiconductor chip is mounted on a package or the like, it is extremely difficult to align the electrode of the semiconductor chip with a strip line that is a transmission line of the package or the like, and there is a problem that productivity and yield are reduced.

Further, in a conventional semiconductor chip,
Since a part of the electrode extends outside the chip substrate, the strength of the part of the electrode outside the chip is relatively weak, and the electrode is bent and deformed depending on handling. There was a problem that it could not be directly attached.

The present invention has been made to solve the above problems, and has as its object to provide a semiconductor member which can easily handle a plurality of semiconductor chips which are small and have excellent element characteristics. And

Another object of the present invention is to provide a small-sized semiconductor chip having excellent element characteristics, which can be easily connected to a strip line.

It is another object of the present invention to provide a small-sized semiconductor chip having excellent element characteristics, which can be connected to a strip line with high positional accuracy.

It is another object of the present invention to provide a small semiconductor chip which can be easily handled and has excellent element characteristics.

[0017]

A semiconductor member according to the present invention comprises: a plurality of semiconductor substrates arranged on the same plane;
Both ends thereof are provided on a plurality of semiconductor substrates adjacent to each other among the plurality of semiconductor substrates, respectively, and include a plurality of metal films for coupling the adjacent semiconductor substrates.

In the semiconductor member, the semiconductor substrate may have a semiconductor element portion, and the metal film may be electrically connected to only one of the adjacent semiconductor substrates. It is something that has been done.

Further, the semiconductor chip according to the present invention comprises a semiconductor substrate, and a semiconductor substrate provided on the semiconductor substrate, one end of which is disposed on the semiconductor substrate, and the other end of which is provided on the surface of the semiconductor substrate outside the semiconductor substrate. And a metal film having a shape extending upward.

The semiconductor chip according to the present invention has a semiconductor substrate and one end thereof disposed on the semiconductor substrate.
The other end side is provided with a metal film arranged along the side surface of the semiconductor substrate.

Further, a semiconductor chip according to the present invention is provided in a semiconductor substrate, a metal film disposed on the semiconductor substrate, and in a region near an end of the semiconductor substrate and below the metal film. Further, a via hole for performing spot welding to the metal film from the back surface side of the substrate is provided.

[0022]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. FIG. 1 is a perspective view (FIG. 1A) showing the structure of a semiconductor member according to Embodiment 1 of the present invention, and FIG.
FIG. 1B is a cross-sectional view taken along the line Ib-Ib (FIG. 1B).
Reference numeral 50 denotes a semiconductor member, 1 denotes a plurality of semiconductor substrates arranged so as not to be in contact with each other, and in a predetermined region of each surface thereof, although not shown, a semiconductor substrate portion subjected to ion implantation or epitaxial growth, Field-Effect Transistor (FET: Field) with source, drain, and gate electrodes
Effect Transistor) is formed. Here, the semiconductor element portion refers to a portion of a semiconductor chip such as an FET other than the wiring, for example, an active layer or a recess structure. Reference numeral 5 denotes a gate electrode metal film, 3a denotes a gate portion which is a part of the gate electrode metal film 5, and 6 denotes a source / drain metal film.

FIG. 2 is a process chart showing a method for manufacturing a semiconductor member according to the first embodiment of the present invention. FIG. 2 (a) is a perspective view, and FIGS. 2 (b) and 2 (c) are views. Plan views corresponding to the parts indicated by A in FIG. 2A are respectively shown. In FIG. 2, the same reference numerals as those in FIG. 1 indicate the same or corresponding parts. Reference numeral 20 denotes a wafer, and reference numeral 10a denotes a semiconductor chip formation region.

FIG. 3 is a perspective view showing a structure of a semiconductor chip obtained from the semiconductor member according to the first embodiment of the present invention (FIG. 3A), and a state in which the semiconductor chip is arranged on a package bottom. 3 (b), wherein the same reference numerals as in FIG. 1 denote the same or corresponding parts, 2 is a source electrode, 4 is a drain electrode, and 10 is a MES.
FET (Metal Semiconductor Field Effect Transisto
r) etc., 11 is a package bottom, 12 is a source side line which is a strip line for transmitting signals and the like,
Reference numeral 13 denotes a gate-side line that is a strip line for transmitting a signal or the like, and 14 denotes a drain-side line that is a strip line for transmitting a signal or the like.

Next, the manufacturing method will be described. First, a wafer 20 is prepared, and a plurality of semiconductor element sections (not shown) are formed on the wafer 20 to provide a plurality of semiconductor elements having semiconductor element sections arranged at predetermined intervals. A chip formation region 10a is provided (FIG. 2A).

Subsequently, a plurality of metal films, both ends of which are respectively arranged on the wafer 20 by using a resist pattern or the like on the mutually adjacent semiconductor chip forming regions 10a among the plurality of semiconductor chip forming regions 10a. That is,
The gate electrode metal films 5, both ends of which are provided at positions where the gate electrodes of the respective semiconductor element portions of the adjacent semiconductor chip formation region 10a are provided, and the source or source of the respective semiconductor element portions of the adjacent semiconductor chip formation region 10a A source / drain electrode metal film 6 having both ends disposed at the position where the drain electrode is to be formed is formed by vapor deposition, plating or the like (FIG. 2 (b)).

Thereafter, as shown in FIG.
No. 0 is attached on a wafer mounting table (not shown) with wax or the like so that the surface on which the metal film such as the source / drain electrode metal film 6 is formed faces down.
A region excluding the semiconductor chip formation region 10a of the wafer 20 from the rear surface side of the wafer 20 so as not to cut the gate electrode metal film 5 and the source / drain electrode metal film 6 using a resist pattern (not shown) or the like as a mask. Is selectively removed by etching or the like to obtain a semiconductor member in which a plurality of semiconductor substrates 1 are connected to each other by a metal film 5 for a gate electrode and a metal film 6 for a source / drain electrode as shown in FIG.

This semiconductor member comprises a plurality of semiconductor substrates 1
Has a structure in which both ends are connected by a plurality of metal films 5 and 6 arranged on the semiconductor substrate 1 adjacent to each other among the plurality of semiconductor substrates 1,
If necessary, the metal films 5 and 6 connecting the semiconductor substrates 1 arranged adjacent to each other may be formed near the center thereof.
As shown in FIG. 3, electrodes 2 and 3 are separated from the semiconductor member 50 one by one by using a laser beam, a blade, or the like.
One end of each of the semiconductor chips 3 and 4 can take out the semiconductor chip 10 extending outside the semiconductor substrate 1. The mounting of the semiconductor chip 10 on the package is performed by arranging the semiconductor chip 10 on the bottom 11 of the package such that the surface on which the electrodes are formed faces the package bottom 11 as shown in FIG. , Package bottom 1
The portions of the source electrode 2, the gate electrode 3, and the drain electrode 14 extending outside the semiconductor substrate 1 with respect to the source-side line 12, the gate-side line 13, and the drain-side line 14, respectively, are soldered or crimped, or Bonding is performed by spot welding from the back surface side of the substrate 1, that is, welding by heat generated by passing an electric current using an electrode needle.

The semiconductor member 50 has a structure in which a plurality of semiconductor substrates 1 are connected to each other by a metal film 5 for a gate electrode and a metal film 6 for a source / drain electrode.
Since the plurality of semiconductor chips 10 have a structure in which the source electrode 2, the gate electrode 3, and the drain electrode 4 are connected to each other by portions extending to the outside of the semiconductor substrate 1, the semiconductor substrate is separated from the wafer as in the related art. This eliminates the need to collect a plurality of semiconductor chips that have been cut apart, and does not cause a problem that the plurality of chips that have been cut apart hit each other and break the chips. Further, when storing or carrying a plurality of semiconductor chips 10, the plurality of semiconductor chips 10 can be integrally handled in an aligned state, and if necessary, the metal film 5 for the gate electrode and the source By separating the drain electrode metal film 6, the semiconductor chips 10 can be easily taken out one by one. Therefore, it is very easy to handle the semiconductor chip 10 having a structure in which one end of the source electrode 2, the gate electrode 3, and the drain electrode 4 extends outside the semiconductor substrate 1. it can.

Further, by sliding the semiconductor members 50 while separating them one by one, the semiconductor chips 10 can be successively supplied on the bottom of the package or the like, so that the semiconductor chips 10 are attached to the package or the like. In this case, the semiconductor chips 10 can be efficiently arranged, and the productivity can be improved.

As described above, according to the semiconductor member of the first embodiment, the plurality of semiconductor substrates 1 are connected to each other by the gate electrode metal film 5 and the source / drain electrode metal film 6. There is an effect that a plurality of semiconductor chips can be handled integrally, and a plurality of small semiconductor chips having excellent element characteristics can be easily handled.

Embodiment 2 FIG. FIG. 4 is a plan view showing a structure of a main part of a semiconductor member according to a second embodiment of the present invention. In the figure, the same reference numerals as those in FIG. A metal film 16 is a metal film for source / drain electrodes.

In the second embodiment, in the semiconductor member described in the first embodiment, one of the gate electrode metal films 5 or the source / drain electrode metal films 6 connecting the adjacent semiconductor substrates 1 is formed. Instead, two metal films 15 for a gate electrode or a metal film 16 for a source / drain electrode are provided, and one end of each of the metal film 15 for a gate electrode and the metal film 16 for a source / drain electrode is connected to an adjacent semiconductor film. The semiconductor device 1 is electrically connected to one semiconductor element portion (not shown) of the substrate 1, and the other end is arranged in a portion other than the other semiconductor element portion (not shown) of the semiconductor substrate 1. It is designed not to be electrically connected to the unit. The gate electrode metal film 15 and the source / drain electrode metal film 16 are the same as those in the step of forming the gate electrode metal film 5 and the source / drain electrode metal film 6 described in the first embodiment. In this step, a predetermined resist pattern or the like is used, and the other parts are formed by the same steps as in the first embodiment.

In the first embodiment, the semiconductor element portions of the adjacent semiconductor substrates 1 are electrically connected to each other by the metal film 5 for the gate electrode and the metal film 6 for the source / drain electrodes. Each semiconductor chip 1 is kept in the state of the semiconductor member 50 without separating the semiconductor chip 1.
Although an electrical check of 0 could not be performed, in the second embodiment, since the semiconductor element portions of the adjacent semiconductor substrates 1 are electrically independent, each semiconductor chip 10 is cut out. Without this, an effect is obtained that an electrical inspection of each semiconductor chip 10 can be performed in the state of the semiconductor member 50.

In the semiconductor members according to the first and second embodiments, the case where a semiconductor chip having an FET element is obtained has been described. However, in the present invention, the case where a semiconductor chip having another semiconductor element is obtained is described. This is also applicable, and in such a case, the same effects as those of the first and second embodiments can be obtained.

Embodiment 3 FIG. 5 is a process chart showing a method for manufacturing a semiconductor chip according to Embodiment 3 of the present invention,
In the figure, the same reference numerals as those in FIG. 1 indicate the same or corresponding parts, 22 is a source electrode, 23 is a gate electrode,
3a is a gate portion, and 24 is a drain electrode. 5 (a) to 5 (d) show cross sections along the direction corresponding to the source / drain direction of the semiconductor chip, and the gate electrode metal film and the like are omitted. FIG. 5E is a perspective view. This semiconductor chip is the same as the source electrode of the semiconductor chip shown in FIG.
Portions of the gate electrode and the drain electrode that extend outside the semiconductor substrate have a three-dimensional structure that extends upward so as to form a predetermined angle with respect to the surface of the semiconductor substrate.

Next, a method for manufacturing a semiconductor chip will be described. Here, the description is made mainly on the manufacturing process of the metal film for the source / drain electrodes, but the metal film for the gate electrode is basically formed by the same method. First, similarly to the first embodiment, a plurality of semiconductor chip forming regions 10a each having a semiconductor element portion (not shown) are provided on a wafer 20 at predetermined intervals. Next, a resist 28 having a predetermined height is formed on the surface of the wafer 20 except for the semiconductor chip forming region 10a, as shown in FIG. In this figure, the cross section is triangular, but a resist having any cross section may be provided.

Next, the wafer 20 including the resist 28
A metal film 26a for plating and power supply made of an electrode material such as gold having a thickness of several hundred nm is formed on the surface of the metal film 26 by vapor deposition or the like, and on the metal film 26a, a metal film for source / drain electrodes is formed. A resist 29 having a pattern of a predetermined planar shape is provided, and the resist 29 is used as a mask to form an electrode material such as gold having a thickness sufficiently larger than the plating power supply metal film 26a, for example, a thickness of several μm by plating. A metal film 26b having a predetermined planar shape is formed. Subsequently, after the resist 29 is removed, dry etching is performed from above the wafer 20. By this dry etching, the plating power supply metal films 26a and 26b exposed on the surface are etched, but the plating power supply metal film 26a in a region other than the region where the metal film 26b is arranged is removed. When the etching is stopped at the point of time, the metal film 26b
Is sufficiently thick, the metal film 26b remains without being completely removed, and the remaining metal film 26b and the metal film 26b are not removed.
The metal film 26a for plating power supply arranged underneath "b" becomes the metal film 26 for source / drain electrodes (FIG. 5 (c)).
The planar shape of the source / drain electrode metal film 26 is
The shape is such that both ends are respectively located at positions where a source or drain electrode is formed on an adjacent semiconductor chip formation region.

Thereafter, after removing the resist 28, a region other than the chip forming region 10a of the wafer 20 is removed from the back surface of the wafer 20 by etching, and a plurality of semiconductor substrates 1 are separated from the wafer 20 (FIG. 5 (d)). 5), the semiconductor film 10 as shown in FIG. 5E is obtained by cutting the source / drain electrode metal film 26 at the center position between the adjacent semiconductor substrates 1.

Next, a method of attaching the semiconductor chip 10 to a package will be described. This semiconductor chip 10
Also, as shown in FIG. 3B in the first embodiment, the surface on which the electrode such as the source electrode 22 is formed is arranged so as to face the bottom 11 of the package. Source side line 12, Gate side line 1
3, the portions of the source electrode 22, the gate electrode 23, and the drain electrode 24 extending outside the semiconductor substrate 1 are soldered, crimped, or
Are connected by spot welding or the like from the back side of the. At this time, since the electrodes 22, 23, and 24 are made of a relatively soft material such as gold, a three-dimensional portion extending to the outside of the semiconductor substrate 1 is mounted on the bottom surface of the package. It is placed in a state where it is pushed to almost the same height as the surface of No. 1.

As described above, in a conventional semiconductor chip in which the source electrode, the gate electrode, and the drain electrode are formed so as to extend outside the semiconductor substrate to reduce the size and improve the device characteristics, the source electrode, the gate, and the gate are used. Since the portion of the electrode and the drain electrode extending outside the semiconductor substrate is provided on the extension of the surface of the semiconductor substrate, if the length of the portion of the electrode extending outside the semiconductor substrate is lengthened, one semiconductor chip is obtained. However, there is a problem that the required area on the wafer increases and the productivity decreases. For this reason, in the conventional semiconductor chip, the length of the part of the electrode extending outside the semiconductor substrate must be shortened, and the bonding of the semiconductor chip becomes a fine work, and the bonding cannot be easily performed. there were.

However, in the semiconductor chip 10 according to the third embodiment, the source electrode 22, the gate electrode 23,
In addition, since the portion of the drain electrode 24 extending outside the semiconductor substrate 1 has a three-dimensional structure extending upward so as to form a predetermined angle with respect to the surface of the semiconductor substrate 1, the substrate of these electrodes 22, 23, 24 is formed. The length of the portion extending outside the substrate 1 can be extended upward with respect to the surface of the substrate 1, and the length of the electrode portion extending outside the substrate 1 can be increased without increasing the distance between the semiconductor substrates 1. Becomes

Therefore, in the semiconductor chip 10 in which the electrodes 22, 23 and 24 are extended out of the semiconductor substrate 1 to reduce the size of the chip and improve the element characteristics, the length of the electrode portion extending out of the substrate 1 is increased. Bonding and the like can be facilitated, and there is an effect that the assemblability can be improved and the yield can be improved.

Similarly, in the case of obtaining a semiconductor chip in which the lengths of the portions of the electrodes 22, 23 and 24 extending outside the semiconductor substrate 1 are the same as those of the conventional semiconductor chip, the present embodiment is also applicable. According to the above, the distance between the semiconductor substrates 1 on the wafer 20 can be reduced as compared with the conventional semiconductor chip, and the number of semiconductor chips that can be manufactured from the wafer can be increased.

In the third embodiment, the shape of the electrode extending outside the substrate is linearly extended upward so as to form a predetermined angle with respect to the substrate surface. May be any shape as long as it is a three-dimensional shape extending upward. In such a case, the same effect as that of the third embodiment can be obtained.

Embodiment 4 FIG. FIG. 6 is a view for explaining a method of manufacturing a semiconductor chip according to a fourth embodiment of the present invention. In the figure, the same reference numerals as in FIG. 1 denote the same or corresponding parts, and 32 denotes a source electrode, 33 is a gate electrode, 33a is a gate portion, 34 is a drain electrode, 35 is a metal film for a gate electrode, and 36 is a metal film for source / drain electrodes. 6A, 6B, and 6D are perspective views, and FIG. 6C is a cross-sectional view taken along line VIc-VIc in FIG. 6B. This semiconductor chip 10 has a source electrode 3
2. Electrodes such as the gate electrode 33 and the drain electrode 34 have a shape in which one end is arranged on the upper surface of the semiconductor substrate 1 and the other end is arranged along the side surface of the substrate 1.

FIG. 11 is a view for explaining a method of attaching a semiconductor chip to a package according to the fourth embodiment of the present invention. In the figure, the same reference numerals as those in FIGS. 3 and 6 denote the same or corresponding parts. Numeral 11a denotes a concave portion which is fitted to the semiconductor chip 10 provided on the package bottom portion 11, and has end portions of a source line 12, a gate line 13, and a drain line 14 which are strip lines on the inner surface thereof. It has been extended. Next, a manufacturing method will be described. First, similarly to the method of manufacturing a semiconductor member described in the first embodiment, a plurality of semiconductor chip forming regions 10a each having a semiconductor element portion and arranged at predetermined intervals are provided on a wafer 20. Then, the region excluding the semiconductor chip formation region 10a from the surface of the wafer 20 is etched using a resist (not shown) or the like to a predetermined depth that does not reach the back surface of the wafer 20 (FIG. 6A). As a result, the semiconductor chip formation region 10a has a shape protruding in the height direction of the wafer 20 with respect to other regions.

Subsequently, using a resist pattern (not shown) or the like on the wafer 20, both ends thereof are respectively arranged on the mutually adjacent semiconductor chip forming regions 10a of the plurality of semiconductor chip forming regions 10a. Of the plurality of metal films, that is, the gate electrode metal films 35 whose both ends are arranged at positions where the gate electrodes of the respective semiconductor element portions of the adjacent semiconductor chip formation regions 10a are provided, and the adjacent semiconductor chip formation regions 10a. A source / drain electrode metal film 36 having both ends disposed at the position where the source or drain electrode is provided in each semiconductor element portion is formed by vapor deposition or the like (FIG. 6B). At this time, a metal film is formed on the side surface of the raised semiconductor chip formation region 10a.

Thereafter, as shown in FIG.
0 is disposed on a wafer mounting table (not shown) such that the surface on which the metal film such as the source / drain electrode metal film 36 is formed faces down. Using a resist pattern (not shown) or the like as a mask, a region other than the semiconductor chip formation region 10a of the wafer 20 is selectively removed by etching or the like to separate the semiconductor substrate 1, and then the source / drain electrode metal film 36 is separated. Is cut at a portion in contact with the side surface of the semiconductor substrate 1.
A semiconductor chip 10 as shown in FIG. 6D is obtained.

Next, a method of attaching a semiconductor chip will be described. First, as shown in FIG. 11A, a package having a concave portion 11a fitted on the semiconductor chip 10 on the bottom surface 11 is prepared in advance. Next, as shown in FIG. 11B, the semiconductor chip 1 of the fourth embodiment is
0 is fitted. At this time, a part of the strip line is previously arranged on the inner surface of the concave portion 11a of the package bottom 11, and when the semiconductor chip 10 is arranged in the concave portion 11a, By adjusting the position so as to be in contact with the electrode located on the side surface of the semiconductor device 10, the electrode of the semiconductor chip 10 and the strip line of the package can be brought into contact on the inner surface of the recess 11a. Then, a solder or the like is applied in advance to the strip line on the inner surface of the concave portion 11a of the package, and the electrode on the side surface of the semiconductor chip 10 and the strip line on the inner surface of the package concave portion 11a are bonded by solder. The chip 10 and the package can be electrically connected.

In the semiconductor chip according to the fourth embodiment, one end of electrodes such as the source electrode 32, the gate electrode 33, and the drain electrode 34 is provided on the side surface of the semiconductor substrate 1. Therefore, the concave portion 11 of the package is
By arranging the wiring at the position a in contact with the electrode on the side surface of the chip, it is possible to easily connect the electrode and the strip line with high positional accuracy simply by fitting the semiconductor chip 10 into the recess 11a. it can.

On the side of the semiconductor chip 10,
The semiconductor chip 10 can be used without performing wire bonding.
Since the connection between the chip 10 and the strip line of the package can be made, it is not necessary to provide a bonding pad or the like on the chip 10, so that the element characteristics can be improved and the chip can be downsized.

Further, since the electrodes do not extend outside the semiconductor substrate, there is no problem that the electrodes for connecting to the strip lines outside the semiconductor substrate are bent unlike the above-described conventional semiconductor chip, and the semiconductor chip does not have a problem. Handling is facilitated, connection defects between the electrodes of the semiconductor chip and the strip lines are reduced, and the yield is improved.

As described above, according to the fourth embodiment, one end of each of the source electrode 32, the gate electrode 33, and the drain electrode 34 is provided on the side surface of the semiconductor substrate 1. Are easily connected, and it is possible to provide a small-sized semiconductor chip having excellent device characteristics, which can improve the yield when the semiconductor chip is mounted on the package bottom.

Embodiment 5 FIG. 7 is a process chart showing a method for manufacturing a semiconductor chip according to Embodiment 5 of the present invention.
7A is a plan view, FIG. 7B is a sectional view taken along line VIIb-VIIb in FIG. 7A, and FIG. 7C is a perspective view. In the figure,
1 denote the same or corresponding parts, and
40 is a via hole, 42 is a source electrode, 43 is a gate electrode, 43a is a gate portion, 44 is a drain electrode, 45 is a gate electrode metal film, and 46 is a source / drain electrode metal film.

FIG. 8 is a view showing a state in which the semiconductor chip according to the fifth embodiment of the present invention is bonded to a package. In the figure, the same reference numerals as those in FIGS. 7 and 3 indicate the same or corresponding parts. ing.

In the semiconductor chip according to the fifth embodiment, a via hole 40 is provided in a portion of the semiconductor substrate 1 where the electrodes 42, 43, and 44 are arranged, near the end of the semiconductor substrate 1. Through this via hole 40, the strip line of the package and the electrode of the semiconductor chip 10 are connected by spot welding to form the semiconductor chip 1.
0 is a structure that can be bonded to a package.

Next, a method for manufacturing a semiconductor chip will be described. First, a plurality of semiconductor chip forming regions 10a provided with a semiconductor element portion (not shown) are provided on the wafer 20 so as to be in contact with each other. Subsequently, on the wafer 20, using a resist pattern (not shown) or the like, a plurality of metals whose both ends are respectively arranged on mutually adjacent semiconductor chip forming regions 10a among the plurality of semiconductor chip forming regions 10a. Film, that is, a metal film 4 for a gate electrode whose both ends are arranged at positions where the gate electrodes of the respective semiconductor element portions of the adjacent semiconductor chip formation region 10a are provided.
A metal film 46 for source / drain electrodes having both ends disposed at positions where the source or drain electrodes of the respective semiconductor element portions of the semiconductor chip forming region 10a and the adjacent semiconductor chip forming region 10a are provided is formed by vapor deposition or the like. Subsequently, the wafer 20
Is attached to a wafer mounting table (not shown) with wax or the like with the front surface of the wafer 20 facing down, and
A portion of the lower region of the gate electrode metal film 45 and the source / drain electrode metal film 46 where the adjacent semiconductor element formation regions 10a are in contact with each other is etched to form the gate electrode metal film 45 and the source / drain electrode metal film. A plurality of via holes 40 having a depth reaching 46 are provided (
FIG. 7 (a)).

Thereafter, as shown in FIG.
0 is cut out in units of the semiconductor chip forming region 10a by a diamond blade or the like, or a cut is made in the surface of the wafer 20, the wafer 20 is attached to an expandable sheet called an expanded sheet, and this sheet is stretched. By separating the semiconductor chip, a semiconductor chip 10 as shown in FIG. 7C is obtained.

Next, a method of attaching a semiconductor chip will be described with reference to FIG. First, as shown in FIG. 3B in the first embodiment, the semiconductor chip 10 is placed such that the surface on which the electrodes such as the source electrode 42 of the semiconductor chip 10 are formed faces the bottom surface 11 of the package. It is arranged on the package bottom surface 11. At this time, package bottom 1
The via holes 40 of the source electrode 42, the gate electrode 43, and the drain electrode 44 of the semiconductor chip 10 are arranged on the one source line 12, the gate line 13, and the drain line 14, respectively. I do. Then, spot welding is performed on the portions of the source electrode 42, the gate electrode 43, and the drain electrode 44 that are exposed in the via hole 40 from the back surface side of the semiconductor substrate through the via hole 40 to thereby form the package bottom surface 11
The source line 12, the gate line 13, and the drain line 14 of the semiconductor chip 10 are connected to the source electrode 42, the gate electrode 43, and the drain electrode 44 of the semiconductor chip 10, respectively, as shown in FIG. It is mounted on the bottom surface 11 of the package.

In the above-described conventional semiconductor chip in which the element characteristics are improved and the size is reduced, the electrode is extended out of the substrate instead of eliminating a bonding pad or the like which causes a parasitic capacitance. Is used for the bonding portion with the wiring, so that the stretched portion is not reinforced at all, and there is a problem that it is bent. However, in the fifth embodiment, the chip area is reduced by the semiconductor area. The via hole 40 is provided only in a region below the vicinity of the end of the semiconductor substrate 1 of the electrodes 42, 43, and 44, and spot welding is performed through the via hole 40 by the spot welding. From the back side of the substrate 1, the electrodes 42, 43, 44 and the transmission lines 12, 1
Since it is possible to connect the electrodes 3 and 14, there is no need to extend the electrodes of the semiconductor chip outside the substrate for the purpose of bonding, unlike the conventional case, and the electrodes outside the substrate are bent during the above-described handling. The problem that a defect occurs does not occur. Further, in this semiconductor chip, since the electrodes 42, 43, and 44 of the semiconductor chip 10 can be directly connected to the strip wiring on the package bottom 11 by welding, bonding pads are provided as in the above-described conventional semiconductor chip. Since it is not necessary, the parasitic capacitance does not increase, the element characteristics can be improved, and the semiconductor chip can be downsized.

As described above, according to the semiconductor chip of the fifth embodiment, the electrodes 42 and
Since the via hole 40 for spot welding is provided below the portion where the 43 and 44 are provided, there is an effect that a semiconductor chip that is small, has excellent element characteristics, and is easy to handle can be provided.

In the semiconductor chips according to the third to fifth embodiments, a semiconductor chip having an FET element has been described. However, the present invention can be applied to a semiconductor chip having another semiconductor element. In such a case, the same effects as those of the third to fifth embodiments can be obtained.

[0064]

As described above, according to the present invention, a plurality of semiconductor substrates arranged on the same plane and both ends of the plurality of semiconductor substrates are placed on adjacent ones of the plurality of semiconductor substrates. Since it is arranged and provided with a plurality of metal films that couple the adjacent semiconductor substrates,
Multiple semiconductor chips can be handled as one,
There is an effect that a semiconductor member which is small and can easily handle a semiconductor chip having excellent element characteristics can be obtained.

According to the present invention, the semiconductor substrate has a semiconductor element portion, and the metal film is electrically connected to only one semiconductor element portion of the adjacent semiconductor substrate. Since they are connected, there is an effect that a semiconductor member capable of performing an electrical inspection of each semiconductor chip while being integrated with a plurality of semiconductor chips is obtained.

Further, according to the present invention, a semiconductor substrate;
A metal film provided on the semiconductor substrate, one end of which is disposed on the semiconductor substrate, and the other end of which has a shape extending upward with respect to the surface of the semiconductor substrate outside the semiconductor substrate. Therefore, the length of the portion of the electrode of the semiconductor chip extending outside the substrate can be increased without reducing the number of chips obtained from the wafer, and the semiconductor chip can be easily attached to a package without reducing productivity. The effect is obtained.

Further, according to the present invention, a semiconductor substrate;
Since one end side is provided on the semiconductor substrate, and the other end side is provided with a metal film disposed along the side surface of the semiconductor substrate, a semiconductor chip which can be mounted on a package with high positional accuracy. The effect is obtained.

Further, according to the present invention, a semiconductor substrate,
A metal film disposed on the semiconductor substrate, near the edge of the semiconductor substrate, provided in a region located below the metal film, spot welding the metal film from the back side of the substrate to the metal film. And a via hole for performing the process, it is possible to reduce the size of the semiconductor chip without extending the electrode out of the semiconductor substrate, and to improve the device characteristics,
There is an effect that a small and easy-to-handle semiconductor chip with excellent element characteristics can be obtained.

[Brief description of the drawings]

FIG. 1 is a diagram showing a structure of a semiconductor member according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a method for manufacturing a semiconductor member according to the first embodiment of the present invention.

FIG. 3 is a diagram for explaining a semiconductor chip obtained from the semiconductor member according to the first embodiment of the present invention.

FIG. 4 is a plan view showing a structure of a semiconductor member according to a second embodiment of the present invention.

FIG. 5 is a diagram showing a method for manufacturing a semiconductor chip according to a third embodiment of the present invention.

FIG. 6 is a diagram illustrating a method for manufacturing a semiconductor chip according to a fourth embodiment of the present invention.

FIG. 7 is a diagram illustrating a method for manufacturing a semiconductor chip according to a fifth embodiment of the present invention.

FIG. 8 is a diagram showing a state where a semiconductor chip according to a fifth embodiment of the present invention is mounted on a package.

FIG. 9 is a diagram showing a structure of a conventional semiconductor chip.

FIG. 10 is a view showing a modification of a conventional method of attaching a semiconductor chip to a package.

FIG. 11 is a diagram illustrating a method of attaching a semiconductor chip to a package according to a fourth embodiment of the present invention.

[Explanation of symbols]

1,101 semiconductor substrate, 2,22,32,42,10
2 Source electrode, 3, 23, 33, 43, 103 Gate electrode, 3a, 23a, 33a, 43a, 103a Gate portion, 4, 24, 34, 44, 104 Drain electrode, 5, 15, 35, 45 For gate electrode Metal film, 6,
16, 26, 36, 46 Metal film for source / drain electrodes, 10, 100 Semiconductor chip, 10a Semiconductor chip formation region, 11 Package bottom, 11a recess, 1
2 source side line, 13 gate side line, 14 drain side line, 20 wafer, 26a metal film for plating power supply, 26b metal film, 28, 29 resist, 40, 1
30 via hole, 50 semiconductor member, 103b columnar member, 105 gate electrode lead, 106 drain electrode lead, 107 input side strip line,
108 output stripline, 109 input stripline substrate, 110 output stripline substrate, 201 input signal transmission line, 202 output signal transmission line. 203 Package bottom.

Claims (5)

[Claims] 1. A plurality of semiconductor substrates arranged on the same plane, and both ends thereof are respectively arranged on mutually adjacent semiconductor substrates of the plurality of semiconductor substrates, and the adjacent semiconductor substrates are connected to each other. And a plurality of metal films. 2. The semiconductor member according to claim 1, wherein said semiconductor substrate has a semiconductor element portion, and said metal film is electrically connected to only one of said adjacent semiconductor substrates. A semiconductor member characterized by being electrically connected. 3. A semiconductor substrate having a shape provided on the semiconductor substrate, one end of which is disposed on the semiconductor substrate, and the other end of which extends upward with respect to the surface of the semiconductor substrate outside the semiconductor substrate. A semiconductor chip comprising: 4. A semiconductor chip comprising: a semiconductor substrate; and a metal film having one end disposed on the semiconductor substrate and the other end disposed along a side surface of the semiconductor substrate. 5. A semiconductor substrate, a metal film disposed on the semiconductor substrate, and a metal film provided in an area near the edge of the semiconductor substrate and below the metal film. A semiconductor chip, comprising: a via hole for performing spot welding from the back side of the substrate.