JPH10209074A - Formation of wiring of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of forming wiring which assures stable electrical connection without degradation of barrier performance by forming a barrier metal within a contact hole. SOLUTION: An interlayer insulation film 4 is deposited on a semiconductor substrate 1 and a contact hole is formed on the interlayer insulation film 4. A Ti layer 6a is deposited on the surface of interlayer insulation film 4 and at the internal surface of the contact hole. On the surface of a Ti layer 6a including the contact hole, a TiN layer 6b is deposited under the atmosphere substantially excluding oxygen. After deposition of a TiN layer 6b, oxygen is additionally supplied to such atmosphere to deposit a TiON layer 6c on the TiN layer 6b. On the TiON layer 6c, a wiring layer 9 is deposited.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a wiring forming method for a semiconductor device, and more particularly to a wiring forming method for connecting a lower conductive region and an upper wiring through a contact hole formed in an interlayer insulating film.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit device, a barrier metal layer is interposed at a contact portion between a semiconductor substrate and a wiring layer.
A technique for preventing a reaction between the two and obtaining stable electrical contact is known. As the barrier metal layer, a Ti layer and Ti
A technique using lamination with an ON layer has been proposed (see Japanese Patent Application Laid-Open No. 4-214653). The Ti layer reduces the contact resistance between the semiconductor substrate and the wiring layer, and the TiON layer prevents a reaction between the wiring layer and the semiconductor substrate.

Further, a Ti layer, a T layer,
TiO formed by oxidizing the surface of iN layer and TiN layer
A technique using an N-layer three-layer structure has been proposed (see JP-A-5-6865 and JP-A-5-121356).

[0004] In this specification, "TiON"
Does not mean that the composition ratio of “O” and “N” is 1: 1. Usually, TiON used as a barrier metal layer is TiO _x N _1-x (x is about 0.1)
It is. When the TiON layer is deposited by sputtering, x changes by changing the amount of O ₂ added during sputtering.

[0005]

When a two-layer structure of a Ti layer and a TiON layer is used as a barrier metal layer, Ti
Deposit a TiON layer on top of the layer. According to an experiment conducted by the inventors of the present application, it was difficult to stably obtain good electrical connection by this method.

As a barrier metal layer, a Ti layer, a TiN layer,
Of TiON layer formed by oxidizing the surface of TiN layer and TiN layer
When a layer structure is used, only the very surface of the TiN layer is oxidized, so that the formed TiON layer is very thin.

When a blanket tungsten layer is deposited on the surface of the barrier metal layer and etched back to fill the contact hole with a tungsten plug, the TiON layer may be exposed at the bottom of the contact hole having a small aspect ratio during the etch back. is there. If the TiON layer is thin, the TiON layer in this portion is removed or becomes thinner, and the barrier performance is reduced.

An object of the present invention is to provide a method for forming a wiring in which a barrier metal layer is formed in a contact hole and a stable electrical connection can be obtained without lowering the barrier performance.

[0009]

According to one aspect of the present invention, a step of depositing an interlayer insulating film on a semiconductor substrate and forming a contact hole in the interlayer insulating film; And Ti on the inner surface of the contact hole.
Depositing a layer, depositing a TiN layer on a surface of the Ti layer including in the contact hole in a substantially oxygen-free atmosphere, and depositing the TiN layer;
There is provided a method for forming a wiring of a semiconductor device, comprising a step of additionally introducing oxygen into the atmosphere to deposit a TiON layer on the TiN layer and a step of depositing a wiring layer on the TiON layer.

Since the atmosphere for depositing the TiN layer on the surface of the Ti layer does not contain oxygen, oxidation of the surface of the Ti layer can be prevented. At the start of TiON layer deposition, Ti
Since the layer is not exposed, oxidation of the surface of the Ti layer by an oxidizing atmosphere during deposition of the TiON layer is prevented.

Since the TiON layer is deposited on the TiN layer, a relatively thick TiON layer can be easily formed as compared with the case where the surface of the TiN layer is oxidized.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Before describing embodiments of the present invention,
The following describes the results of an experiment for evaluating the contact resistance of a wiring structure using a TiON layer as a barrier metal layer.

The n-type and p-type impurity diffusion regions and the wiring layer were connected to the surface of the silicon substrate via contact holes having a diameter of 0.45 μm and an aspect ratio of 1.8. P ⁺ ions are implanted into the n-type region so as to have a dose of 5 × 10 ¹⁵ cm ⁻² , and BF ₂ ⁺ ions are implanted into the p-type region so as to have a dose of 2 × 10 ¹⁵ cm ^−2. Formed. On the bottom of the contact hole, between the wiring layer and the silicon substrate, a 20 nm thick Ti layer and a 100 n thick
m TiON layers are stacked. The TiON layer is made of Ti
After the layers were deposited by sputtering, they were deposited by reactive sputtering with O ₂ and N ₂ mixed in the sputter gas.

The contact resistance between the n-type region and the wiring layer is 55
Ω, the contact resistance between the p-type region and the wiring layer was 157 Ω, and both were non-ohmic contacts where the current was not proportional to the voltage.

The inventor of the present application failed to obtain good electrical contact because the interface between the Ti layer and the TiON layer was TiO 2.
It was considered that the layer was formed. In the example below,
The formation of the TiO layer can be prevented.

Referring to FIGS. 1 and 2, a method of forming a wiring according to an embodiment of the present invention will be described in the case where a source / drain region of a metal-oxide-semiconductor field effect transistor (MOSFET) is connected to an upper wiring. Will be described as an example.

As shown in FIG. 1A, a silicon substrate 1
An active region is defined on the surface of the silicon substrate 1 by the field oxide film 2 formed on the surface of the substrate. In this active region, a MOSFET including a source region 3S, a drain region 3D, a gate insulating film 3I, and a gate electrode 3G is provided.
Are formed. Sidewall insulators 3W are formed on the sidewalls on both sides of the gate electrode 3G. The side wall insulator 3W is used as a mask at the time of ion implantation for forming a low concentration drain (LDD) structure.

As shown in FIG. 1B, the entire surface of the substrate is covered by chemical vapor deposition (CVD) so as to cover the MOSFET.
An approximately 0.8 μm thick interlayer insulating film 4 having a laminated structure of phosphosilicate glass (PSG) and borophosphosilicate glass (BPSG) is deposited. Contact holes 5S and 5D having a diameter of about 0.45 μm are formed in the interlayer insulating film 4, and the source region 3S and the drain region 3D
Expose part of the surface of the

As shown in FIG. 1C, on the surface of the interlayer insulating film 4 and on the inner surfaces of the contact holes 5S and 5D, a Ti layer 6a having a thickness of about 20 nm, a TiN layer 6b having a thickness of about 25 nm, and A TiON layer 6c having a thickness of about 75 nm is laminated in this order.

The Ti layer 6a is deposited by using Ar as a sputtering gas at a substrate temperature of 150 ° C. and an atmospheric pressure of 4 mT.
orr, a sputtering gas flow rate of 15 sccm, and a film forming rate of about 100 nm / min. The TiN layer 6b is deposited by using Ti as a target and N ₂ as a sputtering gas.
Using a mixed gas of Ar and Ar, a substrate temperature of 150 ° C., an atmospheric pressure of 4 mTorr, an Ar gas flow rate of 40 sccm, and N
₍₂₎ Reactive sputtering is performed under the conditions of a gas flow rate of 85 sccm and a film formation rate of about 75 nm / min. TiO
The N layer 6c is deposited by reducing the Ar gas flow rate to 30 sccm after the TiN layer 6b is deposited, and introducing a new O ₂ gas at a flow rate of 10 sccm into a mixed gas of Ar and N ₂ to form the same Ti gas.
This is performed by reactive sputtering using a target.

As shown in FIG. 2A, the TiON layer 6c
A W layer 7 having a thickness sufficient to fill the insides of the contact holes 5S and 5D is deposited on the surface of the substrate by CVD. The W layer 7 is deposited, for example, at a flow rate of 80 s as a source gas.
ccm WF ₆ , H ₂ as a reducing gas, a growth temperature of 450 ° C., a pressure of 8 Torr, and a film formation rate of 0.3 to
It is performed under the condition of 0.5 μm / min. Contact hole 5
The inside of S and 5D is filled with the W layer 7.

As shown in FIG. 2B, the W layer 7 is etched back to remove all the W layer 7 deposited in regions other than the contact holes 5S and 5D. The etch back of the W layer 7 is performed by using SF ₆ or CBrF ₃ as an etching gas.
The dry etching is performed under the condition that the etching selectivity between the TiON layer 6c and the W layer 7 is about 1: (10 to 30). The W plugs 7S and 7D remain inside the contact holes 5S and 5D, respectively.

At this time, contact holes 5S and 5D
In order to prevent the unnecessary W film 7 from remaining in the region where no is formed, it is preferable to slightly over-etch. When over-etching, the W plugs 7S and 7
D has an upper surface slightly lower than the upper surface of the TiON layer 6c,
A shallow dent is formed in the region where the contact holes 5S and 5D are formed.

In FIG. 3A, W plugs 7S and 7
A thickness of about 15 nm made of Ti on the entire surface of the substrate including the upper surface of D
Is deposited. The underlayer 8 is deposited, for example, as shown in FIG.
This is performed by the same method as that for the Ti layer 6a described in (C).

On the underlayer 8, a wiring layer 9 having a thickness of about 400 nm and made of an Al alloy containing 1% by weight of Si and 0.5% by weight of Cu is deposited by sputtering. The wiring layer 9 is deposited by using, for example, an Al alloy as a target and Ar as a sputtering gas at a substrate temperature of 150 ° C. and a pressure of 2 m.
Torr, a sputtering gas flow rate of 20 sccm, and a film forming speed of about 1 μm / min.

After the formation of the wiring layer 9,
Heat treatment is performed at a temperature of about 450 to 500 ° C. for about 120 seconds. By this heat treatment, the Al alloy reflows, and the coverage ratio of the dent formed in the openings of the contact holes 5S and 5D is improved.

As shown in FIG. 3B, the wiring layer 9 is patterned and connected to the wiring 9S connected to the source region 3S via the W plug 7S and to the drain region 3D via the W plug 7D. The wiring 9D is formed. An interlayer insulating film 10 made of an insulating material such as PSG is deposited on the entire surface of the substrate by CVD or the like so as to cover the wirings 9S and 9D.

According to the above embodiment, the W plugs 7S and 7
Three layers of a Ti layer 6a, a TiN layer 6b, and a TiON layer 6c are interposed between D and the source / drain regions 3S and 3D. The TiON layer 6c acts as a barrier metal layer,
The reaction between the W plug and the surface of the silicon substrate is suppressed.

In the above embodiment, the TiON layer 6c is not directly deposited on the Ti
Deposit layer 6b. The surface of the Ti layer 6a is the TiON layer 6c
Since it is not exposed to an oxidizing atmosphere at the time of deposition, formation of a TiO layer can be prevented. Therefore, a good electrical connection can be obtained stably.

The thicknesses of the Ti layer, TiN layer, and TiON layer were set to 20 nm, 25 nm, and 75 nm, respectively, and other conditions were the same as in the above-described evaluation experiment. Connection made. As a result, the contact resistance between the n-type region and the wiring layer was 18Ω, and the contact resistance between the p-type region and the wiring layer was 110Ω, and both were ohmic contacts. Thus, by depositing the TiN layer before depositing the TiON layer, it is possible to obtain a good electrical connection.

In the above embodiment, since the TiON layer is deposited by reactive sputtering, a thick film can be easily formed as compared with the case where the surface of the TiN layer is formed by oxidation.

FIG. 4 is a sectional view of the substrate corresponding to FIG. 2B when a contact hole having a small aspect ratio is formed, that is, a sectional view of the substrate after the W layer is etched back. A W plug 7 is buried in a contact hole having a large aspect ratio like a contact hole on the left side in the drawing. On the other hand, in the contact hole having a small aspect ratio on the right side in the drawing, only the W region 7 remains on the side wall, and the W layer at the center of the contact hole is etched back together with the W layer on the interlayer insulating film 4. Would. For this reason, T
The iON layer 6c is exposed.

When the TiON layer 6c is thin, the TiON at the center of the bottom of the contact hole is formed by an etch-back process.
The layer 6c may be removed. TiON layer 6
When c is removed, the barrier performance in this part decreases.

In the above embodiment, since a relatively thick TiON layer can be easily formed, the TiON layer can be stably left on the bottom surface of the contact hole having a small aspect ratio. In order to stably leave the TiON layer even after the etch-back, the thickness of the TiON layer is preferably set to 50 nm or more. By leaving the TiON layer, a decrease in barrier performance can be suppressed.

The present invention has been described in connection with the preferred embodiments.
The present invention is not limited to these. For example, it will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

[0036]

As described above, according to the present invention,
The TiON layer is interposed between the surface of the semiconductor substrate and the wiring layer, so that the mutual reaction between the wiring layer and the surface of the semiconductor substrate can be prevented. Further, the electrical connection between the surface of the semiconductor substrate and the wiring layer can be stably obtained.

[Brief description of the drawings]

FIG. 1 is a sectional view (part 1) of a semiconductor substrate for describing a wiring forming method according to an embodiment of the present invention.

FIG. 2 is a sectional view (part 2) of a semiconductor substrate for describing a wiring forming method according to an embodiment of the present invention.

FIG. 3 is a cross-sectional view (part 3) of a semiconductor substrate for describing a wiring forming method according to an embodiment of the present invention.

FIG. 4 is a cross-sectional view of a semiconductor substrate for explaining a wiring forming method according to an embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Silicon substrate, 2 ... Field oxide film, 3S ... Source region, 3D ... Drain region, 3G ... Gate electrode, 3W
... sidewall insulator, 3I ... gate insulating film, 4 ... interlayer insulating film, 5S, 5D ... contact hole, 6a ... Ti
Layer, 6b ... TiN layer, 6c ... TiON layer, 7 ... W layer, 7
S, 7D W plug, 8 base layer, 9 wiring layer, 9S,
9D: wiring, 10: interlayer insulating film

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Harumitsu Fujita 10-1 Nakazawacho, Hamamatsu City, Shizuoka Prefecture Yamaha Corporation

Claims (4)

[Claims] An interlayer insulating film is deposited on a semiconductor substrate,
Forming a contact hole in the interlayer insulating film; depositing a Ti layer on the surface of the interlayer insulating film and on the inner surface of the contact hole; and forming a contact layer on the surface of the Ti layer including the inside of the contact hole. ,
Depositing a TiN layer in an atmosphere substantially free of oxygen, depositing the TiN layer, and then additionally introducing oxygen into the atmosphere to deposit a TiON layer on the TiN layer; Depositing a wiring layer on the TiON layer. 2. In the step of depositing the TiN layer,
2. The method according to claim 1, wherein the TiN layer is deposited by reactive sputtering of sputtering a Ti target in a nitrogen atmosphere. 3. A step of forming a buried region made of W on the surface of the TiON layer in the contact hole after the step of depositing the TiON layer and before the step of depositing the wiring layer. The method for forming a wiring of a semiconductor device according to claim 1, further comprising: 4. The step of forming the contact hole, the step of forming another contact hole larger than the contact hole and the step of forming the buried region simultaneously with the formation of the contact hole, Depositing a W layer over the entire surface; and forming the W layer until a top surface of the interlayer insulating film is exposed and a part of the surface of the TiON layer is exposed at a central portion of the bottom surface of the another contact hole. 4. The method of forming a wiring of a semiconductor device according to claim 3, further comprising a step of etching back and leaving the TiON layer at a central portion of a bottom surface of the another contact hole.