JPH10208646A - Ac type plasma display panel - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an AC type PDP(plasma display panel) which can suppress the reduction of the maintaining discharge voltage margine resulting from the unevenness of the thickness of a dielectric layer. SOLUTION: In this AC type PDP 32, resistors 38 to limit the current value flowing when an address discharge is generated are provided to plural address discharge electrodes 18 respectively. As a result, the current value flowing to the address discharge electrodes 18 in the address discharge time is decided by the resistors 38 exclusively, so as to suppress the variation of the discharge current value resulting from the variation of the thickness of the dielectric layers on maintenance-cum-address discharge electrodes 24b. Consequently, even when the thickness of the dielectric layers is made uneven, the unevenness of a wall charge amount formed in the address discharge time is suppressed, and the reduction of the maintaining discharge voltage margine resulting from the unevenness of the thickness of the dielectric layers is suppressed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in an AC type plasma display panel having a three-electrode structure having an address discharge electrode in addition to a sustain discharge electrode.

[0002]

2. Description of the Related Art A plurality of light emitting sections arranged along a predetermined first direction and a second direction intersecting the first direction, and a plurality of light emitting sections which are parallel to each other along the first direction while being covered with a dielectric material. A plurality of sustain discharge electrodes and a plurality of sustain and address discharge electrodes alternately arranged, and a plurality of address discharge electrodes arranged in parallel with each other along a second direction thereof; While selectively generating an address discharge between the address discharge electrode and the plurality of address discharge electrodes to form wall charges in a predetermined light emitting section, the plurality of sustain discharge electrodes and the plurality of sustain discharge electrodes are maintained. An AC-type plasma display panel (hereinafter referred to as an AC-type plasma display panel) of a type in which a predetermined sustain discharge voltage is applied between the electrode and an address discharge electrode to generate and maintain a display discharge in a predetermined light emitting section to emit light. That the AC-type PDP) has been known. For example, IEICE Technical Report (EID)
An AC type full-color PDP described on pages 17 to 21 of P. 92-79 (published in December 1992) is an example thereof.
Such an AC-type PDP is considered to be an image display device that replaces a cathode-ray tube because it can be easily made thin and has a large display surface, and can obtain a wide viewing angle and a fast response speed comparable to a cathode-ray tube.

As shown in FIG. 1, for example, a partially cutaway perspective view of the AC type PDP 8 forms an airtight space formed between a front plate 10 and a back plate 12 positioned parallel to each other. A plurality of discharge spaces 16 defined by longitudinal partitions 14 along one direction, and a plurality of address discharge electrodes passing between the partitions 14 on the back plate 12 along the one direction. 18 is provided,
A plurality of pairs of sustain discharge electrodes 24a and 24b for causing a display discharge in the plurality of discharge spaces 16 on the front plate 10 are covered with the dielectric layer 20 and the protective layer 22 and are orthogonal to one direction. They are provided alternately along the direction. The one sustain discharge electrode 24b also functions as an electrode for performing an address discharge with the above-described address discharge electrode 18 as described later. That. Also,
On the back plate 12, three types of phosphor layers 26 of R (red), G (green), and B (blue), which are separately applied to each discharge space 16, are provided.
Are provided, and the phosphor layer 26 is excited by ultraviolet rays generated by the surface discharge between the sustain discharge electrodes 24a and 24b to emit light, and the light is transmitted to the front plate 1 having translucency.
Fired through 0. In addition, each pair of sustain discharge electrodes 24
The transparent conductive films 28a and 24b have a large width and a pair of outer portions in the width direction on each pair of the transparent conductive films 28 in order to generate a surface discharge in a wide range and reduce the shielding of display light as much as possible. And a metal film 30 having a small width provided at an end portion to supplement its conductivity. Further, in the AC type PDP 8, a light emitting section is formed at each intersection of the address discharge electrode 18 and the pair of sustain discharge electrodes 24a and 24b.

[0004]

FIG. 2 shows the AC type P
FIG. 9 is a diagram showing an example of a drive waveform when DP8 is composed of 480 × 640 pixels. As shown in the figure, the AC type PDP 8 has a so-called period-separated type in which an address period Ta for selecting a light-emitting section and a sustain period Ts for performing display discharge (light-emission) in the selected light-emitting zone are separated. It is driven by a driving method. It should be noted that the figure shows a driving waveform in the case of displaying a gradation by dividing one TV field for displaying one image into a plurality of subfields and driving the same in a television using a cathode ray tube. Period Ta and sustain discharge period Ts
Constitute one subfield, but when gradation display is not performed, one subfield in FIG.
Just replace it with a field.

In the address period Ta, first, an erase pulse Ve is applied to all the sustain discharge electrodes 24a to erase wall charges in all the light emitting sections, thereby eliminating the influence of the lighting state of the previous subfield. I do. Next, a write pulse Vw is applied to all the sustain and address discharge electrodes 24b to form wall charges in all the light emitting sections.
Then, the erase pulse V is again applied to all the sustain discharge electrodes 24a.
e is applied to reduce the wall charge to a value at which the display discharge does not start. Thereafter, the sustain and address discharge electrode 24b-
Scanning is performed by sequentially applying a scanning pulse Vb to 1, 2,... 480, and at the same time, an address pulse Va is applied to a predetermined address discharge electrode 18 in synchronization with the scanning. This allows
Address discharge electrode 18 and sustain / address discharge electrode 24b
Are sequentially and sequentially address-discharged to form wall charges, and a light-emitting section to emit light is selected. Thereafter, in the sustain discharge period Ts, all the sustain discharge electrodes 24a, 24a,
Sustain discharge pulses Vs whose phases are different from each other by a half cycle are applied between 4b. At this time, the sustain discharge voltage V
Since s is set lower than the discharge starting voltage, no discharge occurs in the light-emitting section where no wall charge is formed, but in the selected light-emitting section where the wall charge is formed, the sustain discharge voltage Vs indicates the wall charge. Is superimposed and exceeds the discharge start voltage, so that a display discharge is generated and maintained, and the phosphor layer 26 is excited to emit light. According to such a driving method, display discharge is simultaneously performed on the entire surface during the sustain discharge period Ts, and the scan time of each of the sustain and address discharge electrodes 24b is extremely short. There is an advantage that a decrease in light emission duty due to an increase in the number of lines is suppressed.

In the driving method shown in FIG. 2, the amount of discharge current at the time of address discharge is maintained and the thickness of the dielectric layer 20 on the address discharge electrode 24b and the phosphor layer 26 on the address discharge electrode 18 are maintained. Is determined by the thickness of Note that the above driving method is not applicable to the case where the phosphor layer 26 is not provided as in the case of monochrome display using Ne light emission or the like.
Although the present invention can be applied to a C-type PDP, in that case, the discharge current value is determined solely by the thickness of the dielectric layer 20. However, since it is desired that the thickness of the dielectric layer 20 be reduced within a range having a withstand voltage sufficient to lower the sustain discharge voltage as much as possible, the thickness is generally several tens.
(μm), there is a problem that the discharge current value greatly varies due to a slight thickness variation of the dielectric layer 20, and the amount of wall charges to be formed tends to vary among the light emitting sections. As described above, the display discharge is started when the potential difference due to the wall charge is superimposed on the sustain discharge voltage and exceeds the discharge start voltage. Therefore, if the variation in the wall charge amount is large, the sustain discharge voltage margin (the sustain discharge voltage (The allowable range of variation of the discharge) becomes small, and discharge mistakes and erroneous discharges are likely to occur.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor device capable of suppressing a decrease in a sustain discharge voltage margin due to a variation in the thickness of a dielectric layer.
An object of the present invention is to provide a C-type PDP.

[0008]

In order to achieve the above object, the gist of the present invention is to provide a plurality of light emitting devices arranged along a predetermined first direction and a second direction intersecting the first direction. A plurality of sustain discharge electrodes and a plurality of sustain / address discharge electrodes, which are arranged in parallel with each other and alternately along the first direction while being covered with the dielectric, and along the second direction. A plurality of address discharge electrodes arranged in parallel with each other, and selectively generating an address discharge between the plurality of sustaining / address discharge electrodes and the plurality of address discharge electrodes to generate a predetermined address in a predetermined light emitting section. While a wall charge is formed, a predetermined sustain discharge voltage is applied between the plurality of sustain discharge electrodes and the plurality of sustain and address discharge electrodes to generate a display discharge in the predetermined light emitting section. and AC type P form to emit light by lifting
In the DP, there is provided (a) a current limiting device for limiting a current value flowing to the plurality of address discharge electrodes when the address discharge is generated.

[0009]

In this way, the AC type PDP has:
A current limiting device is provided for limiting the value of the current flowing through the plurality of address discharge electrodes when generating the address discharge. Therefore, the current value flowing to the address discharge electrode during the address discharge is determined exclusively by the current limiting device, so that the change in the discharge current value caused by the variation in the thickness of the dielectric on the sustain and address discharge electrode is suppressed. Is done. Therefore, even when the thickness of the dielectric varies, the variation in the amount of wall charges formed at the time of address discharge is suppressed, so that the decrease in the sustain discharge voltage margin due to the variation in the thickness of the dielectric is suppressed.

[0010]

In another preferred embodiment, the current limiting device is a resistor provided in series for each of the plurality of address discharge electrodes. In this way, the value of the discharge current flowing through each of the address discharge electrodes is limited by the resistor provided in series. At this time,
The resistance value of the resistor may be different for each address discharge electrode according to the variation of the discharge characteristics between the respective light-emitting sections, but in general, when a resistor is provided, when the discharge characteristics vary. Also, since the discharge current value is determined exclusively based on the resistance value of the resistor, a resistor having a constant resistance value corresponding to a desired current value may be provided for all the address discharge electrodes. The resistance of the resistor is preferably set in the range of 0.2 to 2.8 (kΩ).

Preferably, the current limiting device is a constant current device for supplying a constant current of a predetermined value to each of the plurality of address discharge electrodes. By doing so, the discharge current value flowing through each of the address discharge electrodes is maintained at the current value set in the constant current device. In addition, since heat generation that can occur when using a resistor is suppressed, power loss due to the heat generation is reduced, and I
C conversion becomes easy.

Preferably, the AC type PDP is a color PDP including a plurality of types of phosphor layers provided for the plurality of light emitting sections. In this way, the AC type PDP can perform multicolor display according to the type and arrangement of the phosphor layer, but at this time, it is caused by the difference in the dielectric constant and the thickness for each type of the phosphor layer. Variations in the discharge current value during the address discharge are suppressed by the current limiting device. Therefore, a decrease in the margin of the sustain discharge voltage due to the difference in the amount of wall charges formed by the address discharge between the light-emitting sections having different emission colors is suppressed. Incidentally, the dielectric constant of the phosphor layer is different for each type, that is, for each emission color, and the thickness is appropriately set depending on the luminous efficiency, chromaticity, and the like of the phosphor layer, and is not always constant. Therefore, in general, in an AC type PDP having a plurality of types of phosphor layers, such as an AC type full-color PDP, a single color phosphor layer is provided for each discharge space, that is, for each address discharge electrode. The discharge current values of the address discharge electrodes corresponding to the kinds of phosphor layers can be different from each other based on the difference in the dielectric constant and the thickness of the phosphor layers.

[0013]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 3 shows an AC type PDP according to an embodiment of the present invention.
It is a figure which shows the principal part structure of No. 32 typically. This AC type P
DP32 is an AC type P whose overall configuration is shown in FIG.
It is substantially the same as DP8, and the following description will focus on the differences. In the figure, the solid lines extending vertically above and below the AC type PDP 32 represent the address discharge electrodes 18, the solid lines extending left and right represent the sustain discharge electrodes 24a and the sustain / address discharge electrodes 24b, respectively, and the dashed lines extending vertically separate the discharge space 16 from each other. Of the partition 14 to be formed. The address discharge electrode 18 is
The AC type PDP 3 is provided for each discharge space 16.
2 is configured to divide the panel into upper and lower parts so as to drive the upper half and the lower half simultaneously, so that the address discharge electrodes 18 are electrically connected to the respective discharge spaces 16 at the intermediate portions in the longitudinal direction. Has been split. A resistor 38 is connected to each of the address discharge electrodes 18 in series between an output terminal 34 of a drive circuit (not shown) and an end 36 of the address discharge electrode 18. The resistor 38 is, for example, a fixed resistor having a resistance value in the range of about 0.2 to 2.8 (kΩ), and includes a plurality of address discharge electrodes 1.
8 have the same resistance value. The sustain discharge electrode 24a and the sustain / address discharge electrode 24b are drawn on the same straight line in the figure,
Actually, they are provided in parallel with each other as shown in FIG.

FIG. 4 shows an example of the driving waveform of the AC type PDP 32 described above. The AC PDP 32 may be driven by the driving waveform shown in FIG. 2, but will be described with reference to FIG. In addition, FIG.
The display discharge is maintained during the period of each subfield because it is a driving waveform in the case where one TV field is divided into eight subfields and driven in order to perform grayscale display with it. In the following description, the subfield may be read as 1 TV field.
In the figure, a first sustain discharge pulse of a negative voltage of about the potential Vs is constantly applied to the sustain discharge electrode 24a. The pulse width of the first sustain discharge pulse is, for example, Pw =
It is about 3.6 (μs), and the cycle is about Pc = 16 (μs). In addition, the sustain and address discharge electrode 24b is connected to the first
A second sustain discharge pulse having the same potential Vs, pulse width Pw, and cycle Pc as the sustain discharge pulse is constantly applied with a phase shift of half a cycle. The potential Vs is set so that the potential difference between the sustain discharge electrodes 24a and 24b becomes the discharge sustain voltage.

In the state where the first and second sustain discharge pulses are constantly applied as described above, during the writing period Tw starting from time t1, the sustain and address discharge electrode 24 is applied.
b, a scanning pulse of a negative voltage of about the potential Vwy, which is shaded in the figure, is applied and scanning is performed, and at the same time, the address discharge electrode 18 is synchronized with the scanning timing.
, A write pulse of a positive voltage of about the potential Vwa is applied. Each of the scanning pulse and the writing pulse has a pulse width of, for example, about Aw = 0.6 to 1.9 (μs), and the first sustain discharge pulse and the second sustain discharge as indicated by the dashed line at the left end of the drawing. The pulses are applied so as not to overlap with any of the pulses (so as not to match in time). The write pulse is, for example, A during a write period Tw until a scan pulse is applied to the next sustain and address discharge electrode 24b.
c = 8 (μs) and the writing period Tw is 1 H
(That is, 1 TV horizontal scanning period = value obtained by dividing one TV frame period for displaying one screen in a television using a cathode ray tube by the number of scanning lines) = about 63.5 (μs), so that the writing period Tw Eight peaks are located within. The above-mentioned scanning pulse is applied at a timing coincident with one of the writing pulses, in the drawing, the first writing pulse of each writing period Tw. An address discharge is generated between the electrode 24b-1 and the address discharge electrode 18 to which the write pulse is applied, and wall charges are accumulated at the intersection. At this time, since the resistor 38 is connected to the address discharge electrode 18 as described above, the discharge current value during the address discharge is limited to a value obtained by dividing the applied voltage by the resistance value. Therefore, even if the driving circuit does not particularly control, the discharge current is appropriately prevented from being excessively large, and a sufficient amount of wall charges is formed only in a desired light emitting section.

The scan pulse is sustained and the address discharge electrode 24
When the discharge sustaining voltage Vs is applied to the sustaining discharge electrode 24a at time t2 after the voltage is applied to b-1, the potential difference due to the wall charges is superimposed on the light emitting section where the wall charges are formed, and the voltage is higher than the discharge starting voltage. Will also be higher. Therefore, in the light emitting section where the wall charges are formed, the sustain discharge electrode 2
A display discharge is generated between 4a and 24b, and thereafter,
The discharge is maintained by the wall charges newly generated by the display discharge. Since the sustaining pulse is constantly applied between the sustaining discharge electrodes 24a and 24b, the display discharge is immediately generated as soon as the wall charges are formed. In the figure, the sustain discharge period Ts
Are drawn after the end of the writing period Tw, but as is clear from the above description, the sustain discharge period Ts
Starts substantially immediately after the application of the scanning pulse.

The sustain discharge (display discharge) started as described above is applied to the sustain / address discharge electrode 24b-4 at time t at the boundary between the subfields.
As shown in FIG. 3, an erasing pulse having a pulse width Ew of about 0.05 to 1.8 (.mu.s) is applied at a positive voltage having an absolute value of about a potential Ve smaller than Vs so as to overlap the sustain discharge pulse. Thus, when the sustain discharge is interrupted and the amount of wall charges formed on the sustain / address discharge electrode 24b-4 is reduced, the discharge starting voltage is maintained even if a sustain discharge pulse is subsequently applied to the sustain discharge electrode 24a. , The display discharge is stopped. The time until the display discharge is stopped is a period determined for each subfield in accordance with the number of display gradations. After the sustain discharge is stopped, a pause pulse having a potential equal to the discharge sustain voltage Vs is applied during a pause period Tp until time t4 when the writing period Tw of the next subfield starts. In the sustain / address discharge electrode 24b-4, the sustain discharge period T
s and the pause period Tp belong to mutually different subfields. The above-mentioned pause pulse corresponds to a combination of the first sustain discharge pulse and the second sustain discharge pulse, and is applied with a phase that coincides with any of them in a half cycle thereof. As a result, even if wall charges remain after the erase pulse is applied, the wall charges are gradually attenuated during the idle period Tp, and substantially before the start of the next writing period Tw. Will be erased. In the present embodiment, the address period T is calculated from the write period Tw and the pause period Tp.
a, and the idle period Tp is, for example, 2 H = 12
It is set to a length of about 7 (μs).

FIG. 5 is a graph showing the relationship between the resistance value of the resistor 38 and the sustain discharge voltage margin (the width of the sustain discharge voltage that can be displayed and discharged in all the selected light emitting sections without causing erroneous discharge). is there. As is clear from the figure, when the resistance value is 0 (kΩ), that is, when the resistor 38 is not provided, the sustain discharge voltage margin becomes about 0 (V) and driving becomes difficult, but the resistor 38 is provided. Thereby, the sustain discharge voltage margin is dramatically increased. When the resistance value exceeds a certain value (approximately 1.0 [kΩ] in the figure), the sustain discharge voltage margin tends to decrease, but this is because the discharge current value becomes too small and the amount of wall charge formed Is estimated to be reduced. In the present embodiment, the maximum value of the sustain discharge voltage margin is about 16 (V), but it is considered that it is preferable in terms of driving that a sustain discharge voltage margin of 8 (V) or more, which is the half value, is obtained. As can be seen from the figure, it can be said that the effect of providing the resistor 38 is effectively obtained when the resistance value is in the range of 0.2 to 2.8 (kΩ). Note that this range can be appropriately changed according to the discharge characteristics of each light emitting section.

In short, in this embodiment, the AC type P
The DP 32 is provided with a resistor 38 for limiting a current value flowing when an address discharge is generated, for each of the plurality of address discharge electrodes 18. Therefore, the value of the current flowing to the address discharge electrode 18 at the time of the address discharge is determined exclusively by the resistor 38, so that the value of the discharge current caused by the variation in the thickness of the dielectric layer 20 on the sustain and address discharge electrode 24b is reduced. Is suppressed. Therefore, even when the thickness of the dielectric layer 20 varies, the variation in the amount of wall charges formed during the address discharge is suppressed.
The reduction of the sustain discharge voltage margin caused by the variation of the zero thickness is suppressed.

If the address discharge current is too small, that is, if the address discharge is too weak, the amount of wall charges is too small, so that a luminous section in which no display discharge occurs despite the selection is generated. If the current is excessive, that is, if the address discharge is too strong, an erroneous discharge may occur in which light is emitted despite the fact that wall charges are also formed in the adjacent light-emitting sections along the address discharge electrode 18 and are not selected. Therefore, it is desired that the address discharge current has a small variation among the light emitting sections and is within a certain range.

In this embodiment, the AC type PDP
32 denotes R (red), G provided for each of the plurality of light emitting sections.
This is a color PDP including three types of phosphor layers 26 (green) and B (blue). Therefore, the AC PDP 32 can perform full-color display. At this time, the variation in the discharge current value at the time of address discharge due to the difference in the dielectric constant and the thickness for each type of the phosphor layer 26 is reduced by the resistor 38. Is suppressed. Therefore, a decrease in the sustain discharge voltage margin due to the difference in the amount of wall charges formed by the address discharge between the light-emitting sections having different light-emitting colors is suppressed, and a good full-color display can be obtained.

FIG. 6 is a diagram showing a configuration of another embodiment of FIG.
FIG. In this embodiment, the resistor 38
Are not provided, and the plurality of address discharge electrodes 18 are connected to the constant current device 40, respectively. This constant current device 4
0 indicates that a constant current is supplied to any address discharge electrode 18 in accordance with data in synchronization with the scan timing of the sustain and address discharge electrode 24b. For this reason, at the time of the address discharge, the constant current generated by the constant current device 40 flows through the address discharge electrode 18.
As in the embodiment shown in FIG. 3, variations in the discharge current due to variations in the thickness of the dielectric layer 20 and the like are suppressed, and a decrease in the sustain discharge voltage margin is suppressed. In addition,
As the constant current device, for example, a device formed of a bipolar transistor or the like and generating a constant current by controlling a current value applied to a base is preferably used.

While the embodiment of the present invention has been described in detail with reference to the drawings, the present invention can be embodied in other forms.

For example, in an embodiment, the present invention
Although the case where the present invention is applied to the type color PDP 32 has been described, the present invention is similarly applied to a monochrome type AC PDP having no phosphor layer 26.

In the embodiment shown in FIG.
Although the resistors 38 provided on all of the plurality of address discharge electrodes 18 are composed of fixed resistors having the same resistance value, the address discharge electrodes 1 may be changed according to the variation in the panel structure.
A fixed resistor having a different resistance value for each 8 may be provided as the resistor 38, or a semi-fixed resistor or a variable resistor may be provided as the resistor 38.

In the embodiment shown in FIG.
A constant current device 40 in which a plurality of address discharge electrodes 18 are common
However, the current values may be independently set by being connected to separate constant current devices.

Although not specifically exemplified, the present invention can be variously modified without departing from the gist thereof.

[Brief description of the drawings]

FIG. 1 is a perspective view showing a configuration of a conventional AC type PDP with a part thereof cut away.

FIG. 2 is an example of a driving waveform of the AC type PDP of FIG. 1;

FIG. 3 is a diagram illustrating a configuration of an AC PDP according to one embodiment of the present invention.

FIG. 4 is an example of a driving waveform of the AC type PDP of FIG. 3;

FIG. 5 is a diagram illustrating a relationship between a resistance value and a sustain discharge voltage margin in the AC PDP of FIG. 3;

FIG. 6 is a diagram illustrating a configuration of an AC PDP according to another embodiment of the present invention.

[Explanation of symbols]

 18: Address discharge electrode 20: Dielectric layer 24a: Sustain discharge electrode 24b: Sustain and address discharge electrode 32: AC PDP 38: Resistor (current limiting device)

 ──────────────────────────────────────────────────続 き Continued from the front page (72) Inventor Shigeo Mikoshiba 2-43-17 Izumi, Suginami-ku, Tokyo

Claims (4)

[Claims] 1. A plurality of light-emitting sections arranged along a predetermined first direction and a second direction intersecting the first direction, and a plurality of light-emitting sections parallel to each other along the first direction in a state covered with a dielectric. A plurality of sustain discharge electrodes and a plurality of sustain and address discharge electrodes alternately arranged, and a plurality of address discharge electrodes arranged in parallel with each other along the second direction;
An address discharge is selectively generated between the plurality of sustain / address discharge electrodes and the plurality of address discharge electrodes to form wall charges in a predetermined light emitting section, while the plurality of sustain / address discharge electrodes are formed. An AC plasma display panel of a type in which a predetermined sustain discharge voltage is applied between the plurality of sustain and address discharge electrodes to generate and maintain a display discharge in the predetermined light emitting section to emit light. 2. An AC plasma display panel according to claim 1, further comprising a current limiting device for limiting a value of a current flowing through the plurality of address discharge electrodes when the address discharge is generated. 2. The AC-type plasma display panel according to claim 1, wherein said current limiting device is a resistor provided in series for each of said plurality of address discharge electrodes. 3. The AC type plasma display panel according to claim 1, wherein said current limiting device is a constant current device for supplying a constant current of a predetermined value to each of said plurality of address discharge electrodes. 4. The AC plasma display panel according to claim 1, comprising a plurality of types of phosphor layers provided for each of said plurality of light-emitting sections.