JPH1020825A - Video signal converter for television game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a video signal converter for displaying a video of a TV game machine on a screen of a personal computer(PC) by connecting a TV game machine to a PC display, and especially to enable the connection between a multidisplay of a PC and a TV game machine. SOLUTION: A TV game machine is connected to a display for a PC by using an up-scan converter 1 (video signal converter) equipped with a double speed conversion circuit (consisting of a line buffer 21 and a clock generator 24) doubling the number of the main scanning lines per field by means of doubling only the horizontal scanning frequency of the vertical and horizontal frequencies of the TV game machine video signal. Thus, this arrangement makes it possible to view a video of a TV game machine on a high definition video screen by utilizing a high precision display for a PC use.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal converter, and more particularly, to a video game machine for connecting a video game machine to a display of a personal computer and displaying an image of the video game machine on the display of the personal computer. The present invention relates to a video signal conversion device for use.

[0002]

2. Description of the Related Art In recent years, video game machines have been widely used in homes and the like, and have been enjoyed. By the way, an image of such a video game machine is projected on a high-precision display for a personal computer (hereinafter, referred to as a personal computer), that is, an analog RGB monitor, and a high-resolution image utilizing the characteristics of the analog RGB monitor is produced. There is a demand to see.

[0003]

However, in the case of the NTSC system as the video of the TV game machine, the TV game machine is connected to the video terminal of the NTSC system television and used. It is impossible to display the screen even if it is directly connected to a display for a personal computer. That is, a general television, as described above,
SC method is used, and horizontal scanning frequency is 15.75k
Hz. However, that of the display for personal computers is 24 kHz or 31 kHz, and the screen cannot be displayed due to the difference in the horizontal scanning frequency.

In this case, if the scanning method of the video game machine and the display for the personal computer are the same, the component analog RGB signals output from the video game machine may be input to the display for the personal computer. Is a multi-display which is multi-layered for higher resolution and larger screen. Since the display is of the VGA type, it cannot support the lower scanning frequency side.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems. A video signal for connecting a video game machine to a display of a personal computer and projecting an image of the video game machine on the display of the personal computer is provided. An object of the present invention is to provide a conversion device, and in particular, to enable connection between a multi-display of a personal computer and a video game machine.

[0006]

For this purpose, the invention according to claim 1 is connected to an NTSC video game machine and a display of a VGA personal computer,
A video signal converter for a video game machine for converting a video signal of the video game machine into a video signal as a display signal, comprising: an input terminal connectable to the video output for the video game machine; An output terminal connectable to a video input;
In order to make the C-system interlaced scanning non-interlaced scanning, the number of scanning lines per field is increased by doubling only the vertical scanning frequency and the horizontal scanning frequency of the video signal for the video game machine. Is configured to have a double speed conversion circuit for doubling.

According to a second aspect of the present invention, the double-speed conversion circuit generates a signal of a line skipped by interlaced scanning using a memory, reads the signal at a double frequency, and executes a signal for one line. Is configured to scan two lines at twice the frequency where should be scanned.

The invention according to claim 3 is characterized in that the signal of the skipped line is obtained by reading the same signal twice so as to use the signal of the previous line as it is.

The invention according to claim 4 is configured to include a remote control circuit for turning on the power of the video signal conversion device for a video game machine when the video game machine is powered on.

According to a fifth aspect of the present invention, the personal computer has an input terminal connectable to an analog RGB output of the personal computer, and is connectable to a personal computer. A switching circuit is provided for switching from connection with the display to connection between the personal computer and the display, and when power is turned on, switching from connection between the personal computer and the display to connection between the video game machine and the display.

According to a sixth aspect of the present invention, the switching circuit comprises:
It consisted of a through circuit.

According to a seventh aspect of the present invention, the main body of the video signal conversion device for a video game machine is formed in a rectangular box shape whose height direction is flat.

According to an eighth aspect of the present invention, there is provided a video signal conversion device, wherein an LED lamp, a headphone connector, and a volume control lever are provided on a front portion of the video signal conversion device main body when the power is turned on. Has a video game machine A
A game machine connection connector connected to the V multi output terminal, a display connection connector connected to the input connector of the display, a personal computer connection connector connected to the output connector of the personal computer, and an AC adapter are connected. And a power supply connector.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the attached drawings. First, the basic concept of the video signal conversion device for a video game machine according to the present invention will be described. As described above, the display of a personal computer in recent years is a multi-display that is multi-layered for higher resolution, and cannot support a lower scanning frequency side. Therefore, the video signal conversion device of the present invention has a function of converting to a VGA compatible scanning frequency compatible with most multi-displays.

VGA specification horizontal scanning frequency is 31.5 kHz
z, which is set to about twice as large as 15.734 kHz of the NTSC system. The vertical scanning frequency is 60 for both.
Hz. Therefore, a configuration is adopted in which the scanning line of the video game machine is double-speed converted so as to be VGA specification. The above double speed conversion is the same as changing the interlaced scanning of the NTSC system to non-interlaced scanning.

Here, the NTSC scanning line system uses interlacing (interlacing) to reduce screen flicker.
Scanning is adopted. That is, as shown in FIG. 10, instead of scanning every other scanning line to lower the pixel density in the vertical direction, the field frequency (the number of screens per second) is set to two.
The doubling method is adopted.

In the interlaced scanning, one complete picture (frame) is completed in the first field and the second field. Therefore, in the case of the NTSC television, the number of scanning lines in one field is 262.5 and the number of screens is 30 / sec. As described above, in the interlaced scanning, the pixel density (the number of scanning lines) in the vertical direction per screen is reduced, so that the scanning becomes coarse and gaps between the scanning lines become visible, and this becomes more remarkable as the screen becomes larger. And the screen becomes hard to see.

In order to eliminate the deterioration of the pixel density in the vertical direction due to the interlaced scanning, the signal for each scanning line may be doubled. Then, the horizontal frequency is doubled while keeping the field frequency (vertical frequency) as it is,
There is a method of doubling the number of scanning lines per field.

As a result, the interlaced scanning is converted to the non-interlaced scanning, and the pixel density in the vertical direction can be increased, as shown in FIG.

In order to realize non-interlaced scanning conversion from such interlacing, it is only necessary to write a signal to a memory for each scanning line and read out data at twice the writing speed, which is double speed conversion (non-interlacing). This is the principle of (race conversion), and this is as shown in FIG.

As a specific method of the double speed conversion,
The signal of the line skipped by the interlaced scanning is generated using the memory, and the frequency is doubled (for example,
Reading is performed at a sampling rate of 4 fsc (corresponding to 8 fsc), and a portion where a signal for one line is to be scanned conventionally is scanned twice (two lines) at a double frequency.

There are various ways to create a signal (interpolation signal) of a skipped line. In the embodiment of the present invention, as shown in the figure, the signal of the previous line is used as it is (the same signal is used). (Read twice) Use the simplest method. This method uses a line signal for one signal input.
Use one buffer. Write at 4 fsc, 8 fs
Since the same signal is read at c, the same signal is read twice, and the signal read at the second time becomes an interpolation signal (see FIG. 13).

Next, a specific configuration of an embodiment of a video signal converter (hereinafter referred to as an up-scan converter) for a video game machine according to the present invention, which has been devised based on the above-described basic concept, will be described. . The up-scan converter is connected to the video game machine, and converts a video signal of the video game machine into a video signal which is a display signal for a personal computer by a circuit configuration described later. As shown in FIG.・ Scan converter 1
Is the display 3 for the video game machine 2 and the personal computer 3
Connect to A and use. The up-scan converter 1 is also connected to the personal computer 3, and can switch between the video game machine 2 and the personal computer 3 by using one display 3A.

In this case, one end of the RGB cable 4A is connected to the AV multi output terminal of the video game machine 2, and the up-scan converter 1 is connected to the other end. on the other hand,
Another RGB cable 4 for up-scan converter 1
B, and this is connected to the personal computer display 3A. Also, a cable 4 is connected to the up-scan converter 1.
C and connect it to the personal computer 3. The up-scan converter 1 additionally includes an AC (to be described later).
The adapter 33, the speaker with built-in amplifier 34, and the headphones 35 are connected.

A method of using the up-scan converter 1 will be described. First, an AC adapter 33 is connected to a household outlet, and the up-scan converter 1 is connected.
To the plug of the AC adapter 33. In addition, the up-scan converter 1 includes a speaker 34 with a built-in amplifier,
Headphones 35 are connected. When the personal computer 3 is connected, the personal computer 3 is operated, and the personal computer screen is displayed on the display 3A to check.

Next, when the power of the video game machine 2 is turned on, the display 3A switches from the personal computer screen to the game screen. When using the personal computer 3, when the power of the video game machine 2 is turned off, the display 3A is automatically set.
Switches to the PC screen.

Next, referring to FIG. 8 and FIG.
The main structure of the scan converter 1 will be described. The main body 1A of the up-scan converter 1 is formed in a rectangular box shape whose height direction is relatively flat, and a supporting leg 6 for mounting is provided on the bottom surface. Such a converter body 1A
LED lamps (P
POWER) 7 and a headphone connector (PHON)
ES) 8 and a volume control lever (VOLUME) 9 are provided.

At the rear of the converter main body 1A, an RGB cable 4A is connected to the AV multi-output terminal of the video game machine 2.
Game machine connector (IN) 10 connected via
A display connector (DISPLAY OUT) 11 connected to the input connector of the personal computer display 3 via the separate RGB cable 4B, and a personal computer connected to the output connector of the personal computer main body via a cable (not shown). Main unit connector (PC I
N) 12 and a power supply connector (DC9VIN) 13 to which an AC adapter 33 is connected, respectively.

Next, the circuit configuration inside the up-scan converter 1 will be described. First, an outline of the circuit configuration will be described based on the block diagram of FIG. In this figure, the circuit of the up-scan converter 1 has A /
A D converter (RGB 8 bits) 20, a line buffer (RGB 910 words × 8 bits) 21, a D / A converter (RGB 8 bits) 22, an amplifier (RGB) 23, a clock generator 24, a relay 25, a relay driver 26, and a regulator 27 It is comprised including.

The game machine connector (IN) 10-4 connected to the AV multi-output terminal of the video game machine 2
Audio signal left terminal and right terminal (AUDIO
L, R) 28 is a volume control lever (VOLUM).
E) Connected to audio amplifier 29 associated with 9).
The AUDIO L and R signals from the audio amplifier 29 are supplied to the headphone connector (PHONES).
8 is input.

The POWER terminal 30 is connected to a relay driver 26, and a relay control signal from the relay driver 26 is input to the relay 25. The relay 25
Is to select and switch between the connection between the analog RGB output of the personal computer and the display 3 and the connection between the AV multi-output of the video game machine 2 and the display.
The through circuit including the relay 25 corresponds to a switching circuit in the present invention. Thereby, one display 3
Can be used by switching between the video game machine 2 and the personal computer.

The analog RGB terminal 31 is connected to the A / D converter 20, and the A / D converter 20
Connected to a buffer 21 and the line buffer 21
/ A converter 22. The D / A converter 22 is connected to an amplifier 23, and receives an analog signal from the amplifier 23.
The GB signal is input to the personal computer display via the relay 25.

The NTSC video terminal 32 is connected to the clock generator 24. The clock generator 24 receives a 32HD signal and an 8fsc signal. The CLUMP signal output from the clock generator 24 is input to the A / D converter 20. or,
The 4fsc signal output from the clock generator 24 is input to the A / D converter 20 and the write (write) control unit 21A of the line buffer 21.

Further, the W-RST signal (write reset signal) is supplied to the write control unit 21A by the R-R signal.
The ST signal (read / reset signal) is input to the read (read) control unit 21B of the line buffer 21. The 8fsc signal is input to the read control unit 21B and the D / A converter 22.

The horizontal synchronizing signal H-SYNC and the vertical synchronizing signal V-SYNC output from the clock generator 24
C is input to the personal computer display via the relay 25. The regulator 27 is connected to the relay 25 and the LED lamp (POWER) 7.

Next, a schematic operation of the up-scan converter 1 having such a configuration will be described. The power supply system and the through circuit of the up-scan converter 1 will be described. First, when the power of the video game machine is turned on, the relay driver 26 operates, and 9 V DC supplied from the AC adapter 33 is supplied via the relay 25 to the regulator 2.
7 has a remote control circuit which is supplied to the circuit as analog and digital + 5V,
The up-scan converter 1 does not require a power switch, and is turned on by remote control from a video game machine.

At the same time, a personal computer body connector (PC
IN) 12 has passed through the relay 25 to the display connector (DISPLAY OUT) 11, and switches to a scan-converted signal. The audio system of the up-scan converter 1 will be described.
The pin connector specification has no audio signal and generally has few displays with built-in speakers. When using a video game machine, it is necessary to prepare some audio output.

Since a high-quality sound cannot be obtained even if a speaker is built in the video game machine, the sound of the video game machine is transmitted to a volume control lever (VOLUME) 9 and an audio amplifier 29.
Output to the stereo mini jack via
It can be connected directly to the active speaker of headphones or personal computer accessories.

Next, the video system of the up-scan converter 1 will be described. A component analog RGB video signal (hereinafter, referred to as an RGB signal) and a composite video signal are input from the AV multi-output, and the D-format of the personal computer display is input. The RGB signal corresponding to the sub15-pin connector specification is subjected to double speed conversion processing, and the video signal is used to generate a control signal required for double speed conversion processing.

In the double-speed conversion processing, the RGB signals are treated as signals of three systems, and the same processing of three systems is performed. In order to perform the double-speed conversion processing, as described above, one line of memory is required. Since a digital memory is used, first, an analog video signal is A / D-converted by the A / D converter 20, It is realized by writing to the buffer (memory) 21, reading at twice the speed, and performing D / A conversion by the D / A converter 22.

Next, the control signal system of the up-scan converter 1 will be described. The control signal includes a synchronizing signal required to cause the internal clock generator 24 to perform GEN-LOCK (genlock) and the color of the burst flag. Use the signal separated from the video signal. Necessary signals are a clamp signal for fixing an analog signal to a reference voltage at the time of A / D conversion, a 4 fsc clock signal at the time of writing to the A / D converter 20 and the line buffer 21, and a writing to the line buffer 21. Reset signal for determining the position, 8 fsc clock signal for reading from the memory and D / A conversion, reset signal for determining the reading position of the memory, horizontal synchronization signal H-
SYNC and a vertical synchronization signal V-SYNC.

In such a configuration, the A / D converter 20,
The line buffer 21, the D / A converter 22, and the clock generator 24 double only the horizontal scanning frequency of the vertical scanning frequency and the horizontal scanning frequency of the video signal for the video game machine to perform scanning per field. A double speed conversion circuit of the present invention for doubling the number of lines is configured.

Then, for one signal input, a line
The clock generator 20 uses one buffer 21
Based on the control signal from, the line buffer 21 performs writing at 4 fsc, performs reading at 8 fsc,
The same signal is read twice, the second read signal,
That is, a signal of the skipped line (interpolation signal) is created, and this signal is multiplied by a double frequency (4 fsc sampling /
(Corresponding to 8 fsc with respect to the rate).
Double-speed conversion is performed by scanning twice (for two lines).

As a result, the interlaced scanning is converted to non-interlaced scanning, the pixel density in the vertical direction can be increased, and the scanning line of the video game machine can be converted to the VGA specification by double speed conversion.

FIGS. 2 to 6 show actual circuit diagrams of the up-scan converter 1, and the operation of each system of the up-scan converter 1 will be described based on the circuit diagrams.

(Power supply system) DC9V supplied to CN4 from the AC adapter 33 of FIG. 1 enters a switch of RY3-8pin (see FIG. 14), and is driven by driving RY3.
The power is output to a pin and two power supplies of +5 V (VCC) for digital block and +5 V (AVCC) for analog block are supplied to each system via series regulators of IC8 and IC9.

(Main body switch system) Power ON / OFF
The CN5-4pin is the power ON / O of the video game machine
Since it changes to + 5V / 0V by FF, RY3-10pin becomes GND by turning on Q4, and C
LED lamp (POWER) 7 supplied directly from N4
(D3) is driven by driving RY3 to supply VCC and emit light.

(Through Circuit System) The signals of the display connector (DISPLAY OUT) 11 (CN2) are synchronized with the video R / G / B, H / V and DDC 9/12/1.
5pin is output and the video R / G / B and the synchronous H / V are
When the RY1,2,3 are not driven, they are connected to the common (3,8 pin) of each switch of RY1,2,3.
IN) 12 (CN1) is connected to the video R / G / B and synchronous H / V, and a personal computer body connector (PC IN) 1
2 (CN1) to display connector (DISP)
(LAY OUT) 11 (CN2).

When RY1, RY2, and RY3 are driven, the video R of the video game machine is converted into a scan-converted video R.
/ G / B and synchronous H / V are connected to the display connector (D
DISPLAY OUT) 11 (CN2).
The driving of RY1, RY2, RY3 is 7 pin by the driving of RY3.
+ 9V is generated in the RY1, 2 and supplied to 1pin
Since 10 pin is GND, RY1 and RY2 are driven. D1 and D2 are diodes for absorbing surge of the relay coil.

(Audio system) If the audio signal specification of the video game machine is, for example, "1.1-1.2 Vrms, impedance is 47 kΩ or more", the audio level does not need to be amplified, and it can be used for driving headphones or active speakers. Necessary impedance can be secured. The signal flow is CN
The R / L signal input to 5-2 and 3pin is volume-adjusted by a volume control lever (VOLUME) 9 (RV1) (see FIG. 15), and output to a stereo mini jack CN3 through an audio driver circuit. Since the audio R / L circuit is the same, the driver circuit on the L side will be described. Since the power supply voltage is only 5 V, the configuration is such that a sufficient voltage amplitude can be secured.

Volume control lever (VOLUME) 9 (RV
The audio signal whose volume has been adjusted according to 1) is DC cut at C36, biased at a bias voltage of about +3 V using the LED constant voltage characteristic of D3, and split into source-side Q5, 9 and sink-side Q7, 11. As the DC voltage matching, the source side is first set to the positive Vbe by Q5 and is set to the negative Vbe by Q9, so that the input potential and the output potential become the same. Q on the sink side
7 and 11, the potentials become the same, and since Q9-E and Q11-E have the same potential, power is saved because no bias current flows. The signal component has sufficient drive capability. Also, the voltage amplitude is about A on the plus side.
VCC-Vbe, and the minus side is secured to about GND + Vbe. The difference between the constants of R22 and R24 is that the bias voltage is not ＡＶ AVCC and that PNP and N
This is due to the difference in the characteristics of the PN transistors.

(Video System) Basically, the same processing is performed for the R / G / B signals, so only the R signal will be described.

(A) Signal termination The R / G / B signal specification of the video game machine is described as "for example,
In the case of “0.7 vp-p, impedance 75Ω, including DC component”, since the signal input from CN5-10pin is not DC-cut on the TV game machine side, after DC-cut at C2, it is determined by R1 Terminate at 75Ω.

(B) A / D conversion Thereafter, the signal is processed by the IC 1 for A / D conversion.
FIG. 16 is a block diagram of the IC1, in which a signal DC-cut by C5 is input to 4pin, and a 7pin bias voltage Vc1 is input by a clamp signal input to 6pin.
Is clamped by In order to produce Vc1, 1 pin Vrt and 10 pin Vrb are produced and supplied to ICs 1 and 3, as in the vicinity of IC2. R52 and 53 are provided with IC1,
A few characteristics are available.

(C) Memory The signal A / D-converted by the IC1 with 8 bits is input to the memory of the line buffer 21 (IC4). I
C4 is a high-speed line memory having a configuration of 910 words × 8 bits. When an NTSC video signal is quantized to 8 bits at a sampling rate of four times the frequency of the color subcarrier frequency (fsc) (14.3 MHz), 4fsc = 4 × 455 / 2fh = 910fh, where fsc is , The color subcarrier frequency (3.579545)
MHz) fh is the horizontal synchronization frequency (15.734265 MHz)
Thus, the configuration is such that exactly one line portion (one horizontal scanning line) can be stored. Therefore, it is most suitable for digitally processing a video signal, and one-line delay, time axis conversion, and the like can be easily realized.

FIG. 17 is a block diagram of the IC4.
The IC 4 has a built-in address pointer, and does not require an external address generation circuit. Further, since writing / reading can be performed independently and asynchronously, there is no need to use a double buffer configuration unlike the case where a general-purpose static RAM is used. Therefore, external signals for controlling this memory include a write clock (WCK), a read clock (RCK), and a write reset signal (RST).
W) and read / reset signal (RSTR).

The timing of the write operation will be described. The write cycle is, as shown in FIG.
When E is at the “L” level, one address (8 bits = 1 byte) is performed in one cycle in synchronization with WCK. The write address automatically increments one address each time a write cycle ends. Therefore, it is necessary to add write data to the rising edge of the cycle end of WCK so as to satisfy the setup and hold times.

The RSTW signal is a signal input for resetting the write address pointer to the 0 address as shown in FIG. Input is made so as to satisfy the setup and hold times with respect to the rising edge of WCK. The write address pointer is incremented by 1, 2, 3, 4... In synchronization with WCK, and when the address reaches the final address (909), the next address automatically returns to 0, Writing is performed again from address 0. When WE is at "H" level, no data is input, and the write address is stopped regardless of WCK.

The timing of the read operation will be described. The read cycle is, as shown in FIG.
When E is at the “L” level, one address (8 bits = 1 byte) is performed in one cycle in synchronization with RCK. The read address is automatically incremented by one each time the read cycle ends. Therefore, read data is output after the access time from the rising edge of the cycle end of RCK. RSTR
The signal is a signal input for resetting the read address pointer to the 0 address.

As shown in FIG. 21, an input is made so as to satisfy the setup and hold times with respect to the rising edge of RCK. The read is performed while the read address pointer is incremented one by one in synchronization with RCK. As in the case of write, 91 after reset
After performing 0 read cycles, the next address automatically returns to 0. When RE is at "H" level, reading is prohibited and the output becomes high impedance,
The read address also stops regardless of RCK.

(D) D / A Conversion and Voltage Amplification The signal output at 8-bit double speed by the IC 4 is input to the D / A converter 22 of the IC 7. IC7 is R / G / B
Are packaged in one package. This I
FIG. 22 shows a block diagram of C7.

(E) The signal output from the video driver IC7-37pin is reduced in impedance by the emitter follower of Q1, and DC is applied by C25.
After cutting, the signal is output via the coaxial matching resistor 75Ω of R17.

(Control Signal System) (a) The genlock of the clock generator 24 The video signal input from the CN5-6pin is DC-cut inside the video game machine, and thus terminates directly at R26. The signals necessary for gen-locking the clock generator 24 of the IC 10 are a horizontal synchronization separation signal, a vertical synchronization separation signal, and a chroma signal. FIG. 23 shows a block diagram of the IC 10.

The circuit of the input section for the horizontal synchronization separation signal and the vertical synchronization separation signal is configured as shown in FIG. The operation of the sync separation based on this circuit will be described. When the video signal of the sync negative polarity is input, the IC 10 is controlled by C of FIG.
The charging current Isp flows to o. Then, during a period other than the leading end of the synchronization (the lowest potential), the voltage at 36 pin becomes 2.2 V or more, and the transistor TR1 is cut off (the collector current of TR1 is reduced). For this reason, during this cutoff period, the electric charge charged in the Co becomes I through the Ro.
It is discharged with a current x. FIG. 25 schematically illustrates this state.

Assuming that Co is sufficiently large and Ix and Isp are linear, Isp and Vs in FIG. 25 are (Isp / Co) × 4 us = (Ix / Co) × 58.8.
6us∴Isp = (58.86us / 4.7us) × Ix = 1
2.5 × Ix Vs = Rx × Isp = 12.5 × Ix × Rx This Vs represents a slice voltage, and a portion below this voltage is amplified to perform synchronization separation. To determine the sync separation sensitivity, Vs is set by changing Rx.

When Vs is reduced, it is advantageous for the separation of the horizontal synchronization part, but is disadvantageous for the separation of the vertical synchronization part. Conversely, when Vs is increased, it causes synchronization failure (jitter) due to noise (whisker) in the horizontal synchronization portion. Therefore, the constant needs to be optimized according to the input signal. The value of Co is selected to be sufficiently large as compared with the charging / discharging current. However, if the value is too large, the transient response characteristic deteriorates and it becomes impossible to follow a sudden APL fluctuation of the input signal.

In the circuit shown in FIG. 24, the input is coupled with a capacitor for facilitating measurement, so that the circuit is weak against APL fluctuation. Therefore, when actually configuring the circuit, it is stronger to establish the potential at the synchronous tip using the SyncTip clamp circuit before inputting to the emitter follower in FIG. About 1.4 V (= A) divided by R27 and R28 in FIG.
VCC / (R27 + R28) × R28) minus Q13
Vbe potential at the bottom of the signal (SyncTi
p) is clamped.

In order to generate a clock synchronized with the burst signal, a chroma signal is input to the IC 10-4 pin. To make a chroma signal from a video signal, C4
5, through the 3.58 MHz trap by C46, L2, and R31 and through the buffer at Q15.

(B) Synchronization of color subcarriers 1 to 18 pins of the IC 10 in FIG. 23 are blocks mainly for generating a synchronization signal of color subcarriers.
The use of 10 allows the VOC to be used up to 8 fsc, and the up-scan converter requires a clock of, for example, a maximum of 8 fsc.
(= 28.63636 MHz). By the VOC, 8 fsc synchronized with the color subcarrier of the video signal of the video game machine is output to 16 pins of the IC 10. The output signal is subjected to TTL level logic processing, but since the output level is 1.3 vp-p, IC11
The signal is converted to a TTL level by F and 11A. The TTL level of 8 fsc (TP22 waveform) is
The RCKs 6 and 7 are supplied to the clock.

FIGS. 26 to 31 show waveforms at each test point. FIGS. 26A to 26G show cable input signals (R, R) to the video game console connector (IN) 10 (CN5) in the up-scan converter 1.
G, B, VIDEO, AUDIO-L, AUDIO-
R, POWER SW).

FIGS. 27A to 27E show a display connector (D) in the up-scan converter 1.
ISP PLAY OUT) 11 (CN2) signal (R,
G, B, H-SYNC, V-SYNC). FIGS. 28A and 28B show a headphone connector (PHON) in the up-scan converter 1.
ES) 8 (CN3) shows the waveform of the signal (L, R). FIGS. 29A to 29C show the waveforms of COLOR SYNC, FIGS. 30A to 30D show the waveforms of POWER, and FIGS. 31A to 31I show Sync Gen.
5 shows a waveform of an erector.

(C) Creation of 4fsc With an IC12AD type flip-flop, 8fsc is divided by 2 to create 4fsc (TP23 waveform), and IC1
6 for each clock, WCK.

(D) Horizontal and vertical synchronization 20 to 36 pins of the IC 10 shown in FIG. 23 are mainly blocks for generating horizontal and vertical synchronization signals.
The oscillator X2 for OC is 37 fh (= 503.5 KHz)
Is used. Each signal synchronized with the horizontal and vertical synchronization signals of the video signal of the video game machine by VOC, 23 pins
Horizontal sync HD (TP18 waveform), 22 pin clamp,
A 20-pin vertical synchronization VD (TP20 waveform) signal is used. The clamp signal CLUNP (TP19 waveform) is
Used as 1, 2, 3 clamp signals.

(E) Synchronization of horizontal synchronizing signal and color subcarriers The IC 10 itself cannot synchronize the output horizontal synchronizing signal with the color subcarriers.
B, 20A, when IC10-23pinHD falls, from the time when 4fsc rises, the next 4
Up to the time when fsc rises, IC20A-3pi
Output to nN-HD (TP24 waveform). However, IC
The jitter at the time of 10 horizontal synchronization separation and the jitter at the IC 16A are not taken, and the processing of this jitter will be described later.

(F) Double horizontal synchronizing signal In order to generate a double horizontal synchronizing signal of the NTSC system according to the VGA standard, using 4fsc, the NTSC horizontal synchronizing frequency fh = 2/455 × fsc = 4.
55 × 2 fsc ≒ 15.734 KHz VGA horizontal synchronization frequency 2fh = 2 × fsc = 2 × 455
× 2 fsc = 4 fsc / 455 ≒ 31.468 KHz fsc: chrominance subcarrier frequency (3.579545 MHz) As described above, if 4 fsc is divided by 455, a double horizontal synchronization signal can be generated.

In the circuit diagrams of FIGS. 2 to 6, 4 fsc is
Input to each clock of 2B, 13 and 14, IC11C-
6 pin outputs a negative pulse, so that IC12
The counters of B, 13, and 14 are in the loaded state, and the preset value of 000111001 (IC14-6, 5, 4,
3 pin, IC13-6, 5, 4, 3 pin, IC12
B-13pin) = 57, and when the full set 111111111 = 511, the IC
14-15 pin outputs a positive pulse, and IC1
Negative pulses are output again through 9, 11B and 11C, and the counter operates in a loop state.

The number of times of 4fsc in one cycle is from 57 to 511
Up to 455 times. One cycle at that time is 2fh, and the IC11C-6pin is RSTR (TP27 waveform).
Are used for reset signals of the ICs 4, 4, and 6. However, simply dividing the frequency of 4fsc by 455 is not synchronized with the video signal.

(G) How to Take Horizontal Synchronization and Jitter In the above description, there are 4fsc / 8fsc and HD jitter, and 2fh is in a free-run state. As a method of solving these problems at once, a feedback method is used in which a counter is created, a 455 counter is free-run if an HD pulse is contained in the gate, and the counter is forcibly preset when the gate is removed from the gate. .

In the circuit diagrams of FIGS. 2 to 6, the ICs 15A, 20
A gate is made by D, 15B, and 11E. The count number of the gate is 111111100 = 508 to 11111
If 1111 = 511 and 454 (start from 0) of the full set, 4/45 from 451 to 454
The gate has a width of 4 fsc (TP25 waveform). IC2
If a 4 fsc width pulse of N-HD is in the gate due to 0B, it will not be output to the IC 20B-6 pin (TP26 waveform) and the IC 19A will not be affected. N
A 4 fsc width pulse of -HD is output, and the output of the IC 19A is also affected, forcing the counter to be preset.

After presetting, N-HD does not occur at the timing of the first output gate (because it is double speed) and appears near the second gate. If it is not in the gate at that time, it is forcibly preset, and by repeating the operation, it stably enters the gate several times. Therefore,
The jitter is absorbed if it is within the range of 4/4 fsc = fsc ≒ 279 ns.

(H) Creation of H-SYNC In order to create VGA standard H-SYNC (TP29 waveform), ICs 18B and 19D are used to make IC 18B-11.
The rising pulse of 1111110000 = 496 = 439 is input to the pin, and the IC18B-13 pin is preset from 57 = 0 to 11111 = 63 = 6 when preset.
By inputting the i-level IC 13-11 pin, 23/4 from 439 to 454 and 0 to 6
fsc パ ル ス 1.606us width negative pulse is IC19D-1
Output to 3pin.

(I) Creation of V-SYNC In order to create VGA standard V-SYNC (TP30 waveform), the IC 17A, 17B, 18A, 20C, and 19C are used to clock the synchronized signal of the IC 14-11 pin. Then, after the falling pulse of VD is input, 2
× 2fh = fh ≒ 63.55 us width negative pulse is IC1
Output to 9C-10pin.

(I) Creation of RSTW Since the RSTW (TP28 waveform) only needs to intermittently form the RSTR, the RSTR and HD are input by the ICs 19B and 11D. RSTW is used for ICs 4, 5, and 6.

Using the up-scan converter 1 having the above-described configuration, the video game machine 2 is connected to the display 3 for a personal computer by simply connecting the video game machine 2 to the display 3 for a personal computer. The image is displayed on an analog RGB monitor, and a high-resolution image utilizing the characteristics of the analog RGB monitor can be viewed.

[0085]

According to the first aspect of the present invention, NTSC
In order to make the interlaced scanning of the system a non-interlaced scan, only the horizontal scanning frequency out of the vertical scanning frequency and the horizontal scanning frequency of the video signal for the video game machine is doubled to reduce the number of scanning lines per field to two. By using a video signal conversion device equipped with a double speed conversion circuit to double the
Just by connecting the video game machine to the display of a personal computer, the video of the video game machine is projected on a high-precision display for a personal computer.
It is possible to view a high-resolution image that takes advantage of the characteristics of the GB monitor.

According to the second aspect of the present invention, a double-speed conversion circuit generates a signal of a line skipped by interlaced scanning using a memory, reads the signal at a double frequency, and reads the signal for one line. Since the signal should be scanned, two lines are scanned at twice the frequency.
Double speed conversion can be performed with a simple circuit configuration.

According to the third aspect of the present invention, the signal of the skipped line is obtained by reading the same signal twice so as to use the signal of the immediately preceding line as it is. This is a simple method of creating a signal (interpolation signal) of the skipped line.

According to the invention of claim 4, since the remote control circuit for turning on the power of the video signal conversion device for the video game machine is provided when the video game machine is turned on, the power switch is not required.

According to the fifth aspect of the invention, when the power of the video game machine is turned off, the connection between the video game machine and the display is switched to the connection between the personal computer and the display. Is provided with a switching circuit for switching from connection of the video game machine to connection of the display.
The two displays can be shared and used by switching between a video game machine and a personal computer.

According to the sixth aspect of the present invention, since the switching circuit is constituted by a through circuit, the circuit configuration of the switching circuit is simplified.

According to the seventh aspect of the present invention, since the main body of the video signal converter for a video game machine is formed in a rectangular box shape whose height direction is flat, the main body of the video signal converter is made compact. And improve usability.

According to the eighth aspect of the present invention, an LED lamp, a connector for headphone, and a volume control lever are provided on the front portion of the video signal conversion device main body when the power is turned on, respectively. A game machine connection connector connected to an AV multi-output terminal of a video game machine, a display connection connector connected to an input connector of a display, a personal computer connection connector connected to an output connector of a personal computer; A power connector to which the adapter is connected,
Are provided, each connector and the like in the video signal conversion device main body can be arranged to be easily used, and usability can be improved.

[0093]

[Brief description of the drawings]

FIG. 1 is a block diagram showing a system according to an embodiment of a video signal converter (up-scan converter) for a video game machine according to the present invention.

FIG. 2 is a circuit diagram for explaining details of the above system.

FIG. 3 is a circuit diagram for explaining details of the above system.

FIG. 4 is a circuit diagram for explaining details of the above system.

FIG. 5 is a circuit diagram for explaining details of the above system.

FIG. 6 is a circuit diagram for explaining details of the above system.

FIG. 7 is a schematic diagram showing a connection state of the video signal conversion device according to the first embodiment;

FIG. 8 is a diagram showing an appearance of the video signal conversion device according to the first embodiment;
(A) is a front view, (B) is a rear view, and (C) is a right side view.

FIG. 9 is a plan view of the above.

FIG. 10 is a diagram illustrating a mechanism of interlacing.

FIG. 11 is a view for explaining the difference between interlaced scanning and non-interlaced scanning.

FIG. 12 illustrates the principle of a scan converter.

FIG. 13 is a diagram illustrating a double speed conversion method.

FIG. 14 is an internal connection diagram of RY3 in the above circuit diagram.

FIG. 15 is an internal wiring diagram of RV1 in the above circuit diagram.

FIG. 16 is a block diagram of IC1 in the above circuit diagram.

FIG. 17 is a block diagram of IC4 in the circuit diagram of Embodiment 1;

FIG. 18 is an explanatory diagram of a write cycle.

FIG. 19 is an explanatory diagram of a write reset cycle.

FIG. 20 is an explanatory diagram of a read cycle.

FIG. 21 is an explanatory diagram of a read reset cycle.

FIG. 22 is a block diagram of IC7 in the circuit diagram of Embodiment 1;

FIG. 23 is a block diagram of IC 10 in the circuit diagram of the above.

FIG. 24 is a diagram showing a synchronization separation circuit.

FIG. 25 is a sync separation waveform diagram in the sync separation circuit of the above.

FIG. 26 shows cable input signals (R, G, B, VIDEO, AUDIO-L, and AUDI) to the video game console connector (IN) in the up-scan converter.
FIG. 4 is a diagram showing a waveform of OR (power SW).

FIG. 27 is a diagram showing waveforms of signals (R, G, B, H-SYNC, V-SYNC) of a display connector (DISPLAY OUT) in the up-scan converter.

FIG. 28 shows a signal (L, L) of a headphone connector (PHONES) in the up-scan converter.
The figure which shows the waveform of R)

FIG. 29 is a diagram showing a waveform of COLOR SYNC;

FIG. 30 is a diagram showing a waveform of POWER.

FIG. 31 is a diagram showing a waveform of a Sync Generator.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Up-scan converter 1A Converter main body 2 Video game machine 3 Personal computer 3A Personal computer display 4 Cable 7 LED lamp 8 Headphone connector 9 Volume control lever 10 Game console connection connector 11 Display connection connector 12 Personal computer connection connector 13 Power supply connection connector Reference Signs List 20 A / D converter 21 Line buffer 22 D / A converter 23 Amplifier 24 Clock generator 25 Relay 26 Relay driver 27 Regulator 33 AC adapter 34 Speaker with built-in amplifier 35 Headphones

Claims (8)

[Claims] 1. An NTSC video game machine and a VGA
Video signal conversion device for a video game machine, which is connected to a display of a personal computer of a system for converting a video signal of the video game machine into a video signal which is a display signal, and which can be connected to the video output for the video game machine. An input terminal, and an output terminal connectable to a video input of a display of the personal computer; and a vertical scanning frequency of the video signal for a video game machine in order to make the interlaced scanning of the NTSC system non-interlaced. A video signal conversion device for a video game machine, comprising a double speed conversion circuit for doubling only the horizontal scanning frequency of the horizontal scanning frequencies and doubling the number of scanning lines per field. 2. The double speed conversion circuit generates a signal of a line skipped by interlaced scanning using a memory, reads the signal at a double frequency, and scans a signal for one line. 2. The video signal conversion device for a video game machine according to claim 1, wherein the image signal is scanned for two lines at a double frequency. 3. The signal of the skipped line is obtained by reading the same signal twice so as to use the signal of the immediately preceding line as it is.
The video signal converter for a video game machine according to the above. 4. The video game device according to claim 1, further comprising a remote control circuit for turning on the video signal converter for the video game machine when the video game machine is powered on. Video signal converter for video game machines. 5. An apparatus according to claim 1, further comprising an input terminal connectable to an analog RGB output of said personal computer, wherein said input terminal is connectable to a personal computer. 5. A switching circuit for switching between connection between a personal computer and a display and switching from connection between the personal computer and the display to connection between the video game machine and the display when the power is turned on. The video signal conversion device for a video game machine according to any one of the above. 6. The video signal conversion device for a video game machine according to claim 5, wherein said switching circuit comprises a through circuit. 7. The video signal conversion device for a video game machine according to claim 1, wherein the main body of the video signal conversion device is formed in a rectangular box shape whose height direction is flat. Video signal converter for video game machines. 8. An LED lamp that lights up when the power is turned on, a connector for headphone, and a volume control lever are provided on a front portion of the video signal conversion device main body, respectively. A game machine connection connector connected to the AV multi-output terminal of the PC, a display connection connector connected to the input connector of the display,
The personal computer connector connected to the output connector of the personal computer, and a power connector connected to an AC adapter are provided, respectively. The video signal converter for a video game machine according to the above.