JPH10207854A - Compiler instruction parallelizing system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To generate a high-speed object code by increasing the parallelism of the object code (object code for a computer which has arithmetic units capable of operating in parallel). SOLUTION: A dependency and parallel operation suppression graph generation part 321 generates a dependency and parallel operation suppression graph as a directional graph representing dependency relation and parallel operation suppression relation between instructions. A path latency and parallel operation suppression number calculation part 322 calculates a path latency and parallel operation suppression number on the basis of the dependency and parallel operation suppression graph generated by the dependency and parallel operation suppression graph generation part 321 and adds the calculation result to the dependency and parallel operation suppression graph. A scheduling part 323 schedules codes in parallel according to the dependency and parallel operation suppression graph to which the calculation result of the path latency and parallel operation suppression number is added.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a compiler instruction parallelizing method, and more particularly to a compiler instruction parallelizing method in a compiler for generating an object code for a computer (computer) having a plurality of operation units that can operate in parallel.

[0002]

2. Description of the Related Art Conventionally, this kind of compiler instruction parallelization method is used for a computer as described above (a computer which can execute a plurality of instructions in parallel and has a plurality of operation units which can operate simultaneously). Used to increase the efficiency of purpose codes.

[0003] As a conventional parallel instruction system of this kind, there are, for example, the ones described in the following patent gazettes.

Japanese Patent Application Laid-Open No. Hei 6-250847 discloses that
VLIW (Very Long)
There is described a technique for converting a VLIW instruction into a VLIW instruction that can be executed by a parallel computer of an Instruction Word) system. In the compiler instruction parallelization method described in this publication, after a parallel logic type language is converted into an abstract instruction sequence by a compiler, scheduling is performed in parallel by taking advantage of the features of the parallel logic type language, and furthermore, the dependency between instructions Scheduling is performed in parallel based on

[0005] JP-A-6-295246 discloses that
A technique is described in which scheduling is performed in a backward code compression phase to reduce the amount of registers used, to prevent delays in system processing, and to improve processing efficiency. In the compiler instruction parallelization method described in this publication, after a method called forward list scheduling, in which scheduling is performed in parallel based on dependencies, is applied, instructions are moved in a backward code compression phase, and register usage is reduced. Is reduced.

[0006] JP-A-6-131195 discloses that
A technique is described in which instructions are rearranged based on an analysis result of an instruction analysis unit that analyzes a dependency of each instruction in an instruction string represented by an assemble text created for an existing machine. In the compiler instruction parallelization method described in this publication, an instruction dependency graph is created based on an instruction sequence represented by an assemble text to analyze dependencies between instructions, and scheduling is performed in parallel based on the result. Done.

[0007]

The above-described conventional compiler instruction parallelization system includes a computer (a certain type of microprocessor) having a plurality of arithmetic units capable of executing a plurality of instructions in parallel and operating simultaneously. ) And resource conflicts (the same arithmetic unit cannot be used by multiple instructions), such as dependencies (relationships between instructions that occur due to reading registers written by one instruction with other instructions). In the case where there occurs a relationship in which parallel operations between instructions that occur due to causes other than the above occur, it is not always possible to optimally schedule the target code.

The reason that such a problem occurs is that the scheduling of the object code is performed based only on the dependencies between instructions and resource conflicts.

[0009] The relationship in which parallel operations between instructions caused by causes other than dependencies and resource conflicts become impossible (hereinafter referred to as "parallel operation suppression relationship") is as follows.
It often occurs in a microprocessor included in the technical field to which the present invention belongs. For example, in a Pentium processor (manufactured by Intel Corporation of the United States) having two operation units, an instruction that cannot be executed in parallel with another instruction, or another instruction only when the instruction is executed by a specific operation unit There is an instruction that can be executed in parallel. Restrictions on these instructions cannot be handled by dependencies or resource conflicts between the instructions.

SUMMARY OF THE INVENTION In view of the above, it is an object of the present invention to provide a compiler for generating a target code for a computer having a plurality of operation units which can operate in parallel. It is an object of the present invention to provide a compiler instruction parallelizing method capable of generating a compiler instruction.

[0011]

SUMMARY OF THE INVENTION A compiler instruction parallelization method according to the present invention is a dependency / parallel operation suppression graph for generating a dependence / parallel operation suppression graph which is a directed graph expressing a dependency relationship between instructions and a parallel operation suppression relationship. The path latency and the number of parallel operation suppressions are calculated based on the generation unit and the dependency / parallel operation suppression graph generated by the dependency / parallel operation suppression graph generation unit, and the calculation result is added to the dependence / parallel operation suppression graph. A parallel scheduling of codes based on a dependency / parallel operation suppression graph in which a path latency / parallel operation suppression number calculation unit and a path latency / parallel operation suppression number calculation result are added by the path latency / parallel operation suppression number calculation unit. And a scheduling unit for performing

Incidentally, the compiler instruction parallelizing method of the present invention can be constituted so as to have the following components.

The dependency / parallel operation suppression graph generated by the dependence / parallel operation suppression graph generation unit:
Determining the path latency of each instruction by tracing a node from the root of the directed tree in accordance with the directed side, and calculating the number of undirected sides emanating from each node to determine the number of parallel operation suppressions・ Parallel operation suppression number calculator

[0014] The scheduling unit that schedules instructions in order from the one with the highest path latency and schedules the instructions with the same path latency in the order from the instruction with the largest parallel operation suppression number.

[0015]

Next, an embodiment of the present invention will be described in detail with reference to the drawings.

[0016]

【Example】

(1) First Embodiment of the Present Invention FIGS. 1A and 1B are block diagrams showing the configuration of a first embodiment of the compiler instruction parallelization system of the present invention.

As shown in FIG. 1A, the compiler instruction parallelization method of this embodiment is realized by a compiler 100 including a front end 2 and a back end 3. The compiler 100 receives an input code 1 as an input, and outputs a target code 4 as an output.

The front end 2 performs lexical analysis and syntax / semantic analysis of the program as the input code 1, and outputs an intermediate language code.

The back end 3 includes an intermediate language optimization unit 31
And a code scheduling unit 32 and a target code generation unit 33.

The intermediate language optimizing unit 31 performs wide area optimization and local optimization on the intermediate language code.

The code scheduling unit 32 rearranges the instructions of the intermediate language code so as to increase the parallel execution. The code scheduling unit 32 corresponds to a main part of the present invention.

The target code generator 33 converts the intermediate language code into the target code 4.

Next, the detailed configuration of the code scheduling unit 32 will be described with reference to FIG.

The code scheduling unit 32
The parallel operation suppression graph generation unit 321 and the path latency
Parallel operation suppression number calculation section 322 and scheduling section 3
23.

The dependency / parallel operation suppression graph generator 321
Analyzes the dependencies between the instructions that make up the intermediate language code, and builds a directed graph based on this analysis. Further, the dependency / parallel operation suppression graph generator 321 also analyzes the parallel operation suppression relationship, and adds the parallel operation suppression relationship to the previously constructed directed graph. The directed graph constructed in this manner is called a dependency / parallel operation suppression graph.

Path Latency / Parallel Operation Suppression Number Calculator 3
22 calculates the path latency and the number of parallel operation suppressions using the dependence / parallel operation suppression graph.

The scheduling unit 323 rearranges instructions of the intermediate language code using the dependence / parallel operation suppression graph, the path latency, and the number of parallel operation suppressions.

FIG. 2 is a flowchart showing the processing of the code scheduling unit 32. This process includes a dependency directed graph expression step 201, a parallel operation suppression relation analysis step 202, a path latency calculation step 203,
It comprises a parallel operation suppression number calculation step 204 and an intermediate language code instruction rearranging step 205.

FIG. 3 is a diagram for explaining a directed graph (dependent / parallel operation suppression graph) generated by the dependence / parallel operation suppression graph generation unit 321.

FIG. 4 is a diagram showing an example of an output code as a result of scheduling by the scheduling section 323.

FIG. 5 is a diagram for explaining the operation of the compiler instruction parallelizing method of the present embodiment. The output code of the output code which is the scheduling result when the compiler instruction parallelizing method of the present invention is not used is assumed. It is a figure showing an example.

Next, the operation of the compiler instruction parallelizing system of the present embodiment configured as described above will be described.

First, the compiler 10 shown in FIG.
The general operation of 0 will be described.

Front end 2 in compiler 100
Converts the input code 1 into an intermediate language code. This intermediate language code is passed to the back end 3.

In the back end 3, first, the intermediate language optimizing unit 31 performs local optimization and wide area optimization on the intermediate language code.

Next, the code scheduling unit 32
Instructions are rearranged to improve parallel execution.

Further, the object code generation unit 33 converts the intermediate language code into the object code 4 and generates the object code 4 which is the output code of the compiler 100.

Second, the operation of the code scheduling unit 32, which is the main part of the present invention, will be described with reference to FIGS. 2, 3 and 4 together with FIGS. 1 (a) and 1 (b).

In the code scheduling unit 32, first, the dependence / parallel operation suppression graph generation unit 321 generates a dependence / parallel operation suppression graph.

That is, in order to generate a dependency / parallel operation suppression graph, the dependency / parallel operation suppression graph generator 321 first analyzes the dependencies between instructions, and converts the dependencies into directed graphs (initial dependency / parallel operations). (Inhibition graph) (step 201).

The dependency expressed by the dependency / parallel operation suppression graph will be described with reference to an example of the dependence / parallel operation suppression graph shown in FIG. In the dependency / parallel operation suppression graph, each instruction of the intermediate language code is represented by a node of the directed graph. “A” and “B” in FIG. 3 are nodes representing instructions. In the dependency / parallel operation suppression graph, the dependency is expressed by a directed edge of the directed graph. FIG.
For example, since the instruction B depends on the instruction a, there is a directed edge from the node a to the node B.

Next, the dependency / parallel operation suppression graph generator 3
21 is to generate a dependency / parallel operation suppression graph,
The parallel operation suppression relationship is analyzed, and the analysis result is added to the dependency / parallel operation suppression graph (step 202).

As described above, the parallel operation suppression relationship refers to a relationship in which parallel operation of two instructions becomes impossible due to causes other than the dependency relationship and resource conflict. As an example, "a relationship in which two instructions are executed in separate operation units but cannot be executed in parallel even though two instructions are executed by using a common circuit in a pipeline operation" is considered. The parallel operation suppression relationship is represented by an undirected side in the dependency / parallel operation suppression graph. Referring again to FIG. 3, for example, since the instruction B and the instruction e have a parallel operation suppression relationship, the node B and the node e are connected by an undirected side.

Path Latency / Parallel Operation Suppression Number Calculator 3
22 first calculates the path latency based on the dependence / parallel operation suppression graph, and adds the calculation result to the dependence / parallel operation suppression graph (step 203).

The path latency is defined as the number of cycles at which each instruction can be executed in the shortest time in the dependency / parallel operation suppression graph (for each node, the shortest execution time from the instruction corresponding to the root of the directed tree including the node) Number of possible cycles). Hereinafter, for convenience of explanation, it is assumed that the number of cycles required for execution of all instructions is 1, but it is needless to say that the compiler instruction parallelization method of the present invention can be applied to other cases.

Referring to FIG. 3, for example, an instruction B is an instruction a
Therefore, the instruction B cannot be executed unless the execution of the instruction a is completed. Since the instruction a has no dependent instruction, it can be executed first in this dependence / parallel operation suppression graph. In this case, 0 is given as the path latency of the instruction a. Since the number of cycles required to execute the instruction a is 1 based on the above assumption, the path latency of the instruction B is 1. In FIG. 3, the path latency is represented by a number near parentheses and not enclosed in parentheses.

Subsequently, the path latency / parallel operation suppression number calculation unit 322 calculates the parallel operation suppression number based on the dependence / parallel operation suppression graph, and adds the calculation result to the dependence / parallel operation suppression graph (step 204).

The number of parallel operation suppressions refers to the number of instructions having a parallel operation suppression relationship with each instruction. Therefore, in the dependence / parallel operation suppression graph, the number of undirected sides emerging from the node corresponding to the instruction corresponds to the parallel operation suppression number. Referring to FIG. 3, for example, the parallel operation suppression number of the instruction B is one. In FIG. 3, the number of parallel operation suppressions is represented by the number enclosed in parentheses near each node. However, instructions (nodes) that do not have a number enclosed in parentheses
, The parallel operation suppression number of the instruction is zero.

The scheduling unit 333 rearranges the instructions of the intermediate language code (predetermined scheduling) based on the dependency / parallel operation suppression graph finally constructed as described above (step 205).

The operation of the scheduling section 333 will be described with reference to FIGS. For the sake of explanation,
It is assumed that the object code 4 is an object code for a computer having two operation units operating in parallel (these are referred to as an operation unit and an operation unit).
Further, the operation unit in which the instruction is executed is determined for each instruction. For the instructions included in the dependence / parallel operation suppression graph of FIG. 3, the instructions a, e, f, and h are executed by the operation unit. Assume that B, C, D, and G are executed in an arithmetic unit.

In the present invention, the parallel scheduling method is based on the conventional list scheduling, but the scheduling is performed in consideration of the parallel operation suppression number which is a feature of the present invention. In the list scheduling, in the dependence / parallel operation suppression graph, among the schedulable instructions (instructions whose scheduling is not completed among the dependent instructions), the instruction having the largest path latency is determined as a candidate for scheduling. , An instruction sequence scheduled in the reverse direction (in order from the instruction executed later) is determined.

FIG. 4 is a diagram showing an instruction sequence scheduled by the compiler instruction parallelization method of this embodiment. The instruction sequence shown in FIG. 4 assumes that the instruction a and the instruction D are executed at the first clock, the instruction f and the instruction G are executed at the next clock, and thereafter, the respective instructions are executed similarly. This is a scheduled instruction sequence. In determining such an instruction sequence, in accordance with the above-described list scheduling method, scheduling is started in the order of instructions to be executed later, that is, the instruction e and the instruction C, and the scheduling is performed in the reverse direction.

Returning to FIG. 3, the process of scheduling the instruction sequence shown in FIG. 4 will be described. At first, since no instruction is scheduled, the instructions that can be candidates for scheduling are the instructions C, e, f, and h (instructions that are not the start nodes of the directed sides). Since the instruction C having the highest path latency is the instruction C, the instruction C is first scheduled (scheduled for the arithmetic unit). The remaining three instructions e, f, and h
Have a path latency of 1 and are all executed by the arithmetic unit, so that there is no resource contention with the instruction C. Therefore, one instruction can be arbitrarily selected from these instructions by a normal list scheduling method. Will be done.

According to the method of the present invention, when an instruction having the same path latency and causing no resource conflict with an already-scheduled instruction is a candidate for a schedule, the instruction having the maximum number of parallel operations suppressed is selected. You. However, instructions that have a parallel operation suppression relationship with already scheduled instructions are excluded. In FIG. 3, since the number of parallel operation suppressions of the instruction e is the maximum, the arithmetic unit is scheduled to execute the instruction e.

In the same manner, scheduling for obtaining the scheduling result shown in FIG. 4 is performed.

FIG. 5 shows that the instruction h is selected when one of three instructions e, f and h is selected in the arithmetic unit, regardless of the method of the present invention. The remaining scheduling results of the time are shown. Compared to the scheduling result of FIG. 4, which is the result of the scheduling according to the method of the present invention, it can be seen that the number of execution cycles is clearly larger and the performance of the generated target code is lower.

(2) Second Embodiment of the Present Invention FIG. 6 is a block diagram showing the configuration of a second embodiment of the compiler instruction parallelization system of the present invention. The configuration of the code scheduling unit 7 is the same as the configuration of the code scheduling unit 32 shown in FIG.

The compiler instruction parallelization method of this embodiment is as follows.
This is realized by a compiler 200 including a front end 2, a back end 5, a pre-schedule target code 6, and a code scheduling unit 7. Compiler 2
00, the input code 1 is input and the object code 4 is output.

The front end 2 performs lexical analysis and syntax / semantic analysis of the program as the input code 1, and outputs an intermediate language code.

The back end 5 includes an intermediate language optimization unit 31
And a target code generation unit 33, and outputs the pre-schedule target code 6 based on the intermediate language code.

The code scheduling unit 7 rearranges the instructions of the pre-schedule target code 6 so as to increase the parallel executability.

As shown in FIG. 6, the code scheduling unit 7 is not included in the back end 3 (the back end 5 in this embodiment) in the first embodiment shown in FIG. It exists at the position where the pre-schedule purpose code 6 to be input is input. In this point, the configuration of the second embodiment is different from the configuration of the first embodiment.

Next, the operation of the compiler instruction parallelizing system according to the present embodiment thus configured will be described.

In the first embodiment, the code scheduling unit 32 performs code scheduling (the above-described code scheduling unique to the present invention) on the intermediate language code output from the intermediate language optimizing unit 31. . On the other hand, in the compiler instruction parallelization method of the present embodiment (second embodiment), the code scheduling unit 7 performs predetermined code scheduling on the pre-schedule target code 6 output from the back end 5. Other operations are the same in the first embodiment and the second embodiment.

[0065]

As described above, according to the present invention,
By constructing a dependency / parallel operation suppression graph that reflects the parallel operation suppression relationship and calculating the path latency and the number of parallel operation suppressions, the efficiency of parallel code scheduling is improved, and the execution performance of the target code is improved. The effect occurs.

The reason why such an effect occurs is that an instruction having a large parallel operation suppression number is scheduled first based on the dependence / parallel operation suppression graph, so that the scheduling constraint due to the parallel operation suppression relation at a later stage of the scheduling process. This is because it is possible to prevent the occurrence of.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a first embodiment of a compiler instruction parallelization system according to the present invention (particularly, FIG. 1 (b) is a block diagram showing a detailed configuration of a code scheduling unit).

FIG. 2 is a flowchart showing processing of a code scheduling unit shown in FIG. 1 (b).

FIG. 3 is a diagram illustrating an example of a directed graph (a dependency / parallel operation suppression graph) generated by a code scheduling unit illustrated in FIG.

FIG. 4 is a diagram showing an example of an output code as a result of scheduling by a scheduling unit in FIG. 1 (b).

FIG. 5 is a diagram for explaining the operation of the compiler instruction parallelization method shown in FIG. 1 (a), and is a scheduling result of an output code which is a scheduling result when the compiler instruction parallelization method of the present invention is not used; It is a figure showing an example.

FIG. 6 is a block diagram showing a configuration of a second embodiment of the compiler instruction parallelization system of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Input code 2 Front end 3, 5 Back end 4 Object code 6 Object code before schedule 7, 32 Code scheduling part 31 Intermediate language optimization part 33 Object code generation part 100, 200 Compiler 321 Dependence and parallel operation suppression graph generation part 322 Path Latency / Parallel Operation Suppression Number Calculation Unit 323 Scheduling Unit

Claims (4)

[Claims] 1. A dependency / parallel operation suppression graph generation unit that generates a dependence / parallel operation suppression graph that is a directed graph expressing a dependency relationship between instructions and a parallel operation suppression relationship, and the dependency / parallel operation suppression graph generation unit A path latency / parallel operation suppression number calculating unit that calculates a path latency and a number of parallel operation suppressions based on the generated dependency / parallel operation suppression graph, and adds the calculation result to the dependence / parallel operation suppression graph; A compiler instruction having a dependency in which the calculation results of the path latency and the number of parallel operation suppressions are added by the parallel operation suppression number calculation unit; and a scheduling unit for performing parallel scheduling of codes based on the parallel operation suppression graph. Parallelization method. 2. A path latency of each instruction is determined by tracing a node from a root of a directed tree to a directed edge with respect to the dependency / parallel operation suppression graph generated by the dependence / parallel operation suppression graph generation unit. The path latency / parallel operation suppression number calculation unit that determines the number of parallel operation suppressions by calculating the number of undirected sides emerging from each node. 2. The compiler instruction parallelizing method according to claim 1, further comprising: the scheduling unit that schedules an instruction having a path latency in order from an instruction having a large parallel operation suppression number. 3. The compiler instruction parallelizing method according to claim 1, further comprising the scheduling unit for performing scheduling on the intermediate language code. 4. The compiler instruction parallelizing method according to claim 1, further comprising the scheduling section for performing scheduling on a pre-schedule object code.