JPH10207780A - Frequency counter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To extend the whole life of the frequency counter by reducing a difference between the rewriting frequency of a 1st storage area (level 1) and that of a 2nd storage area (level 2). SOLUTION: An IC card 10 has an EEP ROM 1 and a control circuit 2. The circuit 2 checks the value of a flag 7, and when the flag 7 is '0', controls the level 1 so as to store the value of the lower digit of frequency and controls the level 2 so as to store the value of the upper digit of the frequency. When the flag 7 is '1', the level 1 is controlled so as to store the value of the upper digit of the frequency and the level 2 is controlled so as to store the value of the lower digit of the frequency. The circuit 2 allows the EEP ROM 1 to execute frequency storing processing. In each addition of 400 points, the state of the flag 7 is inverted, so that the level 1 and the level 2 are set up so as to alternately store the value of the lower digit of the frequency.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency counting device for sequentially adding given frequencies each time a command for adding frequencies is given and storing the frequencies obtained by the addition, and more particularly to a frequency counting device. The present invention relates to a frequency counting device that can be used for a long period of time by efficiently using a storage area such as an EEPROM for storing data.

[0002]

2. Description of the Related Art Conventionally, a frequency counting device of this type is known as an EEP.
It is configured as a portable module such as an IC card having a storage circuit such as a ROM. When an instruction to add a frequency (frequency addition command) is given from the card reader, the frequency counting device converts the frequency given by the frequency addition command into EE.
The PROM then adds to the stored frequency (the sum of the frequencies given by the frequency addition command input to the frequency counting device so far) and stores the frequency obtained by the addition. Things.

[0003] Specifically, an EEPROM is divided into a plurality of levels each consisting of a plurality of bits. This E
In the EPROM, for example, an instruction (1
Each time a frequency addition instruction is given, the least significant bit is set to "1" one bit at a time. Then, when all the bits at the lowest level become “1”, 1
In response to the frequency addition instruction being applied, one bit of the next higher level is set to "1", and all bits of the lowest level are set to "0".

As described above, the conventional frequency counting device is
When all the bits at the lowest level change from “0” to “1”, carry from the lower level to the upper level (carry processing) is performed.

[0005]

In the frequency counting apparatus, the upper level always stores the value of the upper digit, and the lower level always stores the lower digit. Therefore, the number of times of rewriting (composed of writing and erasing) of the lower-level bits storing the value of the lower digit is necessarily larger than the number of rewriting of the upper-level bits storing the value of the upper digit.

Therefore, the life of the lower level bit comes before the life of the bit of the upper level comes. Therefore, there is a problem that the life of the frequency counting device as a whole depends on the life of the lower-level bits irrespective of the upper level and is short.

[0007]

A frequency counting apparatus according to the present invention comprises a flag having a first state and a second state, a first storage area having a plurality of bits, and a second storage having a plurality of bits. A frequency in the first storage area and the second storage area, and when the flag is in the first state, the first storage area stores a value of a lower digit of the frequency. And the second storage area stores the value of the upper digit of the frequency, and when the flag is in the second state, the first storage area stores the value of the upper digit of the frequency. A second storage area for storing a value of a lower digit of the frequency, and a memory when the frequency stored by the storage circuit exceeds a predetermined value, or the first or second storage area. A control circuit for inverting the state of the flag when the number of rewrites of the storage area exceeds a predetermined value; Characterized in that it has.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a schematic configuration diagram of an IC card showing a first embodiment of a frequency counting device according to the present invention.
The IC card 10 which is a portable module shown in FIG.
It has an EEPROM 1 and a control circuit 2. IC card 1
0 is activated when the card is inserted into the card reader 20, and the frequency given by the frequency addition command is stored in the frequency (the frequency given by the frequency addition command input to the IC card 10 until then). To the EEPR.
It is stored in the OM, the operation is stopped when it is removed, and the frequency is stored and held.

The IC card 10 and the card reader 20
A power supply line VCC for supplying power to the C card, a ground line GND, a clock line CLK for supplying an operation clock to the IC card, a reset line RST for resetting the control circuit 2 of the IC card, and a card reader 20 Is transmitted to the control circuit 2 and the EEPRO
It is connected by a serial data line SIO that transfers the frequency data read from M1 to the card reader 20.

The EEPROM 1 has a Y address decoder 3, an X address decoder 4, a control / data interface (I / O) 5, and a unit cell area 6. EEP
The ROM 1 can be erased / written by specifying a bit.

The unit cell area 6 stores frequencies.
It has a level of 10 bits (10 cells), a level 2 of 10 bits, a level 3 of 5 bits, and a flag 7 of 1 bit.

In the unit cell, charge is injected into the floating gate by erasing, and charge is extracted from the floating gate by writing. In the following description, the initial value of the bit and the write state are associated with each other and are expressed as “0”. In addition, the inverted value of the bit and the erased state are associated with each other and are expressed as “1”. Note that the initial value and the erased state may be associated with each other, and the inverted value and the write state may be associated with each other.

The Y address decoder 3 and the X address decoder 4 operate according to address data from the control circuit 2.
Specifies a bit for erasing, writing, or reading. The I / O 5 writes data to bits designated by the Y address decoder 3 and the X address decoder 4 in response to a write command (W), an erase command (E), and a read command (R) from the control circuit 2. , Erase, or read data, and sends the read frequency data and the data relating to the flag 7 to the control circuit 2.

The control circuit 2 checks the value of the flag 7, and when the flag 7 is "0", controls so that the level 1 stores the value of the lower digit of the frequency and the level 2 controls the upper digit of the frequency. When the flag 7 is "1", the level 1 is controlled to store the value of the upper digit of the frequency.
In addition, control is performed so that level 2 stores the value of the lower digit of the frequency. The control circuit 2 inverts the value of the flag 7 each time 400 degrees are added. When a frequency addition command is input from the card reader 20, the control circuit 2
Sends address data and an erase / write command to M1,
The EEPROM is made to execute a frequency storage process. As a result, the frequency stored in the EEPROM 1 is rewritten.
The control circuit 2 may be realized by hardware means, or may be realized by software processing by a microprocessor.

FIG. 2 and FIG. 3 are diagrams for explaining the frequency count storage processing in the IC card of FIG. First 1
The operation of the frequency counting device until 400 frequencies are stored will be described. In this period, since the value of the flag 7 is “0”, the control circuit 2 controls the level 1 to store the value of the lower digit of the frequency, and the level 2 controls the value of the upper digit of the frequency. It is controlled to memorize.

First, every time a one-time addition instruction is given,
The bit of level 1 is set to "1" one bit at a time from bit b0 as shown in FIG. This allows 1-1
Zero frequency is stored. After all the bits of level 1 have become "1" ((b), 10 times), when a 1-time addition instruction is given, the level 1 bit b0 is set to "0".
((C), 11 frequency) Thereafter, every time a frequency addition instruction is given, the bit which is "1" at level 1 is set to "0" bit by bit.

Next, after all the bits except for the bit b9 of level 1 become "0" ((d), 19 times), when a one-time addition instruction is given, the bit b0 of level 2 becomes "1".
(E), and the level 1 bit b9 is set to “0” ((f), 20 degrees). As a result, carry from level 1 to level 2 is performed.

The bits b0 to b9 of level 1 are rewritten once by giving the one-time addition instruction 20 times. (In this case, rewriting consists of erasing and writing.) Next, until the frequency of 21 to 219 is stored, level 1
In the same manner as described above, the bits in which all bits are "0" are set to "1" one bit at a time each time the one-time addition instruction is given, and after all bits become "1", all bits are set to "1".
The process of setting the bit of "1" to "0" by one bit each time the one-time addition instruction is given is repeated. Is repeatedly set to “0.” At level 2, every time the frequency addition instruction is given 20 times, the bit that is “0” of level 2 is set to “1” one by one.

Next, after all the bits of the level 2 become "1" and all the bits except the bit b9 of the level 1 become "0" ((g), 219 frequencies), a 1-time addition instruction is given. As a result, the level 2 bit b0 is set to "0" and the level 1 bit b9 is set to "0". ((H), 220 frequencies) Next, until the frequencies of 221 to 399 are stored, at level 1, as described above, all bits are “0”.
Each time a one-time addition instruction is given, one bit is set to "1".
After all the bits are set to "1", the process of setting the bits whose all bits are "1" to "0" one by one each time the one-time addition instruction is given is repeated. . At level 2, every time the 1-time addition instruction is given 20 times, the bit that is “1” of level 2 is changed by 1 bit.
It is set to 0 ".

Next, bit b9 of level 1 and level 2
After all the bits except for have become “0” (399 counts), a one-time addition instruction is given, and the level 3
Is set to "1", and all bits of level 1 and level 2 are set to "0". ((I), 400
Here, the value of the flag 7 is set to “1”.

Next, the operation of the frequency counting device during the period until the frequencies 401 to 800 are stored will be described. In this period, since the value of the flag 7 is "1", the control circuit 2 controls the level 1 to store the value of the upper digit of the frequency, and the level 2 controls the value of the lower digit of the frequency. It is controlled to memorize.

First, every time a one-time addition instruction is given until 401 to 410 frequencies are stored, the bit of level 2 is set to "1" one by one from bit b0 as shown in (j). Is done. After all the bits of level 2 have become "1" ((k), 410 frequencies), when a one-time addition instruction is given, the bit b0 of level 2 is set to "0". ((L), 411 counts) Thereafter, each time a one-time count addition instruction is given, the level 2 "1" bit is set to "0" bit by bit.

Next, after all bits except for the bit b9 of level 2 become "0" ((m), 419 counts), when a one-time addition instruction is given, the bit b0 of level 1 becomes "0".
1 (n), and bit b9 of level 2 is set to "0"
((O), frequency 420). by this,
Carry from level 2 to level 1 is performed.

At this time, the bits b0 to b9 of level 2 are
When the one-time addition instruction is given 20 times, it is rewritten once. (In this case, rewriting consists of erasing and writing.) Next, until 421 to 619 frequencies are stored, at level 2, as in the above, all bits are “1”.
Each time a frequency addition instruction is given, one bit is set to “1”, and after all bits become “1”, all bits are set to “1”.
The process of setting the bit of "1" to "0" one bit at a time each time the one-time addition instruction is given is repeated. Is repeatedly set to “0.” At level 1, every time the frequency addition instruction is given 20 times, the bit that is “0” of level 1 is set to “1” one by one.

Next, after all the bits of level 1 become "1" and all the bits except the bit b9 of level 2 become "0" ((p), 619 frequency), a 1 frequency addition instruction is given. As a result, the level 1 bit b0 is set to "0" and the level 2 bit b9 is set to "0". ((Q), 620 frequency) Level 2 until 621-799 frequency is stored next
In the same manner as described above, the bit in which all bits are “0” is 1
Each time a frequency addition instruction is given, one bit is set to “1”, and after all bits become “1”, all bits are set to “1”.
The process of setting the bit of "1" to "0" by one bit each time the one-time addition instruction is given is repeated. Are set to “0” bit by bit.

After all the bits except for the bit b9 of the level 1 and the level 2 become "0" (799 frequency), a 1-time addition instruction is given, and the bit b1 of the level 3 becomes "1". The bit b9 of the level 1 and the level 2 is set to “0”. (800 degrees) Thereby, the carry from level 1 to level 3 is performed.
Level 1 is that if a one-time addition instruction is given 400 times,
All bits are set to "0". Here, the value of the flag 7 is set to “0”.

Thereafter, each time 400 frequencies are added, the value of the flag 7 is inverted, and level 1 and level 2 are controlled so that the lower digit of the frequency is stored alternately.

According to the first embodiment, each time 400 frequencies are added, the state of the flag 7 is inverted, so that level 1 and level 2 are set alternately to store the lower value of the frequency. Therefore, there is no gap between the number of rewrites of level 1 and level 2. Therefore, the life of the entire frequency counting device is extended.

Incidentally, the erasing order and the writing order of the levels 1 to 3 are not limited to the lower bits to the upper bits. Also, the number of configuration bits for levels 1 and 2 is not limited to 10 bits. The number of constituent bits of level 3 is not limited to 5 bits.

The portable module is not limited to a card.

FIG. 4 is a schematic configuration diagram of an IC card showing a second embodiment of the frequency counting device of the present invention. The IC card 30 shown in FIG.
And

The IC card 30 is activated when it is inserted into the card reader 20, and stores the frequency given by the frequency addition command into the previously stored frequency (the frequency addition input to the IC card 20 until then). (The sum of the frequencies given by the instruction), the frequency obtained by the addition is stored in the EEPROM, the operation is stopped when the frequency is removed, and the frequency is stored and held.

The EEPROM 31 is the EEPROM of FIG.
One unit cell area 6 is replaced by a unit cell area 33 having a 10-bit level 1, a level 2 and a 5-bit level 3 and a 1-bit flag 7.

The control circuit 32 responds to the frequency addition command by
The EEPROM 31 executes a frequency storage process. The control circuit 32 checks the value of the flag 7 and controls the level 1 to store the value of the lower digit of the frequency when the flag 7 is “0”, and to control the level 2 when the flag 7 is “1”. Is controlled to store the value of the lower digit of the frequency. The control circuit 32
Each time 0 is added, the value of the flag 7 is inverted. Further, when a frequency addition command is input from the card reader 20, the control circuit 32 sends address data and an erase / write command to the EEPROM 31, and causes the EEPROM to execute a frequency storage process. As a result, the frequency stored in the EEPROM 1 is rewritten. The control circuit 32 may be realized by hardware means, or may be realized by software processing by a microprocessor.

FIG. 5 is a diagram for explaining a frequency count storage process according to the second embodiment of the present invention. First 1
The operation of the frequency counting device during the period until 20 frequencies are stored will be described. In this period, since the value of the flag 7 is “0”, the control circuit 2 controls the level 1 to store the value of the lower digit of the frequency.

Each time the one-time addition instruction is given, the level 1 bit is changed from bit b0 to bit 1 as shown in FIG.
It is set to "1" bit by bit. Thereby, 1 to 10 degrees are stored. After all the bits of level 1 have become "1" ((b), 10 times), a 1-time addition instruction is given, so that level 1 bit b0 is set to "0". ((C), 11 frequency) Next, every time a frequency addition instruction is given, the bit of level 1 "1" is set to "0" bit by bit.

Next, after all bits except for the bit b9 of level 1 become "0" ((d), 19 times), a 1-time addition instruction is given, so that the stored value of level 3 is changed to "1". The binary value stored there until ("0000
It is rewritten to a binary value (“00001”) obtained by adding +1 to “0”).
That is, the level 3 bit b0 is set to "1" and the level 1 bit b9 is set to "0" ((e), 20)
frequency). Here, the value of the flag 7 is set to “1”.

Next, the operation of the frequency counting device in the period until the frequencies 21 to 40 are stored will be described. In this period, since the value of the flag 7 is "1", the control circuit 2 controls the level 2 to store the value of the lower digit of the frequency.

Until the frequency of 21 to 30 is stored, every time the frequency addition instruction is given, the level 2 bit is
As shown in (f), "1" is set bit by bit from bit b0.
Is set to After all the bits of level 2 become “1” ((g), 30 degrees), a 1-time addition instruction is given, so that the bit b0 of level 2 is set to “0”. ((H), 31 frequency) Next, every time a frequency addition instruction is given, the bit of level 2 "1" is set to "0" bit by bit.

Next, after all bits except for the bit b9 of level 2 become "0" ((i), 39 times), a 1-time addition instruction is given, so that the stored value of level 3 is changed to "0". The binary value stored there until ("0000
1 ”) is rewritten to the binary value (“ 00010 ”) which is +1.
That is, bit b0 of level 3 is “0” and bit b1
Is set to "1", and the bit b9 of level 2 is set to "0" ((j), 40 degrees). Here, the value of the flag 7 is set to “0”.

Thereafter, every time 20 degrees are added, the value of the flag 7 is inverted, and level 1 and level 2 are controlled so that the lower digit of the frequency is stored alternately.

According to the second embodiment, the state of the flag 7 is inverted every 20 degrees, so that the level 1
And level 2 are set alternately to store the lower value of the frequency, so that there is no gap between the number of rewrites of level 1 and level 2. Therefore, the life of the entire frequency counting device is extended.

Note that the order of erasing and writing at level 1 is not limited to lower bits to upper bits. Also, the number of configuration bits for levels 1 and 2 is not limited to 10 bits.

The form module is not limited to a card. Further, the control circuit 32 may be provided in a fixed module.

In the first and second embodiments, a value represented by a binary number may be stored in level 1 and level 2.

[0046]

The life of the entire frequency counting device can be extended by reducing the difference in the number of rewrites between the first storage area and the second storage area.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram of a first embodiment of the present invention.

FIG. 2 is an exemplary view for explaining frequency count storage processing according to the first embodiment of the present invention;

FIG. 3 is an exemplary view for explaining frequency count storage processing according to the first embodiment of the present invention;

FIG. 4 is a schematic configuration diagram of a second embodiment of the present invention.

FIG. 5 is a view for explaining frequency count storage processing according to the second embodiment of the present invention;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... EEPROM 2, 32 ... Control circuit 3 ... Y address decoder 4 ... X address decoder 5 ... I / O 6 ... Unit cell area 7 ... Flag 10, 30 ... IC card 20 ... Card reader

Claims (5)

[Claims] Each time an instruction to add a frequency is given,
In a frequency counting device that sequentially adds the frequencies and stores the frequency obtained by the addition, a flag having a first state and a second state and a frequency are stored. First consisting of bits
And a second storage area composed of a plurality of bits, and when the flag is in the first state, the first storage area stores a value of a lower digit of the frequency, and The second storage area stores the value of the upper digit of the frequency, and when the flag is in the second state, the first storage area stores the value of the upper digit of the frequency; A storage area for storing a value of a lower digit of the frequency; and a case where the frequency stored in the storage circuit exceeds a predetermined value or the number of rewrites of the first or second storage area is predetermined. And a control circuit for inverting the state of the flag when the value of the flag is exceeded. 2. The frequency according to claim 1, wherein said storage circuit has a third storage area for storing a value of the most significant digit of said frequency as a value represented by a binary number. Counting device. 3. A frequency counting device for sequentially adding a frequency each time a command for adding a frequency is given and storing a frequency obtained by the addition, wherein a first state and a second state are provided. And a flag having a first storage area, a second storage area, and a third storage area, wherein the third storage area has an upper digit of the frequency. A storage circuit for storing a value, wherein the first or second storage area stores a value of a lower digit of the frequency in accordance with a state of the flag; and the frequency stored in the storage circuit is a predetermined value. And a control circuit for inverting the state of the flag when the number of times of rewriting of the first or second storage area exceeds a predetermined value. 4. The frequency counting device according to claim 1, wherein the storage area for storing the upper digit is a value represented by a binary number. 5. A bit of the first storage area or the second storage area, in which all bits are initial values, is changed to an inverted value one bit at a time every time an instruction to add a frequency is given,
The first storage area or the second storage area in which all bits have inverted values;
4. The frequency counting device according to claim 1, wherein the bits of the storage area are returned to the initial value one bit at a time each time a command for adding one frequency is given.