JPH10207704A - Device for changing program of microcomputer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the program changing device of a microcomputer for reducing the increase of a circuit scale to the minimum, relaxing the limitation of the size of a correction program, and reducing time delay until the execution of the correction program is started to the minimum. SOLUTION: This device is provided with a correction address register 31 and a comparator circuit 32. The values of an ROM fetch address and the correction address register are compared by the comparator circuit 32, and the result is transmitted to an instruction decoder 5. The instruction decoder 5 detects coincidence obtained by the comparator circuit 32, and obtains the start address of a correction program from a prescribed address on an RAM 6 by the execution of a microinstruction. Then, the execution of the program is branched to the start address of the correction program in the same RAM 6.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer program changing apparatus which can correct a program fixedly stored in a ROM built in a microcomputer after a semiconductor integrated circuit is manufactured, and can operate normally. .

[0002]

2. Description of the Related Art Recently, microcomputers are often used in electronic devices in order to cope with higher functions and higher performance. Generally, a program that determines the operation of these microcomputers is a read-only memory (hereinafter referred to as RO).
M). In particular, when used in mass-produced devices such as consumer devices, a mask ROM in which a program is fixedly installed in a semiconductor integrated circuit manufacturing process is often used because of its low unit price. However, since the mask ROM has a fixed program installed in the manufacturing process, it is not possible to modify the program for reasons such as a change in specifications or the detection of a program error after manufacturing. I had to discard it. Further, there is a problem in that the only way to add a modification to the program is to manufacture the microcomputer again, which wastes cost and time.

[0003] In order to solve these problems, some program change devices have been devised, and by incorporating these devices in a microcomputer, it is possible to correct a program in a microcomputer after manufacturing.

FIG. 8 shows a first embodiment of a conventional program changing apparatus. In the figure, 1 is a program counter, 2
Is a ROM in which a program is stored, 31 is a correction address register, 32 is a comparison circuit, 33 is a correction instruction register,
4 is a selection circuit, and 5 is an instruction decoder.

Usually, the microcomputer sequentially reads out the instructions on the ROM 2 pointed to by the program counter 1, decodes them with the instruction decoder 5, and then performs basic operations by executing microinstructions and the like.

In the conventional program changing apparatus, an address at which an instruction requiring correction is stored in the correction address register 31, and the corrected instruction is stored in the correction instruction register. Corrected address register 31 and program counter 1
Are always compared by the comparison circuit 32, and when a match is detected, the selection circuit 4 is switched to the correction instruction register side, and RO
The instruction is corrected by supplying the instruction code stored in the correction instruction register to the instruction decoder, not from M. A program change device 3a including a correction address register 31, a comparison circuit 32, and a correction instruction register 33.
Is required to correct an instruction stored at one address, and usually a plurality of sets of program change devices 3a to 3n are mounted to correct instructions at a plurality of addresses.

FIG. 9 shows a second embodiment of the conventional program changing apparatus. In the figure, 1 is a program counter, 2
Is a ROM for storing a program, 31 is a modified address register, 32 is a comparison circuit, 34 is an interrupt vector register, 5 is an instruction decoder, and 6 is a RAM.

In the conventional program changing apparatus, an address at which an instruction requiring correction is stored in the correction address register 31, a series of correction programs are stored in the RAM 6, and a start address of the correction program is stored in the interrupt vector register 34. I do. The value of the modified address register 31 and the value of the program counter 1 are always compared by the comparing circuit 32, and when a match is detected, an interrupt request signal is generated. When the CPU receives the interrupt request signal, the CPU saves the current program counter value and the like on the stack, reads the address of the interrupt branch destination from the interrupt vector register 34, and sets it in the program counter 1. In this case, the start address of the correction program stored in the RAM is stored in the interrupt vector register, and the correction program is executed as the interrupt processing program.

FIG. 10 shows a third example of the conventional program changing apparatus.
This is an embodiment of the present invention. In the figure, 1 is a program counter,
2 is a ROM for storing a program, 31 is a correction address register, 32 is a comparison circuit, 35 is a branch address register, 4 is a selection circuit, 5 is an instruction decoder, and 36 is a branch instruction generation circuit.

In the conventional program changing apparatus, an address at which an instruction requiring correction is stored in the correction address register 31, a series of correction programs are stored in the RAM 6, and a start address of the correction program is stored in the branch address register 35.
To be stored. The value of the modified address register 31 and the value of the program counter 1 are always compared by the comparison circuit 32. When a match is detected, the selection circuit 4 is switched to the branch instruction generation circuit side, and the branch instruction generated by the branch instruction generation circuit instead of the ROM. Supply the code to the instruction decoder. The branch instruction generating circuit generates an instruction operation code of the branch instruction and a value stored in the branch address register as an operand following the instruction operation code. That is, the CPU decodes and executes the branch instruction to the start address of the correction program, and as a result, executes the correction program.

[0011]

However, the conventional program changing apparatus has the following problems.

In the first conventional example, an instruction that can be corrected by a set of program change devices including a comparison circuit 32, a correction address register 31, and a correction instruction register 33 is an instruction code (for example, 8 bits) corresponding to one address. In a microcomputer, it is only a 1-byte instruction code).
Since the program change device and the correction instruction code have a one-to-one correspondence, it is necessary to implement a plurality of sets of program change devices in order to be able to correct a plurality of instruction codes. Usually, about 8 to 16 sets are mounted in many cases. 16 bits to 24 bits in a general 8-bit microcomputer,
24-bit to 32 for 16-bit microcomputer
It has a bit address line. That is, the comparison circuit and the correction address register of the program change device need to have the same bit width as the address line, and the same number of correction instruction registers (the bit width per set is generally an 8-bit microcomputer). 8 if
Bit, 16 for a 16-bit microcomputer
Bit) is required, and when a plurality of sets are provided, there arises a problem that the circuit scale is increased. On the contrary, there is also a problem that the size of the correction program is limited by the number of sets of the program change device to be mounted.

In the second conventional example, since the correction program is executed by using a general interrupt, the program counter 1 and a program status word PSW (not shown) are saved on a stack. Therefore, it is necessary to secure a stack area for that, and there is a problem that the RAM is wasted. Also, time is required for the operation of saving to the stack, which causes a time loss until execution. This can be fatal for speedy processes. Further, in recent microcomputers, a technique of prefetching an instruction is generally used to increase the processing speed, and a prefetch address for reading a ROM and the execution of an instruction actually executed by a CPU are generally used. It is different from the address. Therefore, the prefetch address and the value of the correction address register 31 are compared by the comparison circuit 32, and if they match, an interrupt is generated, and even if the correction program is executed, the instruction is not correctly corrected. Is generated. This is because, for example, if the instruction being executed is a branch instruction when a match is detected, the instruction specified by the correction address register may not be executed. Therefore, in a microcomputer using the instruction prefetching technique, comparison with an execution address is necessary. However, in general, a register holding an instruction execution address is often not mounted, and the execution of the program is not performed by a program change device. Providing an address register causes a problem of increasing the circuit scale.

In the third conventional example, the correction address register 31 and the program counter 1 are compared by a comparison circuit 32 and a branch instruction is generated when they match, and a branch instruction for generating a specific branch instruction is used. There is a problem that the generation circuit 36 is required and the circuit scale is increased. Further, the following problem occurs.

In recent microcomputers, the basic unit of the bit length of an instruction code may be smaller than the bit width read from a ROM in order to reduce the code size of the instruction. FIG. 7 shows an example of the format of the reduced instruction code. For example, assume that the figure is a 16-bit microcomputer. In a general 16-bit microcomputer, the basic unit of the bit length of the instruction code is 16 bits, and the total bit length of the instruction including the instruction operation code and the operand following thereto is a multiple of 16 bits. In a general 16-bit microcomputer, instructions are read from the ROM with a 16-bit width, so that a boundary between consecutive instructions cannot exist in the middle of the read ROM data. However, in a microcomputer with a reduced instruction code, the instruction operation code has 16 bits (M0) as shown by the instruction n in FIG.
The following operand is 24 bits (M bytes).
2 to M4). In this case, the total bit length of the instruction code is 40 bits (M0 to M0).
M4 (5 bytes), which is not an integral multiple of 16 bits (2 bytes). In such a case, if the reading from the ROM is 16 bits wide, there may be a case where a boundary between consecutive instructions exists in the middle of the read ROM data as shown in FIG. 7B. The same can be said for an 8-bit microcomputer or a 32-bit microcomputer. In the conventional method in which only the instruction fetch address in the ROM is compared and the instruction code is replaced with the code of the branch instruction, it is impossible to generate the branch instruction using the middle of the read data as the instruction boundary. This is because the final code of the instruction immediately before the correction instruction bundled with the branch instruction cannot be uniquely determined.

The present invention solves the above-mentioned problems, (1) minimizes the increase in circuit scale, (2) relaxes the limitation on the size of the correction program, and (3) starts executing the correction program. (4) The address of the corrected part can be directly specified even with a microcomputer using the instruction prefetching technique, and (5) The address of the corrected part can be directly specified even with a microcomputer using the reduced instruction. It is an object of the present invention to provide a microcomputer program change device that can be designated so that the instruction fixedly stored in the ROM can be modified after the microcomputer is manufactured.

[0017]

According to another aspect of the present invention, there is provided a program changing apparatus including a modified address register, a comparing circuit, and a coincidence detecting means. And sends the result to the instruction decoder. When the instruction detector detects a match in the comparison circuit by the match detecting means, the micro-instruction executes to obtain the start address of the correction program from a predetermined address in the RAM. Then, the execution of the program is branched to the start address of the correction program in the RAM. As a result, (1) the increase in the circuit scale is minimized, (2) the restriction on the size of the modification program is relaxed, and (3) the time delay until the execution of the modification program is minimized.
(4) A microcomputer program changing device that can directly specify the address of a correction portion even with a microcomputer using instruction prefetching technology and (5) a microcomputer that can directly specify the address of a correction portion even with a microcomputer using a reduced instruction. can get.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 of the present invention comprises a corrected address register, a comparing circuit, and coincidence detecting means, and compares a ROM fetch address with a value of the corrected address register by a comparing circuit. Is sent to the instruction decoder, and when the match detector detects a match in the comparison circuit, the instruction decoder obtains the start address of the correction program from a predetermined address on the RAM by executing the microinstruction, and executes the program. The program is branched to the start address of the correction program in the RAM, and has the effect of minimizing the circuit scale required to realize the program change device.

According to a second aspect of the present invention, a coincidence signal from a comparison circuit is held until an instruction is decoded. The microcomputer uses an instruction prefetching technique to execute an execution address and read a ROM. Even when the addresses are different, there is an effect that correction can be performed at the time of execution of the corresponding instruction simply by comparing with the ROM read address.

According to a third aspect of the present invention, a plurality of sets of corrected address storage means and comparison circuits are provided.
This has the effect that a program at a plurality of locations can be modified.

According to a fourth aspect of the present invention, a plurality of sets of corrected address storage means and a comparison circuit are provided, and a signal obtained by decoding a coincidence output signal of the comparison circuit is held until an instruction decoding timing. Thus, in addition to the above-described effects of claims 1 to 3, there is an effect that the circuit scale required for holding the coincidence signal can be minimized even when a plurality of correction points are provided.

According to the fifth aspect of the present invention, the coincidence signal is transferred in synchronization with the transfer of the instruction code, and has an effect that the transfer timing of the coincidence signal and the instruction code transfer timing can be shared.

The invention according to claim 6 of the present invention is such that a coincidence signal is directly input to the command decoder, and has an effect that the coincidence can be easily detected.

According to a seventh aspect of the present invention, a specific value is set in an instruction register and a micro address pointer input to the instruction decoder as a coincidence detecting means. Has the effect that the coincidence can be detected without increasing the input signal of.

According to an eighth aspect of the present invention, a decoded value of a coincidence signal is directly used as a part of a RAM address, and a circuit of an address generating circuit as a starting address acquisition means of a correction program is provided. This has the effect that it can be easily realized without increasing the scale.

According to a ninth aspect of the present invention, a coincidence is detected at a timing of decoding an instruction requiring correction. The comparison with the read address has an effect that the corresponding instruction can be corrected.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of the present invention, wherein 1 is a program counter, 2 is a ROM in which a program is stored, 31 is a modified address register, 32 is a comparison circuit, 5 is an instruction decoder, and 6 is an instruction decoder. RAM, 7
Is a coincidence signal. A plurality of sets of the program change device including the correction address register 31 and the comparison circuit 32 are mounted to correct a plurality of instructions (3a to 3n). The program counter 1 and the ROM 2, the comparison circuit 32 and the RAM 6 are connected by an address bus.
And the RAM 6 are connected by a data bus.

The corrected address register 31 has a corrected portion (a defective portion) of a series of instruction codes stored in the ROM 2.
Stores the address of When the corrected portion extends over a plurality of lines, the address where the first instruction code of the corrected portion is stored is stored.

The comparison circuit 32 compares the address value stored in the corrected address register with the address value output from the program counter 1 to the address bus for reading out the instruction code stored in the ROM 2, and the two address values match. Is detected, a match signal 7 is output.

Normally, the microcomputer stores the data addressed by the program counter 1 in the ROM 2.
, The instruction operation code in the read data is decoded by the instruction decoder 5, and various operations are executed by activating the microinstruction. In a general microcomputer, the ROM 2 and the RAM 6 are often arranged in the same memory space, and information necessary for execution of a CPU (not shown) is stored and held in a RAM built in the microcomputer. In many cases, the instruction code on the RAM 6 can be executed by the program counter 1 indicating an address on the RAM 6.

Next, a method of correcting an instruction fixedly stored in the ROM by the present program changing apparatus will be described. (1) When a program fixedly stored in the ROM 2 needs to be modified due to a defect, a change in specification, or the like, the modified instruction code or the address where the first instruction code of a series of modified programs is stored. The value is stored in the correction address register 31. (2) The correction program is stored in the RAM 6. (3) The start address of the correction program stored in the RAM 6 is stored at a predetermined address on the RAM 6.

The above operation is performed by reading necessary data from an external nonvolatile memory or the like at the time of reset start of the microcomputer via a serial interface or a parallel interface generally provided in the microcomputer.

These operations are performed according to the state of data previously stored at a specific address in the external nonvolatile memory on the ROM 2 and the state of the terminals of the microcomputer. What is necessary is just to incorporate the program which is started in.

If the operation of reading the instruction code to be corrected is performed during the operation of the microcomputer having the above setting, the comparison circuit 32 detects the coincidence with the address value stored in the modified address register, and outputs the coincidence signal. Output.

The coincidence signal is input to the instruction decoder 5, and a coincidence is detected by the coincidence signal detecting means provided in the instruction decoder 5 at the timing of decoding the instruction operation code, and the instruction operation code to be decoded is corrected. When the instruction code is detected, a micro instruction that performs the following operation is activated. (1) Obtain the start address value of the correction program from a predetermined address on the RAM 6. (2) Unconditionally branch to the acquired start address value and set the address value in the program counter 1.

Thereafter, the correction program stored in the RAM 6 is read out and executed by sequentially incrementing (or decrementing) the program counter 1.

A series of program corrections is completed by executing a branch instruction to an address on the ROM 2 at the end of the correction program.

Corrected address register 31 and comparison circuit 32
Can modify one program per set. Therefore, by providing a plurality of sets (3a to 3n) of program change devices, it is possible to correct programs at a plurality of locations. Usually, it is sufficient to mount about 2 to 4 sets.

In general, as the number of sets of program change devices increases, the number of coincidence signals also increases, and the circuit scale of the coincidence signal holding means and the coincidence detection means in the instruction decoder increases. Therefore, the following measures are taken to minimize the increase in the circuit scale.

FIG. 2 is a block diagram showing the program change device and the coincidence signal output means according to the present invention. This figure shows a case where the number of program change devices is three (2 ² -1), but the number of sets of program change devices is the maximum (2 ^n).
-1) The same applies to the case of a set.

In FIG. 2A, 3a to 3c are three sets of program change devices, 31a to 31c are modified address registers, 32a to 32c are comparison circuits, 7a to 7c are coincidence signals, 8 is a decoder, 81 and 82 are This is a coincidence decode signal.

The correction address registers 31a and 31b have R
An address on the OM where an instruction code requiring correction is stored is set, and comparison with the instruction fetch address output on the address bus is performed using the comparison circuits 32a to 32c. When the instruction fetch address matches the value of the correction address register, the comparison circuits 32a to 32c output the match signal 7
a to 7c are output. Writing data to the correction address register by executing instructions from the microcomputer,
It goes without saying that reading is possible.

The decoder 8 receives the match signals 7a to 7c and converts them into match decode signals 81 and 82 according to a truth table shown in FIG. Specifically, when none of the comparison circuits output a match signal, the match decode signal (match decode signal 82, match decode signal 81) =
(0, 0), (0, 1) when the comparison circuit 32a is outputting a coincidence signal, and (1, 0) when the comparison circuit 32b is outputting a coincidence signal. Outputs (1, 1) when the output signal is a match signal. In this truth table, it is not assumed that the same correction address is specified in the plurality of correction address registers 31a to 31c due to the nature of the program changing device. However, if necessary, a plurality of coincidence signals 7a and 7b are output simultaneously. In this case, the priority may be set as the coincidence decode signal. For example, it is conceivable to give priority to the coincidence output of a comparison circuit having a smaller number. In this case, when the comparison circuits 32a and 32b output the coincidence signal, the coincidence decode signal of (0, 1) ((coincidence decode signal 82, coincidence decode signal 81)) may be output. The order of priorities is arbitrary. The assignment of decoding can also be arbitrarily configured, but it is preferable that all outputs be the same (all 0s or all 1s) when none of the comparison circuits output a coincidence signal.

By generating the coincidence decode signal as described above, the holding means and the coincidence detecting means in the instruction decoder can be easily configured as described later.

FIG. 3 shows an embodiment of the instruction decoder of the present invention. In the drawing, reference numeral 80 denotes n coincidence decode signals. In the case of the embodiment shown in FIG. 9
Is a PLA, 91 is an AND part constituting the PLA, 92 is an OR part, A0 is an instruction register, A1 is an instruction queue, B0
B1 is a coincidence decode signal holding means for holding a coincidence decode signal at the same timing as the instruction, and D is a control signal for controlling each section of the microcomputer to execute the instruction.

This embodiment shows an instruction decoder in a microcomputer using an instruction prefetching technique. Usually, the instruction code specified and read by the prefetch address is stored in the instruction queue A1 via the data bus. Next, at the instruction decoding timing, the instruction code stored in the instruction queue is transferred to the instruction register. The instruction code stored in the instruction register is input to the AND section 91 of the PLA, decoded, and the control signal D for controlling each section of the microcomputer is output from the OR section 92 of the PLA to execute each instruction.

When the program is changed, the following operation is performed. (1) A desired modified address is compared with a prefetch address by a program changing device as shown in the embodiment of FIG. 2, and a coincidence decode signal 80 obtained by decoding a coincidence signal output in the case of a match is prefetched. The stored instruction code is stored in the coincidence decode signal holding means B1 at the same time as being stored in the instruction queue. (2) Next, the instruction code is transferred to the coincidence decode signal holding means B0 at the same time as the instruction code is transferred to the instruction register, and the coincidence decode signal is held at the same time as the instruction code is input to the AND section 91 of the PLA at the instruction decoding timing. The coincidence decode signal stored in the means B0 is input to the AND section 91 of the PLA. (3) In the PLA, when the coincidence decode signal is input,
(In the embodiment of FIG. 2, (0, 1), (1, 0), (1,
1)) A microprogram that executes the following operation regardless of the type of instruction code is started.

(A) Obtain the start address value of the correction program from a predetermined address on the RAM.

(B) Unconditionally branch to the acquired start address value and set the address value in the program counter. (4) The correction program stored in the RAM is read out and executed by sequentially incrementing (or decrementing) the program counter. (5) A series of program corrections is completed by executing a branch instruction to an address on the ROM at the end of the correction program.

In this embodiment, the coincidence decode signal is held until the instruction decoding timing and input to the AND section of the PLA. However, the undecoded match signal may be held until the instruction decoding timing and directly input.

In this embodiment, n coincidence decode signals are directly inputted to the AND section 91 of the PLA. However, in the decoder of the embodiment of FIG. Since it is 1 ', the configuration can be further simplified by inputting n coincidence decode signals to the OR gate and consolidating them into one signal.

FIG. 4 shows another embodiment of the instruction decoder of the present invention. In the drawing, reference numeral 80 denotes n coincidence decode signals. In the case of the embodiment shown in FIG. 9
Is a PLA, 91 is an AND part constituting the PLA, 92 is an OR part, A0 is an instruction register, A1 is an instruction queue, B0
B1 is a coincidence decode signal holding means for holding a coincidence decode signal at the same timing as the instruction, C is a microaddress pointer, D is a control signal for controlling each part of the microcomputer to execute the instruction, and E is a microaddress control signal. .

In a general microcomputer, a microcode technology is often used for an instruction decoder. In this case, a PLA is used as hardware, and an instruction register value and a micro address pointer value are input to an AND section input of the PLA. The micro address pointer is determined by the micro address control signal according to the previous state. That is, the execution state of each instruction is determined by the instruction register value and the micropointer value.

In this embodiment, the following operation is performed as in the embodiment of FIG. (1) A desired modified address is compared with a prefetch address, and a match decode signal 80 obtained by decoding a match signal output in the case of a match is decoded at the same time when the prefetched instruction code is stored in the instruction queue. It is stored in the signal holding means B1. (2) Next, at the same time when the instruction code is transferred to the instruction register, the instruction code is transferred to the coincidence decode signal holding means B0 to indicate a match ((0, 1), (1, 0) in the embodiment of FIG. 2).
(1, 1)) sets the instruction register and the micro address pointer to specific values, and sets the values to the AND unit 91 of the PLA.
To enter. (3) In the PLA, when the specific value is input, a microprogram for executing the following operation is started.

(A) Obtain the start address value of the correction program from a predetermined address on the RAM.

(B) Unconditionally branch to the acquired start address value and set the address value in the program counter. (4) The correction program stored in the RAM is read out and executed by sequentially incrementing (or decrementing) the program counter. (5) A series of program corrections is completed by executing a branch instruction to an address on the ROM at the end of the correction program.

As a method of setting the instruction register and the micro address pointer to specific addresses, each may be constituted by a register with a set or reset and controlled by a coincidence decode signal, or an AND gate may be connected to each output. Alternatively, an OR gate may be inserted and gated with the coincidence decode signal.

Since the embodiment shown in FIGS. 3 and 4 has means for holding the coincidence decode signal until the decoding timing of the instruction code, the address where the change instruction is stored may be simply compared with the prefetch address. Is normally output to the address bus, it is only necessary to compare the corrected address register with the address bus, so that the configuration of the program changing device can be simplified.

In the above-described embodiment, the configuration of the instruction decoder is PL
Although it is realized by using A, it is needless to say that the configuration can be made by using random logic.

The instruction queue at the time of instruction prefetch is 1
Although the case of stages has been described, the same applies to the case of two or more stages.

In the program change device of the present invention, in the execution cycle of the instruction to be corrected, the microprogram is executed. ・ Acquisition of the start address value of the correction program from a predetermined address on the RAM ・ Unconditional branch to the acquired start address value The operation of setting the address value in the program counter is performed. FIG. 5 shows an embodiment of means for generating an address on the RAM for storing the start address of the correction program at this time.

In the figure, reference numeral 8 denotes a decoder, and B0 and B1 are coincidence decode signal holding means for holding a coincidence decode signal at the same timing as the instruction, which is the same as a part of the embodiment shown in FIGS.

FIG. 6 shows the RAM space for storing the start address of the correction program and the bit configuration of the address signal.

In FIG. 6A, F0 to F2 are the start address storage areas of the correction programs corresponding to the three sets of program change devices.

[0065] 2 ¹⁶ bytes of RAM address space for storing a correction program for simplification in the present embodiment (the address signal lines 16 bits), and the program changing device is three pairs as shown in FIG. 2 However, the number of sets of the address signal lines and the program change devices can be similarly considered in any case.

Since the address signal lines in the RAM space are 16 bits, as shown in FIG. 6A, three sets of 16-bit (2 bytes) areas for storing the start address of the correction program are secured. In this embodiment, the region F0 (X'0202 'and X'
(0203 ') at the program change device 3 in FIG.
a. The correction program start address of the
(Addresses X'0204 'and X'0205'), the modified program start address of the program modifying device 3b is stored in the area F
2 (addresses X'0206 'and X'0207') stores the correction program start address of the program change device 3c.

A general 16-bit microcomputer can access the RAM space in 16-bit units. In this case, in order to obtain the start address of the correction program, the data of the address X'202 ', the address X'204', or the address X'0206 'is simply read according to any of the program changers 3a to 3c which output the coincidence signal. What is necessary is just to read in 16-bit units. As shown in FIG. 6B, the upper 15 bits (bit 3 to bit 15) of the 16-bit address signal line are assigned a fixed value b'00000000100000 'to the next two bits (bit 1 to bit 1). 2) may output a coincidence decode signal according to the decoder of FIG. 2B, and the last bit (bit 0) may output a fixed value b'0 '. As shown in FIG. 5, the coincidence decode signal only needs to output the data stored in the coincidence decode signal holding means B0 to the address bus at the start address acquisition timing of the correction program, and the circuit can be easily formed.

When only 8-bit data can be accessed at a time like an 8-bit microcomputer,
It is sufficient to acquire the 8-bit data twice, and the least significant bit (bit 0) in FIG. 6B is not a fixed value but b'0 'in the first address acquisition and b' in the second address acquisition.
This can be solved by outputting 1 '.

In this embodiment, the coincidence decode signal is output in two bits of bit 1 and bit 2. However, the configuration of the correction program start address storage area, the address bit width of the RAM space, and the data that can be handled by the microcomputer Bit width (4 bits, 8 bits, 16 bits,
32 bits, 64 bits, etc.).

Also, according to the decoder configuration of FIG. 2B, when the coincidence decode signal is b'00 ', it is assigned when no program change device outputs the coincidence signal.
Although the addresses X'0200 'to X'0201' are not used, it goes without saying that if the configuration of the decoder changes, the address of the correction program start address storage area to be allocated also changes.

FIG. 7 shows the format of the reduced instruction code. For example, assume that the figure is a 16-bit microcomputer. The basic unit of the reduced instruction code in this case is 8
Instruction n has an instruction operation code of 1
6 bits (2 bytes M0 to M1), 24 operands
Bits (M3 to M4 bytes). The subsequent instruction n + 1 has the same instruction operation code of 16
Assume that bits (2 bytes of N0 to N1) and the operand are 16 bits (2 bytes of N2 to N3). In this case, assuming that the instruction n is stored from the address X'0100 'as shown in FIG. 7B, the final code M4 of the instruction n is stored at the address X'0104' and the instruction n is stored at the address X'0105 '. n
The first code N0 of +1 is stored. In a general 16-bit microcomputer, instructions are fetched in 16-bit units, so that addresses X'0104 'and X'0
Address 105 'is fetched simultaneously as data at address X'0104'.

For example, if the instruction to be modified is instruction n + 1, X'0104 'is stored in the modified address register. Therefore, when the boundary of the instruction is not on the boundary of the instruction fetch unit, the address of the fetch data including the head of the instruction to be corrected is specified in the correction address register.

In the above-described example, the case of a 16-bit microcomputer is used. However, even though it is an 8-bit microcomputer like the 8-bit microcomputer MN101 series manufactured by Matsushita Electronics, the basic unit of the instruction code format is 4 units. There is also a bit microcomputer. The same applies to microcomputers of 32 bits or 64 bits or more.

As shown in the example of FIG.
Then, when the correction address register value is X'0104 ',
The last code M4 of the instruction n and the leading code N0 of the instruction n + 1 are stored in the instruction queue A1 shown in FIG.
The coincidence decode signal is stored in the coincidence decode holding means B1. The microcomputer using the reduced instruction code has means for extracting and storing only the instruction operation code of the instruction when storing the instruction operation code from the instruction queue in the instruction register in the instruction decoder. Zu).

Therefore, it is sufficient to extract only the instruction operation code from the instruction queue A1 and transfer the coincidence decode signal from the coincidence decode signal holding means B1 to B0 at the timing of storing the instruction operation code in the instruction register A0. And (1) obtaining the start address value of the correction program from a predetermined address on the RAM (2) unconditionally branching to the obtained start address value and setting the address value in the program counter. The operation is performed, and the program can be similarly changed.

Therefore, according to the present invention, the instruction can be modified in the execution cycle of the instruction to be modified regardless of the format of the instruction code.

[0077]

As described above, according to the present invention, the start address of the correction program stored in the RAM is stored at a predetermined address in the RAM, and the address of the desired correction location is stored. A comparing circuit for comparing a fetch address of an instruction with an address stored in the corrected address storing means, and outputting a coincidence signal when they match, and a circuit for decoding coincidence outputs of the plurality of comparing circuits; The instruction decoder of the CPU further comprises means for detecting that the comparison circuit has output a coincidence signal, and upon detecting the coincidence signal, the instruction decoder interprets a predetermined instruction of the RAM by executing a microinstruction. A configuration is provided that obtains the start address of the correction program from the address and branches the execution of the program to the start address of the correction program in the RAM. (1) Minimizing the increase in the circuit scale, (2) relaxing the restriction on the size of the correction program, (3) minimizing the time delay before starting the execution of the correction program, 4) An excellent microcomputer program changing device that can directly specify the address of a correction portion even with a microcomputer using instruction prefetching technology, and (5) can directly specify the address of a correction portion even with a microcomputer using a reduced instruction. Can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an entire embodiment.

FIG. 2 is a diagram showing an embodiment of a program change device and a coincidence signal output means;

FIG. 3 is a diagram showing a first embodiment of an instruction decoder;

FIG. 4 is a diagram showing a second embodiment of the instruction decoder;

FIG. 5 is a diagram showing an address generation unit.

FIG. 6 is a diagram showing a correction program start address storage area;

FIG. 7 shows an example of a reduced instruction code.

FIG. 8 is a diagram showing a first conventional example.

FIG. 9 is a diagram showing a second conventional example.

FIG. 10 is a diagram showing a third conventional example.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Program counter 2 ROM 3, 3a-3n Program change device 31 Correction address register 32 Comparison circuit 33 Correction instruction register 34 Interrupt vector register 35 Branch address register 36 Branch instruction generation circuit 4 Selection circuit 5 Instruction decoder 6 RAM 7, 7a , 7b Match signal 8 Decoder 81, 82 Match decode signal 9 PLA 91 AND section of PLA 92 OR section of PLA A0 Instruction register A1 Instruction queue B0, B1 Match decode signal holding means C Micro address pointer D Control signal E Micro address control signal F0, F1, F2 Correction program start address storage area

Claims (9)

[Claims] 1. A microcomputer in which a read-only memory (ROM), a random access memory (RAM), and a central processing unit (CPU) for performing arithmetic and control are integrated in the same chip, and are modified into instructions stored in the ROM. A program changing device of a microcomputer for branching the execution from a corrected portion to a corrected program stored in the RAM when a portion is generated, the corrected program being stored in the RAM, and the start address being the same. Correction address storage means for storing the address of a desired correction location of the ROM, stored at a predetermined predetermined address in the RAM; read address to the ROM for fetching an instruction; Compares the address stored in the address storage means and outputs a match signal when they match. An instruction decoder of the CPU comprises means for detecting that the comparison circuit has output a coincidence signal, and upon detecting the coincidence signal, the instruction decoder interprets the predetermined instruction of the RAM by executing a microinstruction. A program change device for a microcomputer, which obtains a start address of a correction program from the address of the microcomputer and branches execution of the program to a start address of the correction program in the RAM. 2. When the corrected address storage means and the fetch address of the instruction match, the instruction code read from the ROM and the coincidence signal of the comparison circuit are simultaneously input to the CPU, and the CPU transmits the instruction code and the coincidence signal to the CPU. A means for holding the instruction code until the decoding timing is provided, and when decoding the instruction code, the instruction decoder of the CPU includes means for detecting that the instruction code is an instruction code to be corrected based on the input coincidence signal. 2. The microcomputer according to claim 1, wherein: 3. The microcomputer according to claim 1, wherein a plurality of sets of corrected address storage means and comparison circuits are provided. 4. A microcomputer in which a read-only memory (ROM), a random access memory (RAM), and a central processing unit (CPU) for performing calculations and controls are integrated in the same chip, and modified into instructions stored in the ROM. A program changing device of a microcomputer for branching the execution from a corrected portion to a corrected program stored in the RAM when a portion is generated, the corrected program being stored in the RAM, and the start address being the same. Correction address storage means for storing at a predetermined predetermined address in the RAM, storing an address of a desired correction location of the ROM, an instruction fetch address,
A maximum of 2 ⁿ -1 sets of comparison circuits for comparing the addresses stored in the corrected address storage means and outputting a coincidence signal when they match (n is a natural number), and the maximum is 2 ⁿ -1 From the coincidence output of each of the comparators, the decoder circuit generates n coincidence decode signals indicating which of the comparator circuits coincides with each other. Among the states of the coincidence decode signals, a set of specific states (all signals are 0) Or 1) all the comparison circuits are in a mismatched state, the coincidence decode signal is input to the CPU simultaneously with the instruction code, and the CPU is provided with means for holding the instruction code and the coincidence decode signal until decoding timing of the instruction code. When decoding the instruction code, the instruction decoder of the CPU detects from the input coincidence signal that the instruction code is an instruction code to be corrected, Wherein the RAM start address of the positive program is stored
Means for generating a predetermined address in the RAM, upon detecting that the correction is necessary, the instruction decoder decodes the correction program from the predetermined address of the RAM generated by the address generation means by executing the microinstruction. Get start address and execute program
A program changing device for a microcomputer, wherein a branch is made to a start address of a correction program in M. 5. An instruction register for storing an instruction code to be decoded and at least one stage of prefetch as means for holding the instruction code and the coincidence decode signal according to claim 4 until decoding timing of the instruction code. A program change device for a microcomputer, comprising: an instruction queue for storing an instruction code, wherein a coincidence decode signal is transferred in synchronization with the instruction code on temporary storage means having the same number of stages as the instruction code. 6. A coincidence decode signal is input to an instruction decoder simultaneously with an instruction code as a means for detecting that the instruction code is an instruction code to be corrected according to claim 4. When the coincidence decode signal indicating that the correction code is input, the start address of the correction program is obtained from a predetermined address of the RAM irrespective of the instruction code, and the execution of the program is branched to the start address of the correction program in the RAM. A microcomputer program changing device for executing instructions. 7. A microcomputer for inputting at least an output of an instruction register and an output of a microaddress pointer to an instruction decoder of a CPU, wherein said means detects the instruction code to be corrected according to claim 4. When a coincidence decode signal indicating that the instruction code is an instruction code to be corrected when storing the instruction code in the instruction register is input, a specific value is set in the instruction register and the micro address pointer, and the instruction decoder reads the specific value. A microcomputer which obtains a start address of the correction program from a predetermined address in the RAM, and executes a microinstruction for branching the execution of the program to the start address of the correction program in the RAM. Program change device. 8. A means for generating a predetermined address in the RAM in which a start address of the correction program according to claim 4 is stored, the method comprising the steps of: A program change device for a microcomputer characterized by outputting to a microcomputer. 9. The tone of an instruction code composed of an instruction operation code and an operand following the instruction operation code is 1 / n of the bit width of data to be fetched at a time (n = 2 or 4).
Where the boundary of consecutive instruction codes may be at the intermediate position of the data to be fetched at the same time, and the head of the instruction operation code of the instruction that needs to be modified exists in the modified address storage means. And a coincidence decode signal indicating that the instruction fetch address coincides with the corrected address storage means, at the same time as the fetch data at the beginning of the instruction operation code.
U, the CPU comprises means for holding a coincidence decode signal until the timing of decoding the instruction code requiring correction, and the CPU reads C when decoding the instruction operation code extracted from the fetch data including the head of the instruction code requiring correction.
The instruction decoder of the PU has means for detecting that the instruction code is an instruction code to be corrected based on the input coincidence signal, and when the instruction decoder detects that the instruction code needs to be corrected, the instruction decoder executes the micro instruction. A program change device for a microcomputer, wherein a start address of a correction program is obtained from a predetermined address in the RAM, and execution of the program is branched to a start address of the correction program in the RAM.