JPH10200514A - Transmission quality supervisory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To supervise a transmission quality, even for transmission line that has a low transmission quality with high accuracy by discriminating whether or not a bit error on plural bits occurs in every small set, in addition to a BIP system that discriminates whether or not a bit error occurs in a signal bit in each small set. SOLUTION: A discriminating means 11 discriminates the existence of a bit error based on a BIP system about N sets, that are decided in the order or time sequence and consist of plural bits among bits which are separately included in a fetched frame. On the other hand, and error-detecting means 12 decodes a specific field and calculates a bit string that shows whether or not a bit error occurs to a bit unit. Error bit number detecting means 13-1 to 13-N divide calculated bit strings into N small sets, and discriminates whether or not the number of bits that have bit errors is plural. A supervisory result outputting means 14 multiplexes the result of the discrimination and the logical OR of a discrimination result of the means 13-1 to 13-N and outputs it.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transmission quality monitoring apparatus for monitoring the transmission quality of each transmission section in an in-service state in a transmission system, and outputting the result of the monitoring as information for maintenance and operation. About.

[0002]

2. Description of the Related Art In recent years, transmission lines constituting a trunk system of a communication network have been required to flexibly adapt to an increase in the amount of information and a variety of transmission information while adapting to multimedia communication and other forms of communication. Therefore, high transmission quality is being demanded. However, for such a transmission line, most of the bit errors that occur are caused by problems that the transmission device or the transmission line have in an actual operation state and events that occur suddenly such as disturbances and failures. As the transmission capacity is larger, it is more difficult to secure an alternative transmission path, and occupation of the transmission path for measurement of transmission quality is not allowed.

[0003] Therefore, the transmission quality of the above-mentioned transmission path is determined by a parity check and a CRC (Cyclic Redundancy) in a transmission apparatus connected to both ends or one end of the transmission path.
dancyCheck) and BIP (Bit Interleaved Parity) are monitored as the bit error rate in the in-service state. FIG. 12 is a diagram (1) illustrating a conventional example of a transmission device that monitors transmission quality.

In the figure, one end of a transmission line is connected to the inputs of the bit error correction circuit 111 and the BIP operation unit 112, and a first output of the BIP operation unit 112 is supplied via a quality deterioration detection unit 113 to an operation (not shown). It is connected to a communication link formed with the center. In addition,
Output of bit error correction circuit 111 and BIP operation unit 1
12, the bit error correction circuit 111, the BIP operation unit 112, and the quality deterioration detection unit 1
13 is connected to a circuit (not shown) of the subsequent stage which constitutes the transmission device including.

[0005] In the conventional example having such a configuration, the transmitting end opposed via the above-described transmission path has, as shown in FIG.
Parity bits P1 to P4 (here, for simplicity, included in each set, for each of the four sets of n bits arranged in a time-sequential manner and separated by 4 bits each as a serial bit string constituting transmission information) It is assumed that the number of bits whose logical value is "1" among the bits to be set is an even number.) And is transmitted to the transmission line.

[0006] On the other hand, the BIP operation unit 112 opposed via such a transmission path fetches a bit string received in series via the transmission path, and sets the parity bits for the above four sets included in the bit string. Are determined in parallel, and the result is obtained. The quality deterioration detection unit 113 notifies the operation system of the result obtained by the BIP calculation unit 112 via the communication link. Also, the bit error correction circuit 111
In the same manner, by taking in a bit string received via the transmission path and performing decoding processing on an error correction coded field at the transmitting end among the bits included in the bit string, the information of the field is obtained. Restore.

Further, the bit error correction circuit 111 and the BI
The circuit arranged downstream of the P operation unit 112 performs predetermined processing on the information restored as described above and the result obtained by the BIP operation unit 112, and gives the processed information to an exchange (not shown) or Relay to the transmission path to be performed. Further, for example, when the bit error rate increases due to deterioration of the characteristics of circuit elements such as ICs constituting the transmitting end and the receiving end due to aging and other factors, the BI
Since such a state is detected based on the result obtained by the P operation unit 112, maintenance and recovery can be performed.

FIG. 14 is a diagram (2) showing a conventional example of a transmission apparatus for monitoring transmission quality. The difference between the conventional example shown in FIG. 14 and the conventional example shown in FIG.
The error bit number measuring unit 121 is provided in place of the quality deterioration detecting unit 113, and the input of the error bit number measuring unit 121 is replaced with a bit error correction circuit 111- instead of the output of the BIP operation unit 112. It is connected to error bit notification outputs 1 to 111-N.

In the conventional example having such a configuration, the bit error correction circuits 111-1 to 111-N perform a decoding process in the same manner as the conventional example shown in FIG. Information (hereinafter, referred to as “error bit information”) indicating a position of a bit in which an error has occurred in a codeword unit is sequentially output. The error bit number measuring unit 121 determines whether or not a bit error has occurred by referring to the error bit information, and notifies the operation center via a communication link of a result of the determination.

The difference between the conventional example shown in FIG. 12 and FIG. 14 is that the former has extremely high transmission quality on the transmission line, so that bit errors extend over a plurality of bits per word length of the error correction code. The latter is applied when the possibility of occurrence is small, but the latter is applied when the transmission quality is lower than such a transmission path and a similar bit error may occur over a plurality of bits. Does not apply.

[0011]

By the way, among the above-mentioned conventional examples, the one shown in FIG. 12 is to be applied to a transmission line having originally high transmission quality as described above. Even if the bit error increases for some reason, if the bit error occurs for an even number of bits, such a bit error is not detected.

In the conventional example shown in FIG. 14, when a bit error occurs in a plurality of bits, the bit error is detected with high accuracy. However, for example, in recent years, FTTH (Fiber To The Hom
For the subscriber line to be applied to e) (hereinafter simply referred to as "optical subscriber line"), since the optical fiber replaces the subscriber line formed by the current metallic cable, In general, the transmission speed is lower than that of the trunk transmission line, but it is strictly required that the reduction in maintenance and operation efficiency be kept within an allowable range and that the cost can be reduced.

In other words, these two conventional examples are adapted to transmission lines having different maintenance and operation systems, but the efficiency and cost of maintenance and operation are reduced, and appropriate reliability is maintained. F to be achieved by realizing
It was not always adapted to TTH. SUMMARY OF THE INVENTION An object of the present invention is to provide a transmission quality monitoring device capable of accurately monitoring the transmission quality of a transmission path having a low transmission quality while standardizing the technology.

[0014]

FIG. 1 is a block diagram showing the principle of the first and second aspects of the present invention. According to the first aspect of the present invention, a plurality of frames in which a specific field is subjected to error correction coding are fetched from a transmission path, and a predetermined number of bits individually included in these frames in a time series order. A determination means 11 for determining the presence or absence of a bit error based on the BIP method for N sets of a plurality of unique bits separated by N bits, and a specific field conforming to the error correction decoding method. Error bit detecting means 12 for obtaining a bit string indicating whether or not a bit error has occurred as a result in bit units, and the bit strings obtained by the error bit detecting means 12 individually belonging to N sets. It is divided into N sub-sets of bits, and bit errors occur in these sub-sets based on the logical values of the individually included bits. And error bit number determination unit 13-1 to 13-N the number of bits to perform whether a plurality determination, result of the determination made by determination unit 11, the number of error bits determination unit 13-1
13-N, and a monitoring result output means 14 for multiplexing and outputting a logical sum of the results of the determinations made by 13-N.

According to a second aspect of the present invention, in the transmission quality monitoring apparatus according to the first aspect, a specific field is error-correction-coded based on a single error-correction coding method, and an error bit detecting means is provided. No. 12 is characterized in that a bit string is obtained by performing decoding on a frame basis based on a single error correction coding scheme. FIG.
3 is a principle block diagram of the invention described in FIG.

According to a third aspect of the present invention, a plurality of frames in which a plurality of specific fields are error-correction coded are fetched from a transmission line, and the bits individually included in these frames are chronologically ordered. Determining means 20 for determining whether or not there is a bit error based on the BIP method for N sets of a plurality of unique bits separated by a predetermined number N of bits, and an individual set included in a plurality of frames Error bit detection means 21 for performing decoding in conformity with the error correction decoding method on a specific field, and obtaining a bit sequence indicating whether or not a bit error has occurred as a result in bit units in a time-series order; A bit sequence obtained by the detection means 21 is stored in the order of time series, and is updated at a cycle of a multi-frame including a plurality of frames. The bit strings held by the holding units 22-1 to 22-n and the holding units 22-1 to 22-n are divided into N small sets each including bits individually belonging to N sets. Error bit number determination means 23 for determining whether or not the number of bits in which a bit error has occurred is plural based on the logical value of bits individually included in the set
A monitor that multiplexes and outputs a result of the determination performed by the determination unit 11 and a logical sum of the results of the determination performed by the error bit number determination units 23-1 to 23-N. And a result output unit 24.

FIG. 3 is a block diagram showing the principle of the present invention. According to a fourth aspect of the present invention, a plurality of frames in which a specific field is subjected to error correction coding are fetched from a transmission path, and a predetermined number of bits individually included in these frames are determined in a time series order. A determination unit 11 for determining whether there is a bit error based on the BIP method for N sets of a plurality of unique bits separated by N bits, and a plurality of frames in a specific field under a frame configuration. A division processing unit 31 having a word length equal to or longer than the word length and dividing the field into a plurality of words included without being divided to generate a bit string to be decoded, and a decoding unit generated by the division processing unit 31 Performs decoding that conforms to the error-correction decoding method for the coded bit sequence, and generates a time-series bit sequence that indicates whether or not a bit error has occurred as a result. The error bit detecting means 32, which is determined in order, and the bit string obtained by the error bit detecting means 32 are fetched, and a bit error occurs in the bit string corresponding to a word that does not include a field under the frame configuration. Bit processing means 33 for generating a bit string to be determined by substituting a value indicating a non-existent bit; and N small bits consisting of bits individually belonging to N sets of the bit string to be determined generated by the bit processing means 33. Error bit number discriminating means 34-1 to 3-4 for deciding whether or not the number of bits in which a bit error has occurred is plural based on the logical value of bits individually included in these small sets. 34-N, the logical sum of the result of the determination made by the determination means 11 and the result of the determination made by the error bit number determination means 34-1 to 34-N And a monitoring result output means 35 for multiplexing and outputting the result.

According to a fifth aspect of the present invention, in the transmission quality monitoring apparatus according to the fourth aspect, the specific field comprises a plurality of fields to which different error correction coding systems are individually applied. 31 is characterized in that a plurality of frames are divided into a plurality of words having a word length longer than the maximum word length of a plurality of fields under a frame structure and including these fields without being divided. .

In the transmission quality monitoring apparatus according to the first aspect of the present invention, the determination means 11 takes in a plurality of frames in which specific fields are error-correction coded from a transmission line and individually includes these frames. Among N bits, a set of N bits composed of a plurality of unique bits separated by a predetermined number N of bits in a time series order is used to determine whether there is a bit error based on the BIP method.

On the other hand, the error bit detecting means 12 obtains a bit string indicating whether or not a bit error has occurred as a result by decoding the specific field described above. Error bit number determining means 1
3-1 to 13-N divide the bit string obtained by the error bit detecting means 12 into N small sets each consisting of bits individually belonging to the above-mentioned N sets, and individually divide these bit sets. It is determined whether or not the number of bits in which a bit error has occurred is plural based on the logical value of the included bits. The monitoring result output unit 14 multiplexes and outputs the result of the determination and the logical sum of the results of the determination performed by the error bit number determining units 13-1 to 13-N as described above.

That is, in addition to the above-described BIP method, which is often applied to a trunk transmission path and determines whether a bit error has occurred in a single bit for each small set, the bit Since the result of the determination indicating whether or not an error has occurred for a plurality of bits is reliably provided for maintenance and operation, the transmission quality is also applied to a transmission path whose value is lower than such a main transmission path. It is monitored with high accuracy while standardizing technology.

According to a second aspect of the present invention, there is provided a transmission quality monitoring apparatus according to the first aspect, wherein a specific field is subjected to error correction based on a single error correction coding system. The coded error bit detection means 12 obtains a bit string by performing decoding on a frame basis based on the single error correction coding method.

That is, when the difference between the probability of occurrence of a bit error in the specific field and the other field is small enough to be acceptable, the above-mentioned operation is performed without complicated synchronization control or timing adjustment. , A plurality of bit errors are detected with high accuracy for each small set. Claim 3
In the transmission quality monitoring apparatus according to the invention described in (1), the determining means 20 takes in a plurality of frames in which a plurality of specific fields are error-correction-coded from a transmission path, and sets a bit among bits individually included in these frames. The presence / absence of a bit error is determined based on the BIP method for N sets of a plurality of unique bits separated by a predetermined number N of bits in the order of time series.

On the other hand, the error bit detection means 21 performs decoding suitable for the error correction decoding method for each specific field included in the plurality of frames described above, and determines whether or not a bit error has occurred as a result. Is obtained in bit order in bit sequence. Holding means 2
2-1 to 22-n hold the bit strings obtained by the error bit detecting means 21 in chronological order, and update the bit strings at a cycle of a multi-frame including a plurality of frames.

The error bit number determining means 23-1 to 23-N are:
The bit string held in this way is divided into N small sets of bits individually belonging to the N sets, and bit errors occur in these small sets based on the logical values of the individually included bits. It is determined whether or not the number of bits obtained is plural. The monitoring result output unit 24 multiplexes the result of the determination performed by the determination unit 20 and the logical sum of the results of the determination performed by the error bit number determination units 23-1 to 23-N as described above. Output.

That is, even if different error correction decoding schemes are applied to a plurality of specific fields, respectively, it is often applied to a trunk transmission path and a bit error occurs in a single bit. In addition to the above-described BIP method in which the determination is made for each of the small sets, the result of the determination indicating whether or not a bit error has occurred for a plurality of bits for each of the small sets is reliably provided for maintenance and operation. Therefore, regarding the transmission quality, the value of a transmission line whose value is lower than that of the main line transmission line is measured while standardizing applied technology.
The monitoring is more accurately performed than the transmission quality monitoring device according to the invention described in (2).

In the transmission quality monitoring apparatus according to a fourth aspect of the present invention, the determination means 11 takes in a plurality of frames in which specific fields are subjected to error correction coding from a transmission line and individually includes these frames. Among N bits, a set of N bits composed of a plurality of unique bits separated by a predetermined number N of bits in a time series order is used to determine whether there is a bit error based on the BIP method.

On the other hand, the division processing means 31 divides a plurality of frames into a plurality of words having a word length longer than the word length of the specific field described above and including the field without being divided. Generate a decoded bit string. The error bit detection means 32 performs decoding on the bit string to be decoded generated in this manner in conformity with the above-described error correction decoding method, and determines whether or not a bit error has occurred as a result in bit units. Are obtained in chronological order.

The bit processing means 33 generates a bit string to be determined by replacing a logical value corresponding to a word that does not include a field among these bit strings with a value indicating a bit in which no bit error occurs. The error bit number discriminating means 34-1 to 34-N divide the bit string to be determined generated by the bit processing means 33 into N small sets of bits individually corresponding to the N sets described above, For these small sets, it is determined whether or not the number of bits in which a bit error has occurred is plural based on the logical values of the bits individually included.

The monitoring result output means 35 outputs the result of the determination made by the determination means 11 and the error bit number determination means 3
The result is multiplexed with the logical sum of the results of the determinations made by 4-1 to 34-N and output. That is, under the coordination of the division processing means 31 and the bit processing means 33, the bits to be determined as to whether or not a bit error has occurred in a plurality of bits and the other bits are collectively distinguished. Accordingly, even in the case of a transmission path whose transmission quality is lower than the transmission path of the main system in the same manner as in the transmission quality monitoring apparatus according to the first to third aspects of the present invention, the transmission quality is accurate while standardizing the applied technology. Monitored high.

In the transmission quality monitoring apparatus according to the fifth aspect of the present invention, the specific field includes a plurality of fields to which different error correction coding systems are applied. Further, the division processing unit 31 divides the plurality of frames into a plurality of words having a word length longer than the maximum word length of the plurality of fields and including these fields without being divided. That is, even when different error correction coding schemes are applied to a plurality of specific fields, the division processing means 31 and the bit processing means 33 are provided in the same manner as in the transmission quality monitoring apparatus according to the invention according to claim 4. In cooperation with
A bit to be determined whether or not a bit error has occurred in a plurality of bits and the other bits are collectively distinguished, and the transmission quality of the transmission path is lower than that of the main path. Quality is monitored with high accuracy while standardizing applied technologies.

[0032]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG.
FIG. 3 is a diagram showing an embodiment corresponding to the invention described in FIG. In the figure, components having the same functions and configurations as those shown in FIG. 12 are denoted by the same reference numerals, and description thereof is omitted here.

In this embodiment, the baseband signal indicating the transmission information is transmitted to the error correction decoding circuit 61 and the BIP operation unit 1
12 among the 32 outputs of the error correction decoding circuit 61, the integer i (= 1 to 8) and the i-th
Th, (8 + i) th, (16 + i) th and (24 + i) th
The i combinations of the output combinations are
Each is connected to the corresponding input of the counting units 62-1 to 62-8. Outputs of the counting units 62-1 to 62-8 are connected to corresponding inputs of the OR gate 63, respectively.
Is connected to the set input of flip-flop 64. The output of the timing generator 65 is connected to the reset input of the flip-flop 64, and the output of the flip-flop 64 is connected to the first input of the quality deterioration detector 113. A first output of the BIP operation unit 112 is connected to a second input of the quality deterioration detection unit 113, and an output of the quality deterioration detection unit 113 is connected to an operation center (not shown) via a communication link.

In the counting section 62-1, the first input is the first negative logic input of the AND gate 66-11, and the AND gate 66-2.
1 positive logic input and AND gates 66-31, 66-41,
A second input is connected to a first negative logic input of an AND gate 66-11, a first negative logic input of an AND gate 66-21, and an AND gate 66-31.
And the second negative logic inputs of AND gates 66-41 and 66-51. The third input is the third negative logic input of the AND gate 66-11, and the AND gate 66-2.
1, 66-31 second negative logic input, AND gate 66-41
The fourth input is connected to a positive logic input of the AND gate 66-51 and a third negative logic input of the AND gate 66-51.
, A third negative logic input of AND gates 66-21 to 66-41 and a positive logic input of AND gate 66-51. Outputs of the AND gates 66-11 to 66-51 are connected to corresponding inputs of the NOR gate 67, and outputs thereof are connected to corresponding inputs of the OR gate 63.

The configuration of the counting units 62-2 to 62-8 is the same as the configuration of the counting unit 62-1. Therefore, the suffixes of the corresponding components are "2" to "8". The same reference numerals are given and the description is omitted here. Also, regarding the correspondence between the present embodiment and the block diagram shown in FIG. 1, the BIP operation unit 112 corresponds to the determination unit 11, the error correction decoding circuit 61 corresponds to the error bit detection unit 12, and the counting unit 62- 1 to 62-8 correspond to the error bit number determining means 13-1 to 13-N, and the OR gate 63, the flip-flop 64, the timing generator 65, and the quality deterioration detector 113 correspond to the monitoring result output means 14.

FIG. 5 is an operation timing chart of the embodiment according to the first and second aspects of the present invention. FIG.
FIG. 3 is a diagram for explaining the operation of the embodiment corresponding to the first and second aspects of the present invention. Hereinafter, the operation of the present embodiment will be described with reference to FIGS.

As shown in FIG. 5, the error correction decoding circuit 61 is supplied with a baseband signal indicating a column of a frame in which only a specific field has been subjected to error correction coding, and performs synchronization under a synchronization control unit (not shown). And decodes the contents of the field, and a word (here, for simplicity, it is assumed to be 32 bits long) indicating whether a bit error has occurred for each bit constituting such a field. Output.

The counting units 62-1 to 62-8 are provided by the BIP operation unit 1
Taking these words for each of the eight groups (FIGS. 6-) corresponding to the objects of the BIP operation performed by
In addition, by performing the logical operation in parallel, the logical value of 2 bits or more out of the 4 bits included in each group is “1”.
(Indicating the position of the bit in which the bit error occurred). "

On the other hand, the timing generator 65 outputs a pulse every time a field to be decoded by the error correction decoding circuit 61 is given to the error correction decoding circuit 61 under the above-described synchronization in the order of time series (FIG. 5). The OR gate 63 calculates the logical sum of the results of the above-described determination performed by the counting units 62-1 to 62-8, and indicates the logical sum of 2 or 2.
The value information is given to the quality deterioration detecting unit 113 via the flip-flop 64 reset in response to the above-mentioned pulse (FIG. 5).

The timing generation section 65 includes the BIP operation section 1
12 is the result of the BIP operation performed in the same manner as in the conventional example, and 2 is given via the flip-flop 64 as described above.
The value information is multiplexed and transmitted to the operation center. As described above, according to the present embodiment, it is reliably monitored whether or not a bit error has occurred in a plurality of bits (FIGS. 6A and 6B) in an error-correction-coded field. Since the result of the monitoring together with the result of the BIP operation performed by the BIP operation unit 112 is reliably notified to the operation center, the BIP operation is applied in the same manner as in the case of the trunk transmission line, and the BIP operation detects The presence / absence of a plurality of unsuccessful bit errors is reliably transmitted to maintenance and operation personnel.

Therefore, for monitoring the transmission quality,
The technology applied to the trunk line transmission line and the non-trunk line transmission line such as the optical subscriber line can be standardized, and it is possible to adapt to the operation mode inexpensively and flexibly. In the present embodiment, a single error correction decoding circuit 61 is provided to perform a decoding process on a single specific field included in each frame. For example, decoding is performed on a plurality of fields, respectively. When it is required to perform the conversion processing, a desired number of error correction decoding circuits and a serial / parallel conversion circuit arranged in front of these circuits are provided, and the timing generator 65 is provided with these error correction decoding circuits. It is also possible to realize a configuration in which a pulse indicating a period during which the result of the decoding process performed by the above is obtained.

FIG. 7 is a diagram showing an embodiment corresponding to the third aspect of the present invention. In the figure, components having the same functions and configurations as those shown in FIG. 4 are denoted by the same reference numerals, and description thereof is omitted here. The difference between the present embodiment and the embodiment shown in FIG. 4 is that the counting units 71-1 to 71-8 having twelve input terminals individually have the counting unit 6
Error correction decoding circuits 61-1 and 61-2 which are provided in place of 2-1 to 62-8 and individually have 16 outputs are provided in place of error correction decoding circuit 61, and error correction decoding circuits 61- 1,
Between the stage between 61-2 and the counting units 71-1 to 71-8, 32 connected to the outputs of these error correction decoding circuits 61-1 and 61-2.
Latches 72-1 to 72-3 each having a separate input terminal are arranged, and the clock terminals of the latches 72-1 to 72-3 are connected to the outputs of the clock generators 73-1 to 73-3. It is in.

As for the correspondence between the present embodiment and the block diagram shown in FIG. 2, the BIP operation unit 112 corresponds to the discrimination means 20, and the error correction decoding circuits 61-1 and 61-2 correspond to the error bit detection means. 21 and the clock generation unit 73-1
73-3 and latches 72-1 to 72-3 are holding means 22-1.
Counters 71-1 to 71-8 correspond to error bit number discriminating means 23-1 to 23-N.
The flip-flop 64, the timing generator 65, and the quality deterioration detector 113 correspond to the monitoring result output unit 24.

FIG. 8 is an operation timing chart of the embodiment according to the third aspect of the present invention. Hereinafter, FIG.
The operation of the present embodiment will be described with reference to FIG. The error correction decoding circuits 61-1 and 61-2 perform error correction coding for each frame given in the order of time series.
The decoding process is performed on the two fields, and two words having a bit length of 16 bits, which indicate bits in which a bit error has occurred as a result of the decoding processes, are sequentially output (FIG. 8).

The clock generators 73-1 to 73-3 are
Clocks indicating three timings at which the results of these decoding processes are obtained in frame units are generated in synchronization with the above-described decoding processes. Latches 72-1 to 72-3
Holds two words obtained at the outputs of the error correction decoding circuits 61-1 and 61-2 in synchronization with the clock generated in this manner (FIG. 8 to FIG. 8).

Further, the timing generating section 65 generates a pulse for every three consecutive frames in a time series, unlike the first and second aspects of the present invention (FIG. 8). That is, the counting units 71-1 to 71-8 and the OR gate 63
As described above, it is determined whether or not there are a plurality of bits in which a bit error has occurred in a unit of six fields which are included in each frame and which are error-correction-coded and consecutive in time series. It can be carried out.

As described above, according to the present embodiment, FIG.
As shown in (a) and (b) in comparison with the embodiment corresponding to the invention described in claim 2, the error correction decoding circuit 61-1
With respect to a plurality of fields provided in chronological order under the common use of 61-2, the presence or absence of occurrence of a bit error over a plurality of bits is reliably determined while associating with the target of the BIP operation, and the result of the determination Is reliably sent to the operation center together with the result of the BIP operation performed by the BIP operation unit 112.

FIG. 10 is a diagram showing an embodiment corresponding to the fourth aspect of the present invention. In the figure, components having the same functions and configurations as those shown in FIG. 7 are denoted by the same reference numerals, and description thereof is omitted here. The difference between this embodiment and the embodiment shown in FIG. 7 is that the error correction decoding circuits 61-1 and 61-2, the latches 72-1 to 72-3, and the clock generation units 73-1 to 73-3. Instead, a serial-parallel conversion unit 81, an error correction decoding circuit 82, a pseudo bit adding unit 83, and a serial-parallel conversion unit 84 which are connected in cascade are provided, and a counting unit is used instead of the counting units 71-1 to 71-8. 85-1 to 85-4, an OR gate 86 is provided in place of the OR gate 63, and the output of the timing generation unit 65 is output to the serial-parallel conversion unit 8.
4 at the point connected to the clock terminal.

In the counting section 85-1, the serial input D of the 2-bit counter 87 is connected to the corresponding output of the serial-parallel conversion section 84, and the clear terminal C of the 2-bit counter 87-1 is connected to the above-mentioned terminal. The output of the timing generator 65 is connected. Of the count output of the 2-bit counter 87-1, one output corresponding to the least significant bit is connected to the negative logic input of the AND gate 88, and the other output is connected to the positive logic input of the AND gate 88. You. AND gate 88-1
Is connected to the count enable terminal CE of the 2-bit counter 87 and the corresponding input of the OR gate 86.

Since the configuration of the counting units 85-2 to 85-4 is the same as that of the counting unit 85-1, the corresponding components are assigned the same reference numerals as "2" to "4". The reference numerals are given and the description is omitted here. Also, regarding the correspondence between the present embodiment and the block diagram shown in FIG. 3, the BIP operation unit 112 corresponds to the determination unit 11 and
The parallel conversion unit 81 corresponds to the division processing unit 31, the error correction decoding circuit 82 corresponds to the error bit detection unit 32, the pseudo bit addition unit 83 and the serial-parallel conversion unit 84 correspond to the bit processing unit 33, The units 85-1 to 85-4 correspond to the error bit number discriminating means 34-1 to 34-N.
6, the flip-flop 64, the timing generator 65, and the quality degradation detector 113 correspond to the monitoring result output means 35.

The operation of the embodiment according to the fourth aspect of the present invention will be described below with reference to FIG. In the present embodiment, the number of bits (hereinafter, referred to as “parallel expansion number”) in which transmission information given via a transmission path is expanded in parallel inside the transmission device according to the embodiment is given in advance, and The number of parallel expansions is smaller than the number of bits N which is a unit of a desired BIP operation. Therefore, the BIP operation unit 112
Performs a BIP operation after dividing transmission information into N-bit units via a serial-to-parallel converter (not shown).

However, since the number of bits N is generally smaller than the word length of the applied error correction code, the serial-to-parallel converter 81 performs serial-to-parallel conversion on the transmission information described above. The word length is converted into a word length to be decoded by the error correction code. In addition, the error correction decoding circuit 82 sequentially acquires and decodes the transmission information of the word length, and decodes the bit string indicating the position of the bit in which the bit error has occurred (here, for simplicity, the bit in which the bit error occurs is It is assumed that a logical bit is indicated by a logical value “1” and a normal bit is indicated by a logical value “0”.). The pseudo-bit adding unit 83 synchronizes the individual frames given as the transmission information described above under the control of a synchronization control unit (not shown), and performs the above-described processing for the fields to which the error correction coding method is not applied. In addition, a bit string to be counted is obtained by adding a pseudo bit having a logical value of “0” instead of the bit string obtained by the pseudo bit adding unit 83.

Further, the serial-to-parallel converter 84 performs serial-to-parallel conversion on the bit string to be counted. Counting units 85-1 to 85
-4 is the number of bits (each individually corresponding to an error bit) included in the bit string to be counted obtained under such serial-parallel conversion and having a logical value of "1". Claims 1-3 when counting and when the number exceeds "2"
Is notified to the operation center via the OR gate 86, the flip-flop 64, and the quality deterioration detection unit 113 in the same manner as in the embodiment corresponding to the invention described in (1).

As described above, according to the present embodiment, regardless of the word length of the applied error correction code and the frame configuration, the bit error is reliably reduced to a plurality of bits in the field given as the error correction code. A determination is made as to whether or not the transmission quality has occurred over a period of time, and the transmission quality is notified to the operation center together with the result of the BIP operation in the same manner as in the embodiment according to the first to third aspects of the present invention.

In the present embodiment, the serial-parallel converter 81 is provided because the word length of the error correction code is longer than the number of parallel expansions. However, the present invention is not limited to such a configuration. Conversely, if the word length of the error correction code is shorter than the number of parallel expansions, the error correction code may be configured without the serial-parallel converter 81 or may be provided with the parallel-serial converter that absorbs the difference between the two. Good.

FIG. 11 is a diagram showing an embodiment corresponding to the fifth aspect of the present invention. In the figure, components having the same functions and configurations as those shown in FIG. 10 are denoted by the same reference numerals, and description thereof is omitted here.
The difference between this embodiment and the embodiment shown in FIG. 10 is that latches 101-1 to 101-3 whose inputs are connected in parallel are provided instead of the serial-to-parallel converter 81. Error correction decoding circuits 102-1 to 102-3 cascade-connected individually to -1 to 101-3 are provided in place of the error correction decoding circuit 82, and a selector 103 is provided in place of the pseudo bit addition unit 83. It is in the point.

As for the correspondence between the present embodiment and the block diagram shown in FIG. 3, the BIP operation unit 112 corresponds to the determination unit 11, and the latches 101-1 to 101-3 correspond to the division processing unit 31. Error correction decoding circuits 102-1 to 102
-3 corresponds to the error bit detecting means 32 and the selector 103
And the serial-parallel conversion unit 84 corresponds to the bit processing unit 33, and the counting units 85-1 to 85-4 correspond to the error bit number determination unit 34.
-1 to 34-N, the OR gate 86, the flip-flop 64, the timing generator 65, and the quality deterioration detector 1
13 corresponds to the monitoring result output means 35.

Hereinafter, the operation of this embodiment will be described. The latches 101-1 to 101-3 extract a plurality of fields to which different error correction coding schemes are individually applied for each frame including transmission information under synchronization control performed by a synchronization control unit (not shown). Hold. Further, the error correction decoding circuits 102-1 to 102-3 individually perform decoding processing on the individual fields held in this manner, thereby generating a bit string indicating the position of the bit in which the bit error has occurred. .

Further, the selector 103 sequentially selects and outputs the above-described bit strings under the above-described synchronization control and frame configuration, and selects any bit strings for fields that do not correspond to any of these bit strings. Such a selection will be suspended. That is, the serial-parallel converter 84
Is provided with a plurality of fields to which a plurality of different error correction coding schemes are applied since a bit string including pseudo bits is reliably provided in the same manner as in the embodiment according to the fourth aspect of the present invention. The frame consisting of
The transmission information can be monitored in the same manner as in the embodiment according to the first to fourth aspects of the present invention.

[0060]

As described above, according to the first aspect of the present invention, even for a transmission line whose transmission quality is lower than that of the main line transmission line, the technology applied to such a trunk line transmission system can be used. The transmission quality is monitored with high accuracy. According to the second aspect of the present invention, complex synchronization control and timing adjustment are performed as long as the difference between the probability of occurrence of a bit error between a specific field subjected to error correction coding and other fields is acceptably small. A bit error of a plurality of bits is detected with high accuracy for each small set without necessity.

According to the third aspect of the present invention, even for a transmission path having a transmission quality lower than that of the main transmission path, the first and second embodiments utilize the technology applied to the main transmission path. The transmission quality is monitored more accurately than the transmission quality monitoring device according to the invention. According to the fourth aspect of the present invention, the hardware configuration is simplified, and, similarly to the transmission quality monitoring apparatus according to the first to third aspects of the present invention, the transmission path lower than the trunk transmission path is also used. The transmission quality is monitored with high accuracy.

According to the fifth aspect of the present invention, even if different error correction coding schemes are applied to a plurality of specific fields, the transmission quality monitoring apparatus according to the fourth aspect of the present invention operates in the same manner. Also, the transmission quality of a transmission path lower than the transmission path of the trunk system is monitored with high accuracy. Therefore, according to these inventions, even for an optical subscriber line or the like having a lower transmission quality than the trunk line transmission line, the transmission quality is monitored accurately and inexpensively. It is possible to take prompt measures and to improve the service quality in accordance with the maintenance and operation efficiency.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the principle of the present invention.

FIG. 2 is a principle block diagram of the invention according to claim 3;

FIG. 3 is a principle block diagram of the invention according to claims 4 and 5;

FIG. 4 is a diagram showing an embodiment corresponding to the first and second aspects of the present invention.

FIG. 5 is an operation timing chart of the embodiment according to the first and second aspects of the present invention;

FIG. 6 is a diagram for explaining the operation of the embodiment corresponding to the first and second aspects of the present invention.

FIG. 7 is a diagram showing an embodiment corresponding to the invention described in claim 3;

FIG. 8 is an operation timing chart of the embodiment corresponding to the invention described in claim 3;

FIG. 9 is a diagram showing a difference between the embodiments according to the second and third aspects of the present invention.

FIG. 10 is a diagram showing an embodiment corresponding to the fourth and sixth aspects of the present invention.

FIG. 11 is a diagram showing an embodiment corresponding to the invention described in claim 5;

FIG. 12 is a diagram (1) illustrating a conventional example of a transmission device that monitors transmission quality.

FIG. 13 is a diagram illustrating monitoring of transmission quality based on BIP.

FIG. 14 is a diagram (2) illustrating a conventional example of a transmission device that monitors transmission quality.

[Explanation of symbols]

 11, 20 discriminating means 12, 21, 32 error bit detecting means 13, 23, 34 error bit number discriminating means 14, 24, 35 monitoring result output means 22 holding means 31 division processing means 33 bit processing means 61, 82, 102 error Correction decoding circuit 62, 71, 85 Counting unit 63, 86 OR gate 64 Flip-flop 65 Timing generation unit 66, 88 AND gate 67 NOR gate 72, 101 Latch 73 Clock generation unit 81, 84 Serial-parallel conversion unit 83 Pseudo bit addition unit 87 2-bit counter 103 selector 111 bit error correction circuit 112 BIP operation unit 113 quality deterioration detection unit 121 error bit number measurement unit

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Tomohiro Shinomiya 4-1-1, Kamidadanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Setsuo Adome 4-1-1 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa No. 1 Fujitsu Co., Ltd. (72) Inventor Masaki Hirota 4-1-1, Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu Co., Ltd. (72) Inventor Shogo Miyabe 4-chome, Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture No. 1 Inside Fujitsu Limited (72) Inventor Masaaki Kawai 4-1-1, Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu Limited (72) Yoshiro Takigawa 3--19 Nishishinjuku, Shinjuku-ku, Tokyo No. 2 Nippon Telegraph and Telephone Corporation

Claims (5)

[Claims] 1. A plurality of frames each having a specific field subjected to error correction coding are fetched from a transmission path, and a predetermined number N of bits in a time series among bits individually included in these frames. Discriminating means for discriminating the presence / absence of a bit error based on a BIP method for N sets of a plurality of separated unique bits, and decoding adapted to the error correction decoding method for the specific field Error bit detecting means for obtaining a bit string indicating whether or not a bit error has occurred as a result in bit units; and a bit string obtained by the error bit detecting means, the bits individually belonging to the N sets. It was divided into N small sets, and the bit errors occurred in these small sets based on the logical values of individually included bits. Error bit number discriminating means for discriminating whether the number of bits is plural, and a logical sum of a result of the discrimination performed by the discriminating means and a result of the discrimination performed by the error bit number discriminating means And a monitoring result output means for multiplexing and outputting the results. 2. The transmission quality monitoring apparatus according to claim 1, wherein the specific field is error-correction-coded based on a single error-correction coding scheme, and A transmission quality monitoring apparatus characterized in that a bit string is obtained by performing decoding on a frame basis based on a correction coding scheme. 3. A plurality of frames in which a plurality of specific fields are error-correction-coded are fetched from a transmission path, and a predetermined number N of bits sequentially included in these frames in a time-series order. Discriminating means for discriminating the presence / absence of a bit error based on the BIP method for N sets of a plurality of unique bits separated by bits, and for each specific field included in the plurality of frames, Error bit detection means for performing decoding adapted to the method of correction decoding, and as a result, a bit string indicating whether or not a bit error has occurred in bit units in order of time series, and the error bit detection means A plurality of holding means for holding a bit string in the order of the time series, and updating at a cycle of a multi-frame composed of the plurality of frames; The bit string held by the holding unit is divided into N small sets each consisting of bits individually belonging to the N sets, and the bit error of each of these small sets is determined based on a logical value of a bit individually included. Error bit number discriminating means for discriminating whether or not the number of bits in which the error has occurred is plural; and a result of the discrimination performed by the discriminating means, a result of the discrimination performed by the error bit number discriminating means. A transmission quality monitoring device comprising: a monitoring result output unit that multiplexes and outputs a logical sum. 4. A plurality of frames in which a specific field is subjected to error correction coding are fetched from a transmission path, and a predetermined number N of bits are individually set in a time series among bits individually included in these frames. Discriminating means for discriminating the presence / absence of a bit error based on the BIP method for N sets of a plurality of unique bits separated from each other; Division processing means for generating a bit string to be decoded by dividing the field into a plurality of words that are included without being divided, and for the bit string to be decoded generated by the division processing means, Perform a decoding suitable for the error correction decoding method, a bit sequence indicating whether or not a bit error has occurred as a result in a bit unit in a time series order Error bit detecting means, and the bit strings obtained by the error bit detecting means are taken in, and among these bit strings, the logical value of a bit string corresponding to a word that does not include the field under the frame configuration is determined by the bit error. Bit processing means for generating a bit string to be determined by substituting a value indicating a bit in which no bit occurs, and N bits consisting of bits individually belonging to the N sets of the bit string to be determined generated by the bit processing means. Error bit number discriminating means for discriminating whether or not the number of bits in which the bit error has occurred is plural based on the logical value of bits individually included in these small sets. Multiplexing the result of the determination made by the determination means and the logical sum of the result of the determination made by the error bit number determination means Transmission quality monitoring apparatus characterized by comprising a monitoring result output means for outputting. 5. The transmission quality monitoring apparatus according to claim 4, wherein the specific field includes a plurality of fields to which different error correction coding schemes are individually applied, and the division processing unit converts the plurality of frames into frames. A transmission quality monitoring device, characterized in that the transmission quality monitoring device has a word length equal to or longer than the maximum word length of the plurality of fields under the configuration, and divides these fields into a plurality of words included without being divided.