JPH10199977A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor device, having good shape free from voids or the like and good electrical characteristics, without generating etching-back residues and recesses due to overetching. SOLUTION: After a contact hole, abutting against an active region formed on a semiconductor substrate 1 has been formed, the contact hole is filled with a conducting material such as titanium silicide, a copper alloy and a silver alloy, extra conducting material laminated outside the contact hole is etched and eliminated by using a CPM(chemical-mechanical polishing) method, and a contact 4 is formed. By forming an upper layer wiring 5 in contact with the contact 4, a contact having good shape and electrical characteristics can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, for example, a memory such as a DRAM (dynamic random access memory) or a logic device, and an active region formed of an impurity region on a semiconductor substrate or a gate formed by a lower wiring. The present invention relates to a method for manufacturing a contact connected to an electrode or the like.

[0002]

2. Description of the Related Art FIG. 11 is a sectional view of a contact forming portion of a conventional semiconductor device. In FIG. 11, reference numeral 101 denotes a semiconductor substrate; 102, an active region formed on the surface of the semiconductor substrate 101; 103, an interlayer insulating film laminated on the semiconductor substrate 101; The contact 104 is in contact with the region 102 and formed at the height of the surface of the interlayer insulating film 103. The contact 104 is formed on the surface of the active region 102 and the interlayer insulating film 10.
3. An adhesion layer 10 made of a conductive material that adheres to the cross section on the opening side
5 and a tungsten plug 106 attached to the surface of the adhesion layer 105. 107 is a void formed inside the contact 104,
08 is in contact with the upper part of the contact 104 and the interlayer insulating film 10
Reference numeral 109 denotes a wiring disposed on the wiring 3, and reference numeral 109 denotes an anti-reflection film laminated on the surface of the wiring 108.

Next, a method of manufacturing a semiconductor device including a contact having the structure shown in FIG. 11 will be described. First, as shown in FIG. 12, an interlayer insulating film 103 is stacked on a semiconductor substrate 101, and the interlayer insulating film 103 is selectively etched to form a contact hole 110. After that, impurity ions are implanted into the semiconductor substrate 101 located on the bottom of the contact hole 110 to form an active region 102. There is no problem if the active region 102 is formed before the interlayer insulating film 103 is laminated.

[0004] Thereafter, as shown in FIG.
A TiN / Ti layer is sequentially laminated to a thickness of 100/20 nm by an emical vapor deposition) method, and an adhesion layer 105 a made of the TiN / Ti layer is laminated on the inner wall of the contact hole 110 and the upper surface of the interlayer insulating film 103. .

[0005] Next, as shown in FIG.
Is buried with the tungsten 106a. At this time, when the diameter (in the horizontal direction) of the contact hole 110 is a fine hole of 0.3 μm or less, the adhesion layer 105 a already formed inside the contact hole 110 is formed.
However, in the vicinity of the opening of the contact hole 110, an overhang phenomenon (a phenomenon in which a larger amount of titanium nitride is attached to the vicinity of the opening than the bottom of the contact hole and the diameter of the opening of the contact hole becomes smaller) occurs. Before the inside of the contact hole 110 is completely buried with tungsten, the opening of the contact hole 110 is closed by the tungsten 106a. Therefore, the contact hole 110 is not completely buried by the adhesion layer 105a and the tungsten 106a, and the inside of the contact hole 110 is in a state where the void 107 is formed.

Then, as shown in FIG. 15, using a fluorine-based or chlorine-based gas such as SF ₆ or Cl ₂ ,
The tungsten 106a and the adhesion layer 105a stacked above the surface of the interlayer insulating film 103 are removed by etching, and the tungsten 10a is formed only in the contact hole 110.
6. The contact 104 is formed while leaving the adhesion layer 105.

Next, the wiring 10 is formed by a sputtering method.
And an anti-reflection film 10
9 is laminated. After that, patterning is performed on these films, and the wiring 108 and the antireflection film 1 having arbitrary dimensions are formed.
By forming 09, a structure as shown in FIG. 11 is obtained. However, due to poor coverage in the contact hole 110, the void 107 remains, and there is a problem that the resistance of the contact 104 increases and the device reliability decreases.

Another prior art is disclosed in Japanese Unexamined Patent Publication No.
No. 90425, an interlayer insulating film is laminated on a semiconductor substrate, a contact hole is formed, a titanium silicide buried layer is selectively buried to a depth of about 80% inside the contact hole, and a surface of the titanium silicide buried layer is formed. Selectively laminated titanium nitride, and further laminated another titanium nitride by sputtering method,
After stacking a tungsten layer on the upper layer by CVD,
By removing the conductive material laminated above the surface of the interlayer insulating film by E (reactive ion etching),
It is disclosed that a wiring made of tungsten embedded in an interlayer insulating film is formed on titanium silicide to be a contact via titanium nitride.

In the semiconductor device thus formed, a titanium silicide film is selectively buried from the bottom of the contact hole up to about 80% of the depth of the contact hole, and the depth of the contact hole is reduced when the contact hole is opened. After reducing it to about 20% of
Since the titanium nitride film is laminated, the overhang phenomenon due to the titanium nitride can be suppressed, and a contact can be obtained without forming a void.

Next, a conventional method for forming a contact with a more simplified structure will be described below. First, a contact hole 110 is formed as in the case shown in FIG. 12, and then, as shown in FIG. 16, the titanium silicide film 111a is formed.
Are laminated. At this time, the inside of the contact hole 110 is completely buried with the titanium silicide film 111a, and the titanium silicide film 111a is also laminated on the interlayer insulating film 103. The titanium silicide film 111a stacked on the interlayer insulating film 103 has a poor surface morphology as compared with the case where tungsten is stacked, and the surface is not flat and irregular.

Next, as shown in FIG. 17, the titanium silicide film 111a laminated on the interlayer insulating film 103 is etched back by RIE. At this time, in order to leave the titanium silicide film 111 buried in the contact hole 110 and to minimize the recess (dip in the contact hole), irregularities on the surface of the titanium silicide film 111 a are formed on the interlayer insulating film 103. Therefore, the protrusion 112 corresponding to the protruding portion results in a state in which the residue 112 is generated. This residue 112 causes a short circuit between the wirings when the upper wiring is formed, and reduces the yield of the device.

On the other hand, in the case where over-etching is performed so as not to cause the residue 112, as shown in FIG. 18, the titanium silicide film 111 above the contact hole 110 is removed, and the recess 113 becomes large. .

When the recess is large, as shown in FIG. 19, when an aluminum film 114, which is a wiring material, is formed by a sputtering method in a subsequent wiring formation step, the aluminum film 1 is formed on the surface of the interlayer insulating film 103.
14 are stacked so as to have a uniform thickness, but the aluminum film 114 is not filled in the recessed portion (circled portion) on the titanium silicide film 111 constituting the contact.
Since the coverage is deteriorated and the effective cross-sectional area of the conductive portion through which current flows is reduced in this portion, the titanium silicide film 111 which is a low-resistance material is
There is a problem that the wiring resistance is increased in spite of using as a material for burying the inside.

Further, due to poor coverage of the recessed portion, atoms constituting wirings and contacts move when EM (Electromigration: current is flowing),
Migration resistance such as disconnection etc.) and SM (Stressmigration: the problem of wiring atoms moving due to the stress applied to the wiring when left unattended without flowing current) leading to a decrease in device resistance, However, there is a problem that the reliability is lowered.

Further, even when a barrier metal is disposed on the lower surface of the aluminum film 114 so that the titanium silicide film 111 serving as a contact does not directly contact the aluminum film 114 serving as a wiring, the contact made of the titanium silicide film 111 may be used. Above, poor coverage resulted in similar problems.

[0016]

In the prior art, as shown in FIG.
When 0 is buried, voids 107 are formed, which causes a problem that the resistance value of the contact 104 is increased and device reliability is reduced. Further, the semiconductor device described in Japanese Patent Application Laid-Open No. 4-290425 has a contact hole 11 for suppressing the overhang phenomenon.
There is a problem that the number of steps increases because the inside of 0 is embedded a plurality of times.

Further, after the inside of the contact hole 110 is buried with a conductive material, if RIE is performed by RIE in order to remove an excess conductive material laminated on the surface of the interlayer insulating film 103, a portion other than the contact remains. In addition, when over-etching is performed, there is a problem that a recess is formed to deteriorate the coverage of the wiring in the contact portion. An object of the present invention is to solve the above problems.

[0018]

According to the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of: laminating an insulating film on a semiconductor substrate having an active region on the surface or on a lower wiring, on the active region or on the lower wiring. Forming a contact hole by selectively removing the insulating film stacked on the insulating film, forming a contact by burying a titanium silicide film in at least the contact hole, and forming a contact on the insulating film in the titanium silicide film. The method includes a step of removing the layered structure by the CMP method to leave only the contact, a step of patterning a conductive material on the insulating film, and a step of forming an upper wiring electrically connected to the contact.

The upper wiring formed in the method of manufacturing a semiconductor device according to the present invention is formed via a barrier metal layer laminated on the contact.

Further, an anti-reflection film is formed on the surface of the upper wiring formed in the method of manufacturing a semiconductor device according to the present invention.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. Embodiment 1 of the present invention will be described. FIG. 1 is a cross-sectional view of a semiconductor device formed by the method of manufacturing a semiconductor device of the present invention, and shows a structure suitable for a memory such as a DRAM of 1 G or later or a logic device of 0.18 μm or later.

In FIG. 1, reference numeral 1 denotes a semiconductor substrate made of silicon, 2 denotes an impurity region formed on the surface of the semiconductor substrate 1, 3 denotes an interlayer insulating film laminated on the semiconductor substrate 1,
4 is a contact made of a titanium silicide layer formed inside the interlayer insulating film 3 so as to be in contact with the impurity region 2;
Reference numeral 5 denotes upper wirings made of a metal such as an aluminum alloy and formed on the surface of the interlayer insulating film 3 in contact with the upper surface of the contact 4.

In the semiconductor device shown in FIG. 1, the contact 4 is made of low-resistance titanium silicide, the surface of which is formed in a smooth state. In the upper wiring 5 disposed on the surface of the insulating film 3, the surface of the interlayer insulating film 3 and the surface of the contact 4 hardly form a step (recess), so that the connection between the contact 4 and the upper wiring 5 is formed. Can also be in a good state.

Next, a method of manufacturing the semiconductor device having the structure shown in FIG. 1 will be described. First, as shown in FIG. 2, an impurity region 2 is formed on a semiconductor substrate 1 by a method such as impurity ion implantation or thermal diffusion. Thereafter, an insulating film such as a silicon oxide film is laminated by a CVD method or the like so as to have a uniform thickness on the surface of the semiconductor substrate 1, and 800 to 2000 nm depending on a device to be formed.
Is formed. Further, a contact hole 6 in contact with the impurity region 2 is formed by a combination of photolithography and etching. The contact hole 6
Has an opening diameter of 0.3 μm or less, and the depth of the contact 4 is a dimension corresponding to the thickness of the interlayer insulating film 3.
The dimensions are on the order of nm.

Thereafter, as shown in FIG. 3, the flow rate of TiCl _{4 is} about 2 to 50 sccm, and the flow rate of silane is 10 to several hundreds of seconds.
A titanium silicide layer 4a is formed at a flow rate of about ccm and a temperature of about 400 to 800 ° C., and at least the inside of the contact hole 6 is completely buried with the titanium silicide layer 4a. At the same time, a titanium silicide layer 4a is also stacked on the surface of the interlayer insulating film 3.

In forming the titanium silicide layer 4a, a halogen-based gas containing titanium may be used in addition to TiCl ₄ , and a gas containing silicon such as dichlorosilane may be used instead of silane. Further, an inert gas such as argon or helium, or a gas such as nitrogen or hydrogen may be used as one to several slm as a carrier gas. Further, for lowering the process temperature, a titanium silicide layer 4a may be stacked by generating and reacting plasma in a chamber into which TiCl ₄ and silane are introduced.

Next, as shown in FIG. 4, using a foamed polyurethane pad, a slurry containing a solution for etching titanium silicide such as hydrofluoric acid or hydrofluoric nitric acid is used, and the rotation speed is set to about 35 rpm at an upper speed and about 50 rpm at a lower speed. ,
The pressure is about 500 gf / cm ² and the amount of slurry is 200 c
The titanium silicide layer 4a stacked above the surface of the interlayer insulating film 3 is completely removed by the CMP method under the condition of about c / min. In the etching by the CMP method, the surface of the titanium silicide layer 4a left as the contact 4 has the same height as or the same height as the surface of the interlayer insulating film 3, and little or no recess is generated.

Thereafter, the upper layer wiring 5 made of a metal such as aluminum is patterned on the upper surface of the interlayer insulating film 3 by CVD or sputtering so as to be in contact with the contact 4, thereby obtaining the semiconductor device as shown in FIG. It is possible.

As described above, even when a fine connection hole having a diameter of 0.3 μm or less is formed, a low-resistance contact 4 (titanium silicide plug) having no void can be formed. Further, since the excess titanium silicide layer 4a is removed by the CMP method, titanium silicide (residual) remains on the surface of the interlayer insulating film 3. However, a cause such as a short circuit of the upper wiring 5 can be removed, and the yield is prevented from lowering. can do. Further, since no recess is formed on the upper part of the contact 4, the coverage is improved even when the upper wiring 5 is formed, and the EM and SM resistance can be improved.

As in the prior art, when etch-back is performed by a method such as RIE using a nitrogen-based or halogen-based etching gas, the upper wiring 5 is formed by recessing the connection portion.
However, when the upper wiring 5 is patterned and the upper wiring 5 is patterned, the yield of the upper wiring 5 is shortened due to the etch back residue. However, the etching back of the titanium silicide layer 4a is performed by the CMP method as in the present invention. In this case, there is an effect that a good contact structure can be obtained because there is no etch back residue and no recess is generated.

FIG. 5 shows the application of the contact structure of the present invention, and shows a cross section along the gate length direction of two MOS transistors. In FIG. 5, reference numeral 7 denotes an element isolation region, 8 denotes a gate insulating film, 9 denotes a gate electrode having a two-layer structure in which a metal film 9b is stacked on a polysilicon film 9a, for example, and 10 denotes a side cross section of the gate electrode 9. 2 shows a side wall made of an insulating film formed by attaching to an insulating film.

As shown in FIG. 5, contacts 4 are formed so as to be in contact with the surfaces of gate electrode 9 and impurity region 2 serving as source / drain regions, respectively. It is needless to say that one of the contact structures can be electrically connected, and the contact structure can be applied to the other part.

In the first embodiment, when the contact hole 6 is buried with the titanium silicide layer 4a, there is a description that the CVD method may be used.
The description has been given on the assumption that the VD method uses a blanket CVD method in which a deposit is stacked on, for example, the entire surface of a semiconductor substrate so as to have a uniform thickness. However, even if the titanium silicide layer 4a is laminated using a selective CVD method in which a deposit is selectively embedded in the contact hole 6, titanium deposited on the surface of the interlayer insulating film 3 due to a loss of selectivity. In order to remove the silicide layer 4a, etching may be performed using the CMP method as described above.

An unnecessary portion of the titanium silicide layer 4a laminated by the selective CVD method is removed by etching by the CMP method, so that the blanket C is removed.
The same effect as when the titanium silicide layer 4a is stacked by the VD method can be obtained.

Embodiment 2 Next, a second embodiment will be described. In the semiconductor device of the first embodiment described above, the upper wiring 5 is directly stacked on the surface of the interlayer insulating film 3 in contact with the upper surface of the contact 4. As shown in FIG.
And the upper wiring 5 are indirectly in contact with each other via the barrier metal layer 11.

First, a semiconductor device is manufactured according to the manufacturing process shown in FIGS. 2 to 4 of the first embodiment, and is brought into contact with impurity region 2 formed on the surface of semiconductor substrate 1 and laminated on the surface of semiconductor substrate 1. A contact 4 buried in the formed interlayer insulating film 3 is formed. Since the surface of the contact 4 is flattened by the CMP process,
Even if the material forming the contact 4 is titanium silicide, there is no residue on the surface of the interlayer insulating film 3 and the titanium silicide buried in the contact hole 6 is over-etched to form a large recess. I don't have to.

Next, as shown in FIG. 7, a barrier metal layer 11 made of TiN is formed on the surface of the interlayer insulating film 3 and the contact 4 which are formed to be almost flat.
The layers are laminated so as to have a thickness of 0 to 100 nm. As the barrier metal layer 11, in addition to TiN, TiOx ₁ N
It is also possible to use a y ₁ film, a TiN / Ti laminated film, a TiOx ₁ Ny ₁ / Ti laminated film, or a TiSix ₂ Ny ₂ / Ti laminated film. In the above alloys, Ti is replaced by T
It can also be formed by replacing with a high melting point metal film such as a, Mo, W or the like.

Thereafter, the upper wiring 5 is laminated on the barrier metal layer 11 by the same processing as in the first embodiment,
A semiconductor device having a structure as shown in FIG. 6 can be obtained. The semiconductor device thus formed can be connected with a sufficiently low resistance value by interposing the barrier metal layer 11 between the contact 4 and the upper wiring 5, and can be in a good connection state. .

As described above, in forming a fine connection hole having a diameter of 0.3 μm or less, a low-resistance titanium silicide plug (contact 4) is formed without forming a void as in the first embodiment. Forming the barrier metal layer 11 between the contact 4 and the upper wiring 5 has the effect of suppressing problems such as electromigration and obtaining good device characteristics in addition to the effect of the first embodiment.

Embodiment 3 Next, a third embodiment of the present invention will be described. In the second embodiment, the barrier metal layer 11 is formed between the contact 4 and the upper wiring 5, but in the third embodiment, as shown in FIGS. 2 and the upper wiring 5
Is characterized in that an antireflection film 12 is formed as an upper layer.

The manufacturing method of the semiconductor device shown in FIGS. 8 and 9 is different from the manufacturing method shown in the first and second embodiments in that, after the aluminum-based alloy film to be the upper wiring 5 is laminated, for example, TiN or TiN / Ti by sputtering
The anti-reflection film 12 is laminated so as to have a thickness of about 0 to 50 nm.

By forming the antireflection film 12, a resist pattern or the like serving as an etching mask can be accurately formed even when the upper wiring 5 and the barrier metal layer 11 are subsequently patterned. There is an effect that a highly accurate semiconductor device can be obtained. Further, it goes without saying that the semiconductor device according to the third embodiment has the effects described in the first and second embodiments.

Embodiment 4 FIG. Embodiment 1 already described
In Nos. 4 to 4, it was shown that the material constituting the upper wiring 5 was an aluminum alloy film. However, in the fourth embodiment of the present invention, as shown in FIG.
a is characterized by being formed of a copper alloy or a silver alloy. As described above, even when the upper layer wiring 5a is formed of a copper alloy or a silver alloy, it is possible to obtain a favorable wiring as in the case where the upper layer wiring 5 is formed of an aluminum-based alloy film.

[0044]

The effects of each claim of the present invention will be described below. According to the method of manufacturing a semiconductor device according to claim 1 of the present invention, an active region on a semiconductor substrate or a titanium silicide film for connecting a lower wiring and an upper wiring is laminated after opening a contact hole. Excessive titanium silicide film laminated outside the contact hole is removed by the CMP method, so that there is no etch back residue, no recess due to over-etching, and good shape and electrical characteristics without voids etc. A semiconductor device can be obtained.

Further, according to the method of manufacturing a semiconductor device according to the second aspect of the present invention, the material forming the contact and the material forming the upper wiring are formed by interposing a barrier metal layer between the upper wiring and the contact. By separating them from each other, problems such as electromigration can be solved, and a semiconductor device having good device characteristics can be obtained.

According to the method of manufacturing a semiconductor device according to the third aspect of the present invention, an antireflection film is further formed on the upper surface of the upper wiring, thereby forming the antireflection film for patterning the upper wiring. A resist pattern to be formed can be formed with high dimensional accuracy, and a semiconductor device having a good shape can be obtained.

[Brief description of the drawings]

FIG. 1 shows a semiconductor device according to a first embodiment of the present invention.

FIG. 2 shows a manufacturing flow according to the first embodiment of the present invention.

FIG. 3 shows a manufacturing flow according to the first embodiment of the present invention.

FIG. 4 shows a manufacturing flow according to the first embodiment of the present invention.

FIG. 5 shows a semiconductor device according to the first embodiment of the present invention.

FIG. 6 shows a semiconductor device according to a second embodiment of the present invention.

FIG. 7 shows a manufacturing flow according to the second embodiment of the present invention.

FIG. 8 shows a semiconductor device according to a third embodiment of the present invention.

FIG. 9 shows a semiconductor device according to a third embodiment of the present invention.

FIG. 10 shows a semiconductor device according to a fourth embodiment of the present invention.

FIG. 11 is a diagram showing a conventional technique.

FIG. 12 is a diagram showing a conventional technique.

FIG. 13 is a diagram showing a conventional technique.

FIG. 14 is a diagram showing a conventional technique.

FIG. 15 is a diagram showing a conventional technique.

FIG. 16 is a diagram showing a conventional technique.

FIG. 17 is a diagram showing a conventional technique.

FIG. 18 is a diagram showing a conventional technique.

FIG. 19 is a diagram showing a conventional technique.

[Explanation of symbols]

 1. Semiconductor substrate 2. Impurity region 3. 3. interlayer insulating film Contact 4a. Titanium silicide layer 5, 5a. Upper wiring 6. Contact hole 7. 7. Element isolation region Gate insulating film 9. Gate electrode 9a. Polysilicon film 9b. Metal film 10. Sidewall 11. Barrier metal 12. Anti-reflective coating

Claims (3)

[Claims] A semiconductor substrate having an active region on a surface thereof;
Or a step of laminating an insulating film on the lower wiring, a step of selectively removing the insulating film laminated on the active region or the lower wiring, and forming a contact hole, at least a titanium silicide in the contact hole. A step of embedding a film and forming a contact, and, among the titanium silicide films, a film laminated on the insulating film
A semiconductor, comprising: a step of leaving only the contact by removing it by an MP (chemical mechanical polishing) method; a step of patterning a conductive material on the insulating film to form an upper wiring electrically connected to the contact; Device manufacturing method. 2. The method according to claim 1, wherein the upper wiring is formed via a barrier metal layer laminated on the contact. 3. The method according to claim 1, wherein an anti-reflection film is formed on a surface of the upper wiring.