JPH10199842A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To uniformly polish by setting the polish select ratio of a sacrificial film, so that the time taken for removing a polish stopper layer is not less than the time taken for completely removing this film at a second region having a max. film thickness after the exposure of a stopper layer at a first region, having a min. film thickness. SOLUTION: A sacrificial film 8 is polished by the CMP process, using ceria as a slurry with adjusting the solids concn. of the slurry, so that the time taken for perfectly removing the film 8 in peripheral regions II, including its portion having a max. thickness B after the exposure of a conductor layer 5 in memory regions I is substantially equal to or shorter than the time taken for removing the conductor layer 5 of a thickness C in the memory regions I. Even if a local thickness variation of the sacrificial film on the conductor film 5 exists, it is selectively polished uniformly and removed along the shape of an interlayer insulation film 4.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention generally relates to the manufacture of semiconductor devices, and more particularly to the manufacture of semiconductor devices having fine contact holes or capacitors. With the miniaturization of semiconductor devices, there is a need for a technique capable of forming very fine contact holes having a diameter of 1 micron or less with good reproducibility. Such a technique is important for a logic integrated circuit, but is particularly important for a semiconductor memory device such as a DRAM.

[0002]

2. Description of the Related Art FIG. 7 has a self-aligned contact hole.
1 shows the structure of a conventional DRAM. Referring to FIG.
The DRAM includes a field oxide film 1A on a p-type Si substrate 1.
Formed in the active region 1B defined by⁺Mold diffusion
Area 1D₁, 1D_Two, 1D _ThreeAnd on the substrate 1
Is the diffusion area 1D₁And 1D_TwoBetween and 1D_TwoAnd 1
D_ThreeBetween the word line and the gate oxide film
Constituting gate electrode 2 ₁, 2_TwoAre formed respectively.
Further, the gate electrode 2 is provided on the substrate 1.₁, 2_TwoEach of
Self-aligned oxide to cover the top and sidewalls
3₁, 3_TwoHowever, depending on the shape of the gate electrode,
Self-aligned, ie without using a mask process
It is formed. As a result of forming such a self-aligned oxide film,
Oxide film 3₁, 3_TwoAdjacent to the diffusion region 1
D₁, 1D_Two, 1D_ThreeSelf-aligning openings that expose
Use self-alignment, that is, do not use a mask process.
Formed.

Further, an interlayer insulating film 4 is deposited on the substrate 1 so as to fill the gate electrodes covered with the self-aligned oxide films 3 ₁ and 3 _2. Communicating with the opening, that is, the diffusion region 1D ₁ ,
Contact holes 4 ₁ , 1D ₂ , 1D ₃ are exposed.
4 _2, 4 ₃ are formed, respectively.

[0004] In the DRAM of FIG. 7, further to the contact hole 4 _1, 4 _2, 4 ₃ of the wall surface on the diffusion region 1D _1, 1D _2, as is to cover the surface of the 1D _3, respectively conductive amorphous silicon film or polysilicon film 5 _1, 5 _2, 5 ₃ are formed, further wherein the conductive layer 5 _1, 5 _2, 5 ₃ on the dielectric film 6 _and 62, 6 ₃ are respectively deposited . Further, the dielectric films 6 ₁ , 6 ₂ ,
6 _3, polysilicon plug ₇₁ to fill the respective inner cavity, 7 _2, 7 ₃ are formed.

[0005] Of these, the contact hole 4 ₁ and 4
_{In FIG. 3} , the polysilicon plugs 7 ₁ and 7 ₃ are separated from the corresponding conductive films 5 ₁ and 5 ₃ by the dielectric film 6 ₁ or 6 ₃ , and therefore, the DR of FIG.
In the AM, memory cell capacitors C ₁ and C ₂ are formed so as to be connected to the diffusion regions D ₁ and D ₃ .

On the other hand, the contact hole 4 _2, and the upper portion of the dielectric film 6 ₂ is removed, as a result, the polysilicon plug 7 ₂ and the conductive film 5 _2, thus contact with the diffusion region 1D _2. That is, polysilicon plug 7 ₂ to form a bit line contact.

[0007] As explained previously, the DRAM having such a structure, the opening defining a diffusion region 1D ₁ through 1d ₃ is at the same time as the formation of self-aligned oxide layer 3 _1, 3 _2, self Since it can be formed without using a mask process,
The size of the element to be formed can be made extremely fine without being hindered by the problem of the limit of exposure and the problem of alignment error accompanying the mask process.

By the way, when forming the structure of FIG. 7, in fact, shown in FIG. 8 (A), the upper major surface and a contact hole ₄₁ to ₃ substantially uniform interlayer insulating film 4, from a state covered with the conductive film 5, one of the conductive film 5, to remove the portion covering the surface of the interlayer insulating film 4, shown in FIG. 8 (B), the individual conductive film 5 ₁ to 5 _3, it is necessary to realize a state of forming a conductive sleeve separated from each other in each of the contact holes ₄₁ to _3.

Generally, the transition from the state of FIG. 8A to the state of FIG. 8B is performed by etching back or polishing the amorphous or polysilicon film 5 covering the upper main surface of the interlayer insulating film 4. since it is run, especially as it can be seen from the structure of FIG. 7, the conductive film 5 ₂ constituting a part of the bit line contact by, the polysilicon plug 7
_In particular, a highly reliable contact needs to be formed between them.

FIGS. 9A to 9C show an example of forming a conductor sleeve on the inner periphery of a contact hole by an etching back and a chemical mechanical polishing (CMP) process generally used in the related art. Referring to FIGS. 9A to 9C, FIG.
1A shows an interlayer insulating film 12 formed on a Si substrate 11;
And a contact hole 12A formed in the interlayer insulating film 12 and exposing the surface of the substrate 11, and covers the side wall surface of the contact hole 12A and the exposed surface of the substrate 11 on the interlayer insulating film 12. The conductive film 13 made of amorphous silicon or polysilicon
Is deposited.

[0011] In the step of FIG.
An example in which a desired conductor sleeve is formed by performing etch-back by RIE or the like in a direction substantially perpendicular to FIG. However, in FIG. 9B, the initial conductive film 13 is indicated by a broken line.
As can be seen from FIG. 9B, when a simple etch back is performed, the conductive sleeve 13 remaining on the inner periphery of the contact hole 12A becomes thinner and disappears at the bottom of the contact hole. That is, FIG.
In the step (B), a conductive sleeve as shown in FIG. 8B cannot be formed.

On the other hand, in the step of FIG.
Although the conductive film 13 on the surface of the interlayer insulating film 12 is removed by applying the P process, in such a process, abrasive grains and other polishing residues 12x remain in the contact holes.
In order to solve the above-mentioned problem, conventionally, a contact hole is filled with a so-called sacrificial film during an etch-back or CMP process, and in such a state, the conductive film 13 is polished together with the sacrificial film by the etch-back or CMP method. There are known ways to do this.

FIGS. 10A to 10C show an etch-back process using such a sacrificial film. Referring to FIG. 10A, a sacrificial film 14 made of SOG or resist is formed on the structure of FIG.
A is deposited so as to fill A. In the step of FIG.
Sacrificial film 14 and conductive film 13 on interlayer insulating film 12
Are sequentially etched back. Further, in the step of FIG. 10C, the sacrificial film 1 filling the contact hole 12A is formed.
4 is removed by etching or the like to obtain a desired contact structure.

FIGS. 11A to 11C show a CMP process using a sacrificial film. Referring to FIG. 11A, FIG.
9A, a sacrificial film 14 made of SOG or resist is formed on the structure of FIG.
In the step (B), the conductive film 13 is exposed by polishing the sacrificial film 14 by a CMP method. Further, in the step of FIG. 11C, the conductive film 13 is polished and removed by a CMP method, and then in the step of FIG. 11D, the sacrificial film 14 is removed by etching or the like.

FIG. 10A to FIG. 10C or FIG.
In the steps (A) to (D), the problem described with reference to FIG. 9 can be avoided by using the sacrificial film in this manner. DR shown in
When applied to the memory cell area of the AM, there is also a problem to be solved.

[0016]

Problems to be Solved by the Invention FIGS. 12A and 12B
Is a sectional view showing a state in which a sacrificial film 14 made of SOG or a resist film is formed on a semiconductor integrated circuit such as the DRAM of FIG. 7 including a region I in which a large number of memory cells are formed and a peripheral circuit region II. It is a figure and a top view.

As can be seen from FIGS. 12A and 12B,
In such a structure, the sacrificial film 14 fills a large number of contact holes 12A in the region I, so that the thickness in the region I tends to be smaller than the thickness in the region II. Therefore, in such a structure in which the thickness of the sacrificial film is locally changed, a special process is required for selectively removing the sacrificial film.

FIG. 13A shows a state in which a sacrificial film 8 is formed on the structure of FIG. Referring FIG. 13 (A), FIG. 12 (A), the a region in the memory cell region I memory cell is formed corresponding to the I, a number of contact holes ₄₁ to ₃ (B) is formed Therefore, the thickness A of the sacrificial film 8 is generally smaller than the thickness B in the peripheral circuit region II corresponding to the region II other than the memory cell region I.

In such a structure, when the etch-back is performed on the structure of FIG. 13A, the etch-back is performed so that the thickest portion of the sacrificial film 8 in the region II is removed. As a result of such etching, as shown in FIG.
During _{1-4 3,} conductive sleeve 5 ₁ to 5 ₃ would be deeply etched. Therefore, as shown in FIG.
In the case of forming a _{1-7 3,} the reliability of the contact is reduced.

The structure shown in FIG.
Even when the method is applied, dishing occurs in the memory cell region I as shown in FIG. 14, and the flatness of the device is impaired. When the sacrificial film 8 is removed by CMP, polishing is performed using the conductive film 5 as a polishing stopper. However, even if the conductive film 5 acts as an effective polishing stopper in the region II, it is not polished in the memory cell region I. Since the effective area of the conductor film 5 is small, polishing proceeds. When the conductive film 5 is removed in the memory cell region I, the dishing proceeds at a stretch. Such dishing becomes remarkable especially when the sacrificial film 8 is formed of a resist, and becomes a serious problem. FIG. 14 is actually
The structure generated when the sacrificial film 8 is a resist film is shown.

Accordingly, it is an object of the present invention to provide a method of manufacturing a semiconductor device which solves the above-mentioned problems. A more specific object of the present invention is to provide a method of manufacturing a semiconductor device including a step of removing a sacrificial film formed on a insulating film via a conductive film by a CMP method without causing dishing in an underlying insulating film. CMP for sacrificial film or conductive film
It is a general object to provide a method for manufacturing a semiconductor device that can be completely removed selectively from the insulating film by a method.

[0022]

SUMMARY OF THE INVENTION According to the present invention, the above-mentioned object is achieved on a base structure covered with a polishing stopper layer, the thickness of which varies depending on the location. In a method for manufacturing a semiconductor device including a step of selectively removing a sacrificial film by a chemical mechanical polishing method, a polishing selection ratio of the sacrificial film with respect to the polishing stopper layer at the time of the chemical mechanical polishing is determined by using the polishing stopper layer. After the polishing stopper layer is exposed in the first region where the thickness of the sacrifice film is minimum, the time required for polishing and removing the sacrifice film is reduced in the second region where the thickness of the sacrifice film is maximum. According to a method for manufacturing a semiconductor device, wherein the time required until the film is completely polished and removed is set to be substantially equal or larger, or as described in claim 2, Conductive film Is formed on the covered underlying structural made of an insulating film, the sacrificial film thickness is changed depending on the location, together with the conductor layer, selectively leaving the insulating film,
A method of manufacturing a semiconductor device including a step of removing by a chemical mechanical polishing method, wherein a resist film is used as the sacrificial film, and the resist film and the conductor film are sequentially polished and removed by the same slurry. 4. The method according to claim 3, wherein the chemical mechanical polishing step is performed such that a polishing rate ratio of the conductor film to the insulating film falls within a range of 5 to 30. As described above, the underlayer structure includes the first region where the thickness of the sacrificial film is minimum and another second region, and in the underlayer structure, a plurality of openings are formed in the first region. 5. The method according to claim 2, wherein a step is formed in the second region, and a maximum inclination angle of the step is 24 ° or less. As described A conductor formed on the insulating film so as to continuously cover the first region having a plurality of openings and the second region having irregularities along the surface shape of the insulating film; Selectively forming a film with respect to the insulating film;
In a method of manufacturing a semiconductor device including a chemical mechanical polishing step of removing by a chemical mechanical polishing method, the chemical mechanical polishing step has a polishing rate ratio of the conductor film to the insulating film of 5 to 5.
30. The method according to claim 30, wherein the second region has a maximum inclination angle of 24 °.
According to the method for manufacturing a semiconductor device according to claim 4, or as described in claim 6,
In a method for manufacturing a semiconductor device including a plurality of memory cell transistors in a memory cell region on a substrate, an interlayer insulating film is formed on the substrate so as to cover the plurality of memory cell transistors, and in the interlayer insulating film, Forming a plurality of contact holes corresponding to the plurality of memory cell transistors; and forming the plurality of contact holes in the memory cell region on the interlayer insulating film so as to include the plurality of contact holes. Depositing a conductive film with a substantially uniform thickness so as to include a region other than the cell region; and filling a plurality of contact holes in the memory cell region with a sacrificial film on the conductive film. And a step of depositing the sacrificial film so as to cover a region other than the memory cell region. A chemical mechanical polishing step of polishing and removing by a polishing method, during the chemical mechanical polishing step, the polishing selection ratio of the sacrificial film to the conductor film, the time required to polish and remove the conductor film, After the conductor film is exposed in the memory cell region, in a region where the thickness of the sacrificial film other than the memory cell region is maximized,
8. A method for manufacturing a semiconductor device according to claim 7, wherein the time required until the sacrificial film is completely polished and removed is set to be substantially equal to or greater than the time required. In the chemical mechanical polishing step, the sacrificial film is polished and removed by a first polishing agent.
A second chemical mechanical polishing step of polishing / removing with another polishing agent, or a method of manufacturing a semiconductor device according to claim 6, or as described in claim 8,
In a method of manufacturing a semiconductor device including a plurality of memory cell transistors in a memory cell region on a substrate, an interlayer insulating film is formed on the substrate so as to cover the plurality of memory cell transistors, and in the interlayer insulating film, Forming a plurality of contact holes corresponding to the plurality of memory cell transistors; and forming the plurality of contact holes in the memory cell region on the interlayer insulating film so as to include the plurality of contact holes. Depositing a conductive film with a substantially uniform thickness so as to include a region other than the cell region; and filling a plurality of contact holes in the memory cell region with a sacrificial film on the conductive film. A step of depositing so as to cover a region other than the memory cell region, and the sacrificial film, together with the conductor film,
A chemical mechanical polishing step of selectively polishing and removing the interlayer insulating film by a chemical mechanical polishing method, wherein the step of depositing the sacrificial film comprises: depositing a resist film as the sacrificial film; A semiconductor, wherein the polishing step is performed by using the same slurry as the resist film and the conductive film so that a polishing rate ratio of the conductive film to the insulating film falls within a range of 5 to 30. According to a method for manufacturing a device or as described in claim 9, the interlayer insulating film has a first region in which the thickness of the sacrificial film is minimum, and a second region different from the first region. In the interlayer insulating film, a plurality of openings are formed in the first region, and irregularities are formed in the second region, and a maximum inclination angle of the irregularities is 24 ° or less. 9. The method for manufacturing a semiconductor device according to claim 8, wherein: More, resolve.

Hereinafter, the principle of the present invention will be described. According to the present invention, in a structure in which a large number of contact holes are formed in an interlayer insulating film such as a memory cell region of a DRAM, the surface of the interlayer insulating film may be selected from a conductor film covering the surface of the interlayer insulating film and the inner wall surface of the contact hole. Only the part that covers
The contact hole is filled with a sacrificial film, and is selectively removed by chemical mechanical polishing. At this time, prior to the chemical mechanical polishing of the conductor film, the sacrificial film deposited on the conductor film needs to be chemically mechanically polished. By optimizing, even in the memory cell region where the thickness of the sacrificial film is thin and in the region where the thickness of the sacrificial film is thickly deposited, the conductor film can be exposed substantially at the same time. In a memory cell region having a small thickness, occurrence of dishing can be suppressed. Polishing selectivity can be optimized by adjusting the concentration of the abrasive.

Further, in the present invention, by using a resist as the sacrificial film, the polishing of the sacrificial film and the polishing of the conductor film can be performed in a single polishing step using the same polishing agent. The resist does not have a substantial resistance to chemical mechanical polishing. At this time, by setting a polishing rate ratio of the conductor film to the interlayer insulating film in a range of 5 to 30, the resist is applied to the memory cell region. Without dishing, only the conductor film can be selectively and completely polished with respect to the interlayer insulating film. In such polishing, the conductor film tends to remain in the recesses in the region other than the memory cell region. However, the polishing selection ratio of the conductor film to the interlayer insulating film is optimized as described above, and the region other than the memory cell region is By setting the maximum inclination angle of the unevenness on the surface of the interlayer insulating film at 24 ° or less, the conductive film remaining in the concave portion can be substantially eliminated.

[0025]

1A and 1B show a process of manufacturing a DRAM according to a first embodiment of the present invention. However,
FIG. 1A corresponds to the structure of FIG.
In (A) and (B), the same parts as those described above are denoted by the same reference numerals, and description thereof will be omitted.

Referring to FIG. 1A, the conductor film 5 is made of an amorphous silicon film or a polysilicon film doped with impurities such as P, and the sacrificial film 8 is formed by spin-coating SOG. However, since the SOG sacrificial film 8 is later dissolved and removed in HF or the like, the baking following the spin coating is performed in a range of room temperature to 300 ° C., preferably 5 ° C.
It is preferable to carry out in the range of 0 to 200 ° C. As described above, the sacrificial film 8 includes the memory cell region I and the peripheral region II.
And the thickness is different in the region I.
I has a maximum value B. The minimum value A is typically 0.1
〜0.2 μm, and the maximum value is typically about 0.6 μm. Further, the conductor film 5 typically has a thickness of 0.05 to
It has a thickness C of about 0.1 μm.

In the process of shifting from the state of FIG. 1A to the state of FIG. 1B, the sacrificial film 8 is polished by a CMP process using ceria (CeO ₂ ) as a slurry. In this embodiment, the solid concentration of the slurry is adjusted so that the sacrificial film 8 in the peripheral region II after the conductor layer 5 is exposed in the memory cell region I includes the portion where the film thickness is the maximum value B. Time to complete removal
The time is set so as to be substantially equal to or shorter than the time required until the conductor layer 5 having the thickness C in the memory cell region I is removed. In other words, the slurry is prepared so that (BA) / V _I ≦ C / V _II is satisfied. Where V _I is
Polishing rate of the SOG sacrificial film 8 of the slurry, V _II represents a polishing rate of the conductor layer 5 of the slurry.

[0028] By setting in this manner the polishing rate V _I, V _II, as shown in FIG. 1 (B), the sacrificial film on the conductive film 5, even when there is local variations in thickness In addition, it is possible to selectively polish and remove the shape along the shape of the interlayer insulating film 4. Tables 1 and 2, typical in the CMP method using the ceria slurry, the polishing rate and P for CVD-SiO ₂ in the case of variously changing the solid concentration of the slurry
4 shows the relationship with the polishing rate for doped polysilicon.
However, Table 1 shows the ceria abrasive RNTC00 manufactured by Rodale.
Table 3 shows the case where the same Rodale ceria abrasive RNTC004 was used. In either case,
The polishing speed when the polishing agent is dropped at a rate of 250 cc / min at the same polishing pressure while using a polishing pad made of Fujimi Surfin018-3 as a polishing cloth and the rotation speed of the platen and the polishing head at 70 rpm is shown.

[0029]

[Table 1]

[0030]

[Table 2]

However, in Tables 1 and 2, the solid concentration of the stock solution was 10 wt%, and the polished polysilicon layer was doped with P to an impurity concentration of 1.4 × 10 ²¹ cm ^−3. Was. After the step of FIG. 1B, the conductor layer 5 is polished and removed using colloidal silica as an abrasive,
SO that further filling the contact hole ₄₁ to ₃
G is removed by etching with HF or the like to obtain FIG.
The desired structure shown in (B) is obtained.

When the structure shown in FIG. 8B is obtained, a DRAM shown in FIG. 7 can be formed by forming a dielectric film and a polysilicon plug thereon. Next, a second embodiment of the present invention will be described with reference to FIGS. Referring to FIG. 2A, FIG.
Is similar to the structure of FIG. 1A, but a resist film is used as the sacrificial film 18 instead of the SOG sacrificial film 8.
Since the resist film can be polished using only water and does not substantially resist polishing by the CMP method, FIG.
When polishing is performed on the structure of FIG. 3A, the sacrificial film 18 is immediately polished and removed. In this embodiment, the conductive film 5 is further removed by CMP following the polishing of the sacrificial film 18.

When such a CMP process is performed on the structure shown in FIG. 2A, the peripheral region II is continuously covered with the interlayer insulating film 4 and the conductor film 5 thereon.
Since the memory cell area I is the number of the contact hole ₄₁ to ₃ formed in the interlayer insulating film 4, the memory cell area I, the interlayer insulating film 4 at the time of polishing the conductive film 5 in the region II This is easily removed by polishing, and causes the dishing problem described above with reference to FIG.

In order to suppress the occurrence of such dishing, the polishing selectivity between the interlayer insulating film 4 and the conductor film 5 may be increased as much as possible. In the structure shown in FIG. corresponding to the word line pattern 2 ₃ or the like on the film 1A is uneven portion 4A is formed, the complete removal of the conductive film 5 in the recess with such irregular portion 4A, FIG. 3 (a) ~ (C), as shown in FIG.
Polishing itself is essential. That is, if the polishing selectivity is too large, the removal of the conductor film 5 on the interlayer insulating film 4 becomes incomplete. However, the above-described dishing problem occurs as a result of polishing of the interlayer insulating film 4.

In this embodiment, when the conductor film 5 is polished and removed after the resist sacrificial film 18 is polished in the step of FIG. 2B, the conductor film 5 is completely removed. In order to avoid dishing in the region I, the slurry and the polishing cloth used for polishing the conductive film 5 are adjusted so that the polishing rate ratio of the conductive film 5 to the interlayer insulating film 4 is in the range of 5 to 30. Optimize.

Further, in this embodiment, FIG.
In order to minimize the problem of polishing the interlayer insulating film when polishing the conductor film 5 covering the concave portion shown in FIG. 4C, the maximum inclination angle of the step portion 4A in the region II is 24 ° or less, preferably 20 °.
Restrict to the following. By limiting the maximum inclination angle of the step portion 4A in this manner, the polishing amount of the interlayer insulating film 4 in the polishing step of the conductor film 5 covering the concave portion of the interlayer insulating film 4 shown in FIGS. Can be minimized.

In this embodiment, in order to realize a polishing rate ratio of the conductive film 5 to the interlayer insulating film 4 of 5 to 30 described above, a colloidal silica polishing agent is provided with a polishing cloth having a SHORE-A hardness of 70 or less; For example, Rodale's trade name Supr
EmeRN-R or SupremeRN-H, or a combination of Fujifin's trade name Surfin018-3 or 018-3 slices is used. Each of the above polishing cloths is made of a foamed polyurethane sheet 20 having a structure in which a large number of substantially vertical pores 22 are formed on a base cloth 21 as shown in FIG. Is done. By using a sheet 20 having a SHORE-A hardness of 70 or less as a polishing cloth, polishing along the surface shape of the interlayer insulating film 4 becomes possible.

The maximum inclination angle of the step 4A is shown in FIG.
As shown in FIGS. 2A and 2B, the conductor film 5 is moved from the region II without any dishing in the memory cell region I in the configuration of FIG. For complete removal, as described above, it is preferable that the maximum inclination angle of the step portion 4A is set to 24 ° or less, preferably 20 ° or less. However, the data in FIG. 5A is based on the wiring pattern 3 having a height of 500 nm formed on the substrate 31 in the structure in FIG.
The BPSG film 33 formed by CVD on
The relationship between the wiring interval and the maximum reflow angle when reflowing at 0 ° C. for 20 minutes is shown.

More specifically, a 100 nm thick CVD-SiO ₂ film is formed on the structure shown in FIG.
Polysilicon or amorphous silicon films each having a thickness of 100 nm and doped with P at a concentration of 1.4 × 10 ²¹ cm ⁻³ are sequentially formed. Such a structure is referred to as a silica-based or alumina-based slurry ( For example, the maximum reflow angle that can be polished using Fujimi's PLANARLITE 6103 (silica base) so that the polysilicon film does not remain is in the range of 24 ° or less or 20 ° or less. Of these, the 2
The reflow angle of 0 ° or less is a condition under which the CVD-SiO ₂ film underlying the polysilicon film is not substantially polished, and the reflow angle of 24 ° or less is the condition of the CVD-SiO ₂ film.
_{The two} films are polished, but the underlying BPSG film 33 corresponds to a condition in which the BPSG film 33 is not substantially polished.

When the reflow angle is less than 20 °, a soft polishing cloth enters the unevenness. Therefore, when a normal flat polysilicon film is polished, the polysilicon film is applied to the underlying CVD-SiO ₂ film under the same conditions. It can be selectively polished and removed. In this case, the underlying CVD-SiO ₂ film is hardly polished. The selective removal (just polishing) of the polysilicon film is performed, for example, by using AVANT as a polishing apparatus.
Using I472, the rotation speed of the polishing head and the platen was set to 70 rpm, the polishing pressure was set to 9 psi, and the silica-based or alumina-based slurry was used at 100 rpm.
This is realized by stopping polishing after polishing for 30 seconds while supplying at a rate of cc / min. However, the above 3
Of the 0 seconds, 15 seconds is the time required for the polishing pressure to reach 9 psi, and the net polishing time at a polishing pressure of 9 psi is 15 seconds.

On the other hand, when the reflow angle is large, the underlying CVD-SiO ₂ film also needs to be polished to some extent. Therefore, the polishing time is extended to be longer than the above 30 seconds and about 45 seconds. When the polishing pressure is 9 psi (the net polishing time is 30 seconds) and the reflow angle is 24 ° or less, the CVD-SiO ₂ film functions as a reliable polishing stopper.

By performing the optimized CMP on the structure of FIG. 2A, the conductor film 5 was selectively removed by a single CMP step as shown in FIG. 2B. The structure is obtained. At this time, the conductor film 5 and the interlayer insulating film 4
, The dishing does not occur in the memory cell region I.

FIGS. 6A and 6B are a perspective view and a sectional view, respectively, showing a memory cell region of a DRAM formed by a CMP process with an optimized polishing rate ratio according to the present embodiment. As can be seen from FIGS. 6A and 6B, the surface of the memory cell region is flat and no dishing occurs.

Although the present invention has been described with reference to the preferred embodiments, the present invention is not limited to such embodiments, and various modifications and changes may be made within the spirit and scope of the appended claims.
Changes are possible.

[0045]

According to the first, sixth, and seventh aspects of the present invention, the sacrificial film formed on the underlying structure covered with the polishing stopper layer and having a thickness that varies depending on the location is formed by the method. In a method of manufacturing a semiconductor device, particularly a semiconductor memory integrated circuit device, including a step of selectively removing the underlayer structure by a chemical mechanical polishing method while leaving an underlayer structure, in the chemical mechanical polishing, the sacrificial film of the polishing stopper layer with respect to the polishing stopper layer is removed. After the polishing stopper layer is exposed in the first region where the thickness of the sacrificial film is minimum, the thickness of the sacrificial film is maximized. The second
By setting such that the time required for the sacrificial film to be completely polished and removed in the region is substantially equal to or greater than the time required for the sacrificial film, a number of openings are provided in the underlying structure, and the thickness of the sacrificial film is increased. Even in a region with a small thickness, or in a region where such an opening does not exist and the thickness of the sacrificial film is large, polishing can be performed uniformly, and the flatness of the obtained structure is improved.

According to the second, third, eighth and ninth aspects of the present invention, a sacrificial film which is formed on a base structure made of an insulating film covered with a conductive film and whose thickness varies depending on a location. To
Along with the conductor film, in a method of manufacturing a semiconductor device including a step of selectively removing the insulating film by a chemical mechanical polishing method, using a resist film as the sacrificial film, the resist film and the conductor film, A chemical mechanical polishing step of sequentially polishing and removing the same slurry is performed so that a polishing rate ratio of the conductor film to the insulating film falls within a range of 5 to 30. Without dishing in thin parts,
The sacrificial film and the conductor film can be completely removed.

According to the fourth and fifth aspects of the present invention, the first region having a plurality of openings and the second region having irregularities are continuously formed on the insulating film. A conductor film formed so as to cover the surface shape of the insulating film,
In a method of manufacturing a semiconductor device including a chemical mechanical polishing step of selectively removing the insulating film by a chemical mechanical polishing method, the chemical mechanical polishing step may be performed when a polishing rate ratio of the conductor film to the insulating film is 5%. -30, and the unevenness of the second region is adjusted to a maximum inclination angle of 2
By forming the conductive film at 4 ° or less, the conductive film can be completely removed without causing dishing in the first region where the plurality of openings are formed in the insulating film. .

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a manufacturing process of a DRAM according to a first embodiment of the present invention.

FIG. 2 is a view illustrating a manufacturing process of a DRAM according to a second embodiment of the present invention;

FIG. 3 is a diagram showing a part of the process of FIG. 2;

FIG. 4 is a view showing a structure of a polishing cloth.

FIG. 5 is a diagram illustrating a preferable maximum inclination angle of a step.

FIG. 6 is a diagram showing a part of the structure of a DRAM formed in a second embodiment of the present invention.

FIG. 7 is a diagram showing a structure of a conventional DRAM.

FIG. 8 is a diagram illustrating a step of forming the structure of FIG. 7;

FIG. 9 is a diagram illustrating a problem of a conventional process.

FIG. 10 is a diagram for explaining a conventional process that solves the problem of FIG. 9;

FIG. 11 is another diagram for explaining a conventional process that solves the problem of FIG. 9;

FIG. 12 is a diagram showing a part of the structure of a DRAM to which the present invention is applied.

FIG. 13 is a diagram illustrating a problem that occurs in the structure of FIG. 12;

FIG. 14 is a diagram illustrating another problem that occurs in the structure of FIG.

[Explanation of symbols]

1,11 substrate 1A field oxide film 1B active region 1D _1, 1D _2, 1D ₃ diffusion regions 2 _{1, 2} 2, 2 ₃ gate patterns 3 _1, 3 ₂ self-aligned oxide layer 4, 12 interlayer insulating film 4 _1, 4 _2, 4 _3, 12A contact hole 4A stepped portions 5,13 conductive film 5 _1, 5 _2, 5 ₃ conductor sleeve 6 _1, 6 _2, 6 ₃ dielectric film _71, 7 _2, 7 ₃ conductor plugs 8,14 , 18 Sacrificial film 12x Abrasive 20 Polishing cloth 21 Base cloth 22 Pores 32 Conductor pattern 33 Reflow film

Claims (9)

[Claims] 1. A method of manufacturing a semiconductor device, comprising the step of selectively removing, by a chemical mechanical polishing method, a sacrificial film formed on a base structure covered with a polishing stopper layer and having a thickness that varies depending on a location. In the chemical mechanical polishing, the polishing selection ratio of the sacrificial film to the polishing stopper layer, the time required to polish and remove the polishing stopper layer, the first film thickness of the sacrificial film is the first After the polishing stopper layer is exposed in the region,
In the second region where the thickness of the sacrificial film is the maximum, the time is set so as to be substantially equal to or greater than the time required until the sacrificial film is completely polished and removed. A method for manufacturing a semiconductor device. 2. A sacrifice film formed on an underlying structure made of an insulating film covered with a conductive film and having a thickness that varies depending on a location is selectively formed together with the conductive film while leaving the insulating film.
A method of manufacturing a semiconductor device including a step of removing by a chemical mechanical polishing method, comprising a step of using a resist film as the sacrificial film, and sequentially polishing and removing the resist film and the conductor film by the same slurry. The method of manufacturing a semiconductor device, wherein the chemical mechanical polishing step is performed such that a polishing rate ratio of the conductor film to the insulating film falls within a range of 5 to 30. 3. The underlayer structure includes a first region in which the thickness of the sacrificial film is minimum and another second region. In the underlayer structure, the first region has a plurality of openings. 3. The method according to claim 2, wherein a step portion is formed in the second region, and a maximum inclination angle of the step portion is 24 ° or less. 4. A first region having a plurality of openings formed on the insulating film and a second region having irregularities are continuously covered along the surface shape of the insulating film. In a method of manufacturing a semiconductor device including a chemical mechanical polishing step of selectively removing a formed conductive film from the insulating film by a chemical mechanical polishing method, wherein the chemical mechanical polishing step comprises: A method for manufacturing a semiconductor device, wherein the method is performed so that a film polishing rate ratio falls within a range of 5 to 30. 5. The method according to claim 4, wherein the unevenness of the second region has a maximum inclination angle of 24 ° or less. 6. A method of manufacturing a semiconductor device including a plurality of memory cell transistors in a memory cell region on a substrate, comprising: forming an interlayer insulating film on the substrate so as to cover the plurality of memory cell transistors; Forming a plurality of contact holes corresponding to the plurality of memory cell transistors in an insulating film; and forming the plurality of contact holes in the memory cell region on the interlayer insulating film so as to include the plurality of contact holes. To include a region other than the memory cell region of the insulating film,
Depositing a conductive film with a substantially uniform thickness; sacrificial film on the conductive film, filling the plurality of contact holes in the memory cell region, and forming a region other than the memory cell region. And a chemical-mechanical polishing step of selectively polishing and removing the sacrificial film by a chemical-mechanical polishing method while leaving the conductor film. The polishing selectivity of the sacrificial film with respect to the conductor film, the time required to polish and remove the conductor film, after the conductor film is exposed in the memory cell region, the thickness of the sacrificial film other than the memory cell region Wherein the sacrificial film is set to be substantially equal to or greater than the time required for the sacrificial film to be completely polished and removed in the region where the maximum value is obtained. . 7. In the chemical mechanical polishing step, the sacrificial film is polished and removed by a first polishing agent, and the conductor film is polished by a second different polishing agent after the removal of the sacrificial film. 7. The method according to claim 6, further comprising a second chemical mechanical polishing step for removing. 8. A method for manufacturing a semiconductor device including a plurality of memory cell transistors in a memory cell region on a substrate, comprising: forming an interlayer insulating film on the substrate so as to cover the plurality of memory cell transistors; Forming a plurality of contact holes corresponding to the plurality of memory cell transistors in an insulating film; and forming the plurality of contact holes in the memory cell region on the interlayer insulating film so as to include the plurality of contact holes. To include a region other than the memory cell region of the insulating film,
Depositing a conductive film with a substantially uniform thickness; sacrificial film on the conductive film, filling the plurality of contact holes in the memory cell region, and forming a region other than the memory cell region. And a chemical mechanical polishing step of selectively polishing and removing the sacrificial film together with the conductor film with respect to the interlayer insulating film by a chemical mechanical polishing method. Depositing a resist film as the sacrificial film; and performing the chemical mechanical polishing step, the resist film and the conductor film are polished using the same slurry, and a polishing rate ratio of the conductor film to the insulating film is adjusted. Is performed so as to fall within the range of 5 to 30. 9. The interlayer insulating film includes a first region in which the thickness of the sacrificial film is minimum, and a second region different from the first region. 9. The semiconductor device according to claim 8, wherein a plurality of openings are formed in the first region, and irregularities are formed in the second region, and a maximum inclination angle of the irregularities is 24 ° or less. Production method.