JPH1019981A - Semiconductor device and its inspection method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the reliability of product inspection and imperfect product detection ratio. SOLUTION: An output signal of an oscillation circuit is inputted in an 2N times frequency demultiplier circuit, i.e., F/F2, 3 and its output is connected with a lead 10. In an inspection method by adding an oscillation element of a semiconductor integrated circuit of constitution having a reset input of the frequency demultiplier circuit in a lead 9, logic test function of an LSI tester is used, test period RATE of the LSI tester is set to be 2N times the oscillation period T of an oscillation element, strobe is set to be in the range of T-N*T where N is at least 2, and logic test is performed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and an inspection method therefor, and more particularly to a semiconductor device having a circuit element and a frequency dividing circuit which constitute a part of an oscillation circuit on a semiconductor substrate, and a logic test of the circuit element The inspection method for performing the above.

[0002]

2. Description of the Related Art Referring to a circuit diagram of FIG. 3 showing a conventional semiconductor device, a semiconductor substrate 21 includes a part 15 of an oscillation circuit and a logic circuit (operating using an oscillation output of the oscillation circuit as a clock signal). (Not shown). A crystal oscillator, a capacitor, and the like, which constitute the oscillation circuit, are external circuit elements, and necessary wiring is provided through leads 18 and 19. A part 15 of the oscillation circuit includes an inverter 16 that operates as a feedback element, and a buffer 17 for extracting an output of the inverter 16. The output 20 of the inverter 17 is supplied to an internal logic circuit (not shown).

As a test of the oscillation function of such a semiconductor substrate, a clock signal is input to a lead 18 and an output of an inverter 16 is obtained from a lead 19 by an LSI tester. The output of the lead 19 has been compared with an expected value set in advance in the LSI tester to make a pass / fail judgment. That is, here, the pass / fail judgment of the oscillation circuit is estimated by comparing the inverting function of the inverter 16 with the expected value.

[0004]

However, such a function test of only one inverter 16 of one circuit element is a test of only one circuit element constituting an oscillation circuit. , The trust was poor.

Further, the conventional LIS tester cannot measure the oscillation frequency because a frequency measuring device for measuring the oscillation frequency of the oscillation circuit is not added. Even if the test is performed by oscillating the oscillation circuit, the oscillation circuit is free running, and therefore cannot be synchronized with the LSI tester. The function check test of the circuit could not be performed normally. In the free running state of the oscillation circuit, L
There is a problem that synchronization with the SI tester cannot be obtained. For this reason, it is an essential requirement that the oscillation circuit operation test for improving the reliability and the defect detection rate can be normally performed in the future.

[0006] In view of the above problems, an object of the present invention is to provide a semiconductor device and an inspection method thereof that solve the following problems. (1) A function test of a circuit element in a semiconductor substrate, which constitutes a part of the oscillation circuit, is performed under the condition that the oscillation circuit is oscillated. (2) Improve the reliability of the oscillation circuit and improve the defect detection rate.

[0007]

According to a first aspect of the present invention, there is provided:
In a semiconductor device, a circuit element forming a part of an oscillation circuit, a buffer for extracting an output of the circuit element, and a logic circuit operating the output of the buffer as a clock signal are integrated on a semiconductor substrate. Is provided on the semiconductor substrate, and a lead for leading out the output divided by the frequency dividing circuit to the outside is provided.

According to a second configuration of the present invention, an external circuit element constituting an oscillation circuit is connected to a circuit element in a semiconductor substrate constituting a part of the oscillation circuit, and an output of the oscillation circuit is buffered. To a frequency dividing circuit of 2N (N is an integer equal to or greater than 2), derives the frequency divided output to a lead, supplies a reset signal to the frequency dividing circuit, and supplies a circuit element in the semiconductor substrate. In a semiconductor device inspection method for performing a logic test, a logic test function of an LSI tester is used,
The test cycle of the LSI tester is set to 2N times the oscillation cycle T of the oscillation circuit, and the strobe is set within a range of T to N × T to perform a logic test.

[0009]

FIG. 1 shows an embodiment of the present invention.
Referring to the timing chart of FIG. 2 showing the operation waveform,
The semiconductor substrate 22 of this semiconductor device includes a part 6 of the oscillation circuit.
In addition, flip-flops connected in two stages (hereinafter F /
F, abbreviated as F), a lead 9 for externally inputting a reset signal to the F / Fs 2, 3, and a lead 10 for leading the output 2 of the F / F 3 to the outside.

A part 6 of the oscillating circuit includes a feedback inverter 4 and a buffer 5 composed of an inverter for taking out the output of the inverter 4. To form an oscillation circuit, external capacitors 12,
One end of the capacitor 13 is connected, the other end of each of the capacitors 12 and 13 is grounded, and an external crystal oscillator 11 is connected between the leads 7 and 8. In this state, when a predetermined bias voltage is applied to the semiconductor substrate 22, a free-running oscillation state is established. Next, an LSI tester is prepared for the leads 9 and 10.

The output terminal 1 of the buffer 5 is a terminal for supplying a clock signal to a logic circuit in the semiconductor substrate 22 (not shown). Each of the F / Fs 2 and 3 of the frequency dividing circuit is a D-type flip-flop and is set by a reset signal. In each case, the inverted output is connected to the D input, so that the inverted input is alternately performed by the clock input (c) of the terminal 1. In other words, the oscillation frequency is reduced by half at F / F2,
Even in the F / F3, the input frequency is halved. Therefore, in the two-stage F / F2 and 3, the frequency is divided by 4 and the oscillation frequency is reduced to 1/4.
And output from the lead 10. Here, when the frequency dividing circuit enters the full count state, the ISL tester inputs a reset signal to the lead 9 and resets the F / Fs 2 and 3 to return to the initial state.

Here, as shown in FIG.
, The test period (RATE) of the LSI tester is set to 8 times τ, and the strobe is set to 2τ to 4τ.

In the actual measurement, first, necessary circuit elements are connected to the leads 7 and 8 of the oscillator circuit, and the same oscillation as in normal use is caused. The measurement cycle of the LSI tester is set to, for example, 4 × 8τ, which is the oscillation cycle 2τ of the oscillator to be measured, and a reset signal such that the fall of the reset signal becomes the start of the measurement cycle is input to the lead 9 from the LSI tester.
The signal obtained by dividing the output signal from the buffer 5 by 4 has a HI interval of 4τ and a maximum phase shift of 2τ, so the strobe point is set between 2τ and 4τ, and the expected value is set to HI.
Thus, a function test can be performed.

According to this embodiment, the frequency division by 4 is performed in the F / Fs 2 and 3. However, the invention is not limited to this. For example, in a three-stage F / F, a frequency-divided signal of 8 is obtained. Accordingly, the test can be performed by increasing the test period RATE of the LSI tester.

[0015]

As described above, according to the present invention, since the frequency dividing circuit is provided in the semiconductor substrate, inspection can be performed by a logic test such as an LSI tester. And an oscillation frequency test can be performed, thereby improving the reliability of product inspection and improving the product defect detection rate.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a timing chart showing an operation of one embodiment.

FIG. 3 is a circuit diagram showing a conventional semiconductor substrate.

[Explanation of symbols]

 1,20 terminal 2,3 flip-flop 4,16 inverter 5,17 buffer 6,15 part of oscillation circuit 7,8,9,10,18,19 lead 11 crystal oscillator 12,13 capacitor 21,22 semiconductor substrate

Claims (2)

[Claims] A circuit element constituting a part of an oscillation circuit;
In a semiconductor device in which a buffer for extracting the output of the circuit element and a logic circuit for operating the output of the buffer as a clock signal are integrated on a semiconductor substrate, a frequency divider for dividing the output of the buffer is provided on the semiconductor substrate. A semiconductor device provided with a lead for providing an output divided by the frequency dividing circuit to the outside. 2. An external circuit element constituting an oscillation circuit,
The circuit is connected to a circuit element in a semiconductor substrate which constitutes a part of the oscillation circuit, and the output of the oscillation circuit is connected to a 2N
(N is an integer of 2 or more) is input to a frequency dividing circuit, a frequency divided output is led to a lead, a reset signal is supplied to the frequency dividing circuit, and a logic test of a circuit element in the semiconductor substrate is performed. In the semiconductor device inspection method to be performed, the test cycle of the LSI tester is set to 2N times the oscillation cycle T of the oscillation circuit using the logic test function of the LSI tester, and the strobe is set within a range of T to N × T. A method for testing a semiconductor device, comprising setting and performing a logic test.