JPH10199285A - Sample holding circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a sample holding circuit by which the leakage of an input signal to an output signal through a parasitic capacitance in a holding mode is suppressed, while the high operation speed is maintained and a stable potential can be outputted consistently. SOLUTION: In a sampling mode, a 1st fixed voltage by which a 1st conductivity type 7th transistor Q8 is cut off is set by a voltage superposing means R3, R4 with the switching of the collector currents of a pair of 1st conductivity type 3rd common emitter differential transistors Q10 and Q11 and, in a holding mode, a 2nd fixed voltage by which the voltages between the bases and emitters of a pair of 1st common emitter differential transistors are biased in the reverse bias direction is set by the voltage superposing means R3, R4 in the same way.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sample-and-hold circuit, and more particularly, to a sample-and-hold circuit using a bipolar transistor which is required to operate at high speed. To the output signal through the
The present invention relates to a sample and hold circuit that can always output a stable potential.

[0002]

2. Description of the Related Art Heretofore, as a sample-and-hold circuit using a bipolar transistor element, there has been known a circuit in which a voltage follower circuit is formed by a pair of common-emitter differential transistors, and the common emitter current is intermittently intermittent. FIG. 3 shows a circuit diagram of this conventional sample and hold circuit as a first conventional example.

In FIG. 3, when a sampling signal SAMP supplied to a sampling terminal is at "H" level, N
In the common emitter amplifying circuit constituted by PN transistors Q5 and Q6, the NPN transistor Q6 is selected, and the potential of the output signal OUT is determined by the voltage follower constituted by the PNP transistors Q1, Q2 and the NPN transistors Q3, Q4.

[0004] The output signal OU is supplied to the capacitor C1.
Charge is charged or discharged so that the potential of T follows the potential of the input signal IN. When the holding signal HLD supplied to the holding terminal becomes “H” level and the NPN transistor Q5 is selected, the PN
P transistor Q1, Q2 and NPN transistor Q
3, Q4 is turned off, and the potential of the output signal OUT is kept constant by the capacitor C1 holding the charge amount.

C2 and C3 indicate base-emitter junction capacitances (hereinafter referred to as parasitic capacitances), which are not circuit components of the NPN transistors Q3 and Q4, respectively. When the NPN transistors Q3 and Q4 are on, the voltage between the base and the emitter is constant, so that the parasitic capacitance does not affect the circuit operation. However, in the holding mode, the NPN transistors Q3 and Q3
When the potential of the input signal IN changes while the switch 4 is in the off state, the charge is discharged or discharged from the capacitor C1 via the parasitic capacitances C2 and C3. At this time, since the capacitor C1 is grounded, a change in the charge amount of the capacitor C1 results in a change in the potential of the output signal OUT, which appears as a signal leak during holding.

The input signal I in the holding mode is
A phenomenon in which a change in the potential of N appears as a leak to the potential of the output signal OUT will be described with reference to the drawings. FIG. 5 shows respective waveforms of the potential of the input signal IN and the potential of the output signal OUT affected by the change in the direction in which the potential of the input signal IN increases in the holding mode. As shown in the figure, the rise of the potential of the input signal IN is caused by
By injecting charge into the capacitor C1 via the parasitic capacitances C2 and C3, a change in the potential of the input signal IN appears as leakage to the potential of the output signal OUT.

FIG. 6 shows the potential of the input signal IN when the potential of the input signal IN changes to a lower direction in the holding mode, and the output signal OUT affected by the potential.
3 shows respective waveforms of the electric potential of FIG. In this case, the drop in the potential of the input signal IN causes the charge to be extracted from the capacitor C1 via the parasitic capacitances C2 and C3, and the change in the potential of the input signal IN appears as a leak to the potential of the output signal OUT. .

When the capacitance of the capacitor C1 is increased, signal leakage to the output signal OUT is reduced, but affects the operation speed of the circuit. Therefore, this phenomenon does not cause a fatal drawback in a sample-and-hold circuit in which the capacity of the capacitor C1 can be set relatively large and does not require a high speed, but requires a very high-speed operation. This is a fatal drawback in the sample and hold circuit.

As another prior art, FIG. 4 shows a circuit diagram of a second conventional sample and hold circuit. As shown in the figure, the sample and hold circuit of the second conventional example has N
The output signal OUT is fed back to the base of the NPN transistor Q4 via the emitter follower of the PN transistor Q7.

In the first conventional example (FIG. 3), in order to supply the output signal OUT to the next stage, it is necessary to supply the output signal OUT through a buffer circuit having a high input impedance and a small offset voltage. In the second conventional example, the NPN transistor Q
7 plays its role and the NPN transistor Q7
Is included in the loop, there is no need to consider the effect of the offset.

The leakage of the input signal IN to the output signal OUT in the second conventional example is slightly different from that in the first conventional example. That is, with respect to the change in the direction in which the potential of the input signal IN rises, the charge moving via the parasitic capacitances C2 and C3 only flows into the output terminal (OUT) via the path i41 shown in FIG. It does not affect the charge of the capacitor C1. On the other hand, when the potential of the input signal IN is changed in a direction in which the potential of the input signal IN decreases, the voltage between the base and the emitter of the NPN transistor Q4 is increased. From the capacitor C1. As described above, in the sample and hold circuit of the second conventional example, the above-described leakage phenomenon appears only in the direction in which the potential of the input signal IN decreases.

[0012]

As described above, in the above-mentioned conventional sample-and-hold circuit in which the common emitter current of the common-emitter differential amplifier circuit is interrupted, the potential change of the input signal IN in the holding mode is output. The signal OUT appears as leakage to the potential, and the output signal OUT
Can be suppressed by increasing the capacitance of the capacitor C1, but this has a fatal drawback in a sample-and-hold circuit that requires a high-speed operation.

The present invention has been made in view of the above-mentioned conventional circumstances, and in a sample and hold circuit using a bipolar transistor which is required to operate at a high speed, an input signal in a holding mode can be obtained without impairing the speed. Suppress the leakage to the output signal through the parasitic capacitance,
It is an object of the present invention to provide a sample and hold circuit that can always output a stable potential.

Another object of the present invention is to prevent leakage of an input signal to an output signal through a parasitic capacitance in the holding mode even when the storage capacitance is reduced to the minimum for high-speed operation. An object of the present invention is to provide a sample and hold circuit capable of suppressing an error.

[0015]

In order to solve the above problems, a sample and hold circuit according to the present invention comprises a first transistor of a first conductivity type to which an input signal of the sample and hold circuit is applied to a base; A first emitter common differential transistor pair including a first conductivity type second transistor to which an output signal of the sample and hold circuit is fed back, and a collector connected to the collector of the first conductivity type second transistor; A second transistor of a second conductivity type serving as a current source load of the second transistor of the first conductivity type, and a collector connected to an emitter of the first transistor of the second conductivity type, and a base in a holding mode. A third transistor of a first conductivity type to which a signal shown is applied, and a collector connected to a common emitter of the first emitter common differential transistor pair. A second common emitter differential transistor pair including a first conductive type fourth transistor connected to the base and receiving a signal indicating the sampling mode, and one end having the first conductive type second transistor. And a voltage follower circuit that receives a collector output of the second transistor of the first conductivity type and obtains an output signal of the sample and hold circuit. A fifth transistor of a first conductivity type to which a signal indicating the holding mode is applied to a base; and a sixth transistor of a first conductivity type to which a signal indicating the sampling mode is applied to a base. A third common emitter differential transistor pair of a first conductivity type, the emitter being the first common emitter differential transistor. A seventh transistor of the first conductivity type connected to the common emitter of the pair of transistors, and a first fixed voltage or a second fixed voltage superimposed on the potential of the output terminal of the sample and hold circuit. Voltage superimposing means for applying to the base of a seventh transistor, wherein the voltage superimposing means applies a first fixed voltage at which the seventh transistor of the first conductivity type cuts off in the sampling mode to the first fixed voltage in the holding mode. The second fixed voltage at which the base-emitter voltage of the one common emitter differential transistor pair is biased in the reverse bias direction is switched by the collector current of the first conductive type third emitter common differential transistor pair. , Respectively.

Further, the sample and hold circuit of the present invention comprises:
An eighth transistor of a first conductivity type to which a signal from the voltage follower circuit is applied to a base of the voltage superimposing means, one end of which is the emitter of the eighth transistor of the first conductivity type, and the other end of which is the first transistor. A first resistance element connected to the collector of the fifth transistor of the conductivity type, one end connected to the other end of the first resistance element, and the other end connected to the seventh of the first conductivity type;
And second resistance elements respectively connected to the bases of the transistors.

The sample-and-hold circuit of the present invention is a sample-and-hold circuit of a type in which the common emitter current of the common-emitter differential transistor pair is turned on and off. Increases the output voltage of the voltage superimposing means to a first fixed voltage that cuts off, and in a holding mode, a first conductive type first emitter common differential transistor by a first conductive type seventh transistor. The output voltage of the voltage superimposing means is set to the second fixed voltage so as to pull up the pair of common emitters.

As described above, by pulling up the common emitter of the first conductive type first emitter common differential transistor pair by the first conductive type seventh transistor in the holding mode, the base potential of the input transistor fluctuates. The effect on the output signal can be reduced, and a stable potential can always be output even when the input signal changes in the holding mode without impairing the speed in a sample-and-hold circuit that requires high-speed operation. .

Further, since the change in the potential of the input signal does not affect the charge of the storage capacitor element and does not affect the output potential, even if the storage capacitor is reduced to the minimum for high-speed operation, the change in the holding mode can be prevented. The leakage of the input signal to the output signal via the parasitic capacitance can be suppressed, and the error of the holding signal can be suppressed.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of a sample and hold circuit of the present invention will be described in detail in the order of [Embodiment 1] and [Embodiment 2] with reference to the drawings.

[Embodiment 1] FIG. 1 shows Embodiment 1 of the present invention.
FIG. 2 is a configuration diagram of a sample hold circuit according to FIG. In the figure, the same reference numerals are given to the same parts as those in FIG. 4 (second conventional example).

In FIG. 1, the sample-and-hold circuit of this embodiment includes a first pair of common emitter differential NPN transistors Q3 and Q4, resistors R1 and R2, PNP transistors Q1 and Q2, a second common emitter differential NPN transistor. Pairs Q5 and Q6, current source I1, storage capacitor C
1. NPN transistor Q7, current source I2, diodes Q12 and Q13, current source I4, third emitter common differential NPN transistor pair Q10 and Q11, current source I
3, NPN transistor Q8, resistors R3 and R4, NP
It comprises an N-transistor Q9. Note that C2 in the figure is a base-emitter junction capacitance (hereinafter referred to as a parasitic capacitance) which is not a component on the circuit of the NPN transistor Q3. Vcc is a power supply, and GND is a ground potential.

The first common emitter differential transistor pair includes NPN transistors Q3 and Q4.
The input signal IN is connected to the base of the transistor Q3, the collector of the PNP transistor Q1 is connected to the collector, the output signal OUT is connected to the base of the NPN transistor Q4, and the collector of the PNP transistor Q2 is connected to the collector. NPN transistor Q3
The collector of the NPN transistor Q6 is connected to the common emitter of the transistor Q4 and the common emitter of the transistor Q4.

The resistors R1 and R2 and the PNP transistors Q1 and Q2 form a current mirror. The bases of the PNP transistors Q1 and Q2 are connected to each other. The base of the PNP transistor Q1 is connected to the collector. , The emitter of PNP transistor Q1 is connected to a power supply potential Vcc via a resistor R1, and the emitter of PNP transistor Q2 is connected to a power supply potential Vcc via a resistor R2.

The second common emitter differential transistor pair includes NPN transistors Q5 and Q6.
The holding signal HLD is connected to the base of the PN transistor Q5, the emitter of the PNP transistor Q2 is connected to the collector, and the NPN transistor Q2 is connected to the collector.
6 has a sampling signal SAMP at its base and a first emitter-common differential NPN transistor pair Q3 at its collector.
And Q4 are connected to each other.
One end of a current source I1 is connected to a common emitter of the PN transistors Q5 and Q6. The other end of the current source I1 is connected to the ground potential GND.

The storage capacitor C1 is connected between the collector of the NPN transistor Q4 and the ground potential GND. The base of the NPN transistor Q7 is NPN
The collector of the transistor Q4 is connected to the power supply potential V.
cc, and the emitter is connected to one end of the current source I2. The diodes Q12 and Q13 are connected in series, the anode of the diode Q12 is connected to one end of the current source I4, and the cathode side of the diode Q13 is connected to the output terminal (OUT). The other end of the current source I2 is at the ground potential GND, and the other end of the current source I4 is at the power supply potential Vcc.
Connected to each other.

The third common emitter differential transistor pair includes NPN transistors Q10 and Q11. A holding signal HLD is connected to the base of the NPN transistor Q10, and a connection point between the resistors R3 and R4 is connected to the collector. , The sampling signal SAMP is connected to the base of the NPN transistor Q11, the base of the NPN transistor Q8 and the other end of the resistor R4 are connected to the collector, and one end of the current source I3 is connected to the common emitter of the NPN transistors Q10 and Q11. It is connected. The other end of the current source I3 is connected to the ground potential GND.

The emitter of the NPN transistor Q8 is connected to the common emitter of the first emitter common differential NPN transistor pair Q3 and Q4, the collector is connected to the power supply potential Vcc, and the base is connected to the collector of the NPN transistor Q11. Have been. The power supply potential Vcc is connected to the collector of the NPN transistor Q9, one end of the resistor R3 is connected to the emitter, and the connection point between the current source I4 and the diode Q12 is connected to the base. Furthermore,
The other end of the resistor R3 is connected to one end of the resistor R4.
Is connected to the base of NPN transistor Q8.

The voltage VX across the resistors R3 and R4 is applied to a third common emitter differential NPN transistor pair Q1.
In the sampling mode, a first fixed voltage at which the NPN transistor Q8 is cut off is set by the collector currents of 0 and Q11. In the holding mode, the base-emitter of the first emitter common differential NPN transistor pair Q3 and Q4 is set. A second fixed voltage is set such that the intermediate voltage is biased in a more reverse bias direction.

That is, in the sampling mode, NPN
The voltage VX across the resistors R3 and R4 is increased to a first fixed voltage so that the transistor Q8 is cut off. In the holding mode, the voltage VX across the resistors R3 and R4 is set to the second fixed voltage so that the emitter (node A1) of the first emitter common differential NPN transistor pair Q3 and Q4 is pulled up by the NPN transistor Q8. I do.

In both the sampling mode and the holding mode, the base potential (node B1) of the NPN transistor Q8 must follow the potential of the output signal OUT. Therefore, in the present embodiment, a feedback circuit from the output signal OUT is formed by the NPN transistor Q9, and the voltage VX across the resistors R3 and R4 is superimposed on the feedback voltage, and the base of the NPN transistor Q8 (node B1)
Potential.

The switching between the voltage VX across the resistors R3 and R4 to be the first or second fixed voltage is performed by the third pair of emitter-common differential NPN transistors Q10 and Q11. That is, in the sampling mode, the NPN transistor Q11 is turned on, the potential V (B1) of the node B1 is Vf, the forward voltage of the diode, the potential of the output signal OUT is V (OUT), and the current of the current source I3 is i.
When the number is 3, the following equation is obtained. V (B1) = V (OUT) + Vf− (R3 + R4) × i
3. In the holding mode, the NPN transistor Q11 is turned off, no current flows through the resistor R4, and the potential V (B1) of the node B1 is expressed by the following equation. V (B1) = V (OUT) + Vf−R3 × i3

In order for the sample and hold circuit of this embodiment to operate properly, the potential V (B1) of the node B1 must be
About ± 200 [mV] with respect to the output potential V (OUT),
That is, it is necessary to set such that it is low in the sampling mode and high in the holding mode. Therefore, the condition is the following inequality. At the time of sampling mode: (R3 + R4) × i3> Vf
+200 [mV] In holding mode: R3 × i3 <Vf
-200 [mV]

The resistances R3 and R3 satisfying these two conditional expressions
The resistance value of 4 is given by the following inequality. R3 <(Vf-200 [mV]) / i3 R4> 400 [mV] / i3 Note that switching of the NPN transistors Q5 and Q6 and N3
It is desirable that the switching of the PN transistors Q10 and Q11 be performed at the same time, and it is necessary to design these transistors with the same elements and with the same switching speed.

In the sample and hold circuit of the present embodiment, when the potential of the input signal IN changes in the falling direction in the holding mode, charge is extracted from the node A1 via the parasitic capacitance C2. , NPN than the base potential of NPN transistor Q4.
Since the base potential of transistor Q8 is high, most of this charge will be supplied by NPN transistor Q8. Therefore, the change in the potential of the input signal IN does not affect the charge of the capacitor C1 and does not affect the output potential V (OUT). As a result, without compromising speed,
In the holding mode, the leakage of the input signal IN to the output signal OUT via the parasitic capacitance can be suppressed, and a sample and hold circuit that can always output a stable potential can be realized.

[Embodiment 2] FIG. 2 shows Embodiment 2 of the present invention.
FIG. 2 is a configuration diagram of a sample hold circuit according to FIG. In the figure, the same reference numerals are given to the portions that overlap with FIG. 1 (Embodiment 1).

In FIG. 2, the sample-and-hold circuit of this embodiment includes a first pair of common emitter differential NPN transistors Q3 and Q4, (resistors R1 and R2, PNP transistors Q1 and Q2), resistors R5 and R6, and a second , An emitter common differential NPN transistor pair Q5 and Q6, a current source I1, a storage capacitor C1, an NPN transistor Q7,
Current source I2, diode Q12, third emitter-common differential NPN transistor pair Q10 and Q11, current source I
3, NPN transistor Q8, resistors R3 and R4, NP
It comprises an N-transistor Q9. Vc
c is a power supply, and GND is a ground potential.

The first differential pair of common emitter transistors includes NPN transistors Q3 and Q4.
The input signal IN is connected to the base of the transistor Q3, the ideal current source of the current mirror is connected to the collector, and the output signal OU is connected to the base of the NPN transistor Q4.
T is connected to an ideal current source of a current mirror at the collector, and further, NPN transistors Q3 and Q4
Is connected to the collector of the NPN transistor Q6.

The resistors R1 and R2 and the PNP transistors Q1 and Q2 constitute a current mirror, which is specifically the same as that of the first embodiment. Therefore, FIG. 2 shows a symbol of an ideal current source. .

The second common emitter differential transistor pair includes NPN transistors Q5 and Q6.
The holding signal HLD is connected to the base of the PN transistor Q5, the ideal current source of the current mirror is connected to the collector, the sampling signal SAMP is connected to the base of the NPN transistor Q6, and the first emitter common differential NPN is connected to the collector. The common emitters of the transistor pairs Q3 and Q4 are connected to one another, and one end of the current source I1 is connected to the common emitters of the NPN transistors Q5 and Q6. The other end of the current source I1 is connected to the ground potential G.
Connected to ND.

The storage capacitor C1 is connected between the collector of the NPN transistor Q4 and the ground potential GND. The base of the NPN transistor Q7 is NPN
The collector of the transistor Q4 is connected to the power supply potential V.
cc, and the emitter is connected to the anode of the diode Q12, respectively. The cathode of the diode Q12 is connected to one end of the current source I2 and the output terminal (OUT). Note that the other end of the current source I2 is connected to the ground potential GND.

The third common emitter-differential transistor pair includes NPN transistors Q10 and Q11. The holding signal HLD is connected to the base of the NPN transistor Q10, and the connection point between the resistors R3 and R4 is connected to the collector. , The sampling signal SAMP is connected to the base of the NPN transistor Q11, the base of the NPN transistor Q8 and the other end of the resistor R4 are connected to the collector, and one end of the current source I3 is connected to the common emitter of the NPN transistors Q10 and Q11. Have been. The other end of the current source I3 is connected to the ground potential GND.

The emitter of the NPN transistor Q8 is connected to the common emitter of the first emitter common differential NPN transistor pair Q3 and Q4, the collector is connected to the power supply potential Vcc, and the base is connected to the collector of the NPN transistor Q11. Have been. The collector of NPN transistor Q9 is connected to power supply potential Vcc, the emitter is connected to one end of resistor R3, and the base is connected to the base of NPN transistor Q7. Further, the resistance R
3 is connected to one end of a resistor R4, and the other end of the resistor R4 is connected to the base of an NPN transistor Q8.

As described above, the configuration of the sample and hold circuit of the present embodiment is different from that of the first embodiment in that the output signal OUT
Of the diodes Q12 and Q13 for raising the potential of the current source by 2 Vf, is replaced by an emitter follower using an NPN transistor Q7.
Can be omitted. That is, since the potential of the output signal OUT is raised by 2 Vf using the Vf of the NPN transistor Q7, the same function as that of the sample and hold circuit of the first embodiment (FIG. 1) is realized by one diode Q12. .

However, since droop occurs due to the pace current of the NPN transistor Q9, it is not suitable for applications where the hold time is long or where the allowable value of droop is small.

When a large amount of current is supplied from the current source I1 for high-speed operation, ringing occurs. In order to prevent this ringing, in the sample and hold circuit of the present embodiment, the resistors R5 and R5 are connected to the emitters of the first emitter common differential NPN transistor pair Q3 and Q4, respectively.
6 is connected, the other ends of the resistors R5 and R6 are connected to form a node A2, and the node A2 is connected to the emitter of the NPN transistor Q8, but there is no change in the operation as a sample and hold circuit. .

[0047]

As described above, according to the sample and hold circuit of the present invention, the first mode is provided in the holding mode.
By pulling up the common emitter of the conductive type first emitter common differential transistor pair by the first conductive type seventh transistor, the influence on the output signal due to the fluctuation of the base potential of the input transistor is reduced. In a sample-and-hold circuit that requires a high-speed operation, a stable potential can always be output even when an input signal changes in the holding mode without deteriorating the speed.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a sample and hold circuit according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a sample and hold circuit according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram of a sample and hold circuit according to a first conventional example.

FIG. 4 is a circuit diagram of a second conventional sample-hold circuit.

FIG. 5 is an explanatory diagram showing waveforms of an input signal and an output signal when the potential of the input signal changes in the direction in which the potential of the input signal increases in the holding mode in the conventional sample and hold circuit.

FIG. 6 is an explanatory diagram showing waveforms of an input signal and an output signal when a potential of an input signal changes in a direction to decrease in a holding mode in a conventional sample and hold circuit.

[Explanation of symbols]

Q3 and Q4: first emitter common differential NPN transistor pair, Q3: first transistor of first conductivity type, Q4 ...
A second transistor of the first conductivity type, R1 to R6.
3, R4: superimposing means, Q1: PNP transistor, Q2
... PNP transistor (first transistor of second conductivity type), Q5 and Q6 ... second emitter common differential NPN transistor pair, Q5 ... third transistor of first conductivity type
Q6: fourth transistor of first conductivity type; I1 to I4: current source; C1: capacitor (storage capacitor element); Q7: NP
N transistor, Q8 ... NPN transistor (seventh transistor of the first conductivity type), Q9 ... NPN transistor,
Q12, Q13: diode, Q10 and Q11: third
A common emitter differential NPN transistor pair, Q10: a fifth transistor of the first conductivity type, Q11: a sixth transistor of the first conductivity type, C2, C3, C4 ... a junction capacitance (parasitic capacitance) between the base and the emitter of the NPN transistor, Vcc ...
Power supply, GND: ground potential, IN: input signal, OUT: output signal, HLD: holding signal, SAMP: sampling signal.

Claims (2)

[Claims] A first transistor of a first conductivity type to which an input signal of the sample hold circuit is applied to a base;
A first emitter-common differential transistor pair including a first conductive type second transistor to which the output signal of the sample hold circuit is fed back to the base; and a collector having a collector of the first conductive type second transistor. A first transistor of a second conductivity type, which is connected and serves as a current source load of the second transistor of the first conductivity type; a collector connected to the emitter of the first transistor of the second conductivity type; A third transistor of a first conductivity type to which a signal indicating that there is a signal is applied, a collector is connected to the common emitter of the first emitter common differential transistor pair, and a signal indicating that sampling mode is applied is applied to a base. A second transistor common-differential transistor pair comprising: a first transistor of a first conductivity type; A sample-and-hold circuit comprising: a storage capacitor connected to a collector of a second transistor; and a voltage follower circuit that receives a collector output of the second transistor of the first conductivity type and obtains an output signal of the sample-and-hold circuit. A fifth transistor of a first conductivity type to which a signal indicating the holding mode is applied to a base, and a fifth transistor of a first conductivity type to which a signal indicating the sampling mode is applied to a base. A third common-emitter transistor pair of a first conductivity type comprising: a first transistor of a first conductivity type; a third transistor of a first conductivity type having an emitter connected to a common emitter of the first common-emitter differential transistor pair; Superimposing a first fixed voltage or a second fixed voltage on the potential of the output terminal of the sample and hold circuit, A voltage superimposing unit to be applied to the base of the seventh transistor, the said voltage superimposing unit, the sampling mode first
A first fixed voltage at which the conductive seventh transistor is cut off is a second fixed voltage at which the base-emitter voltage of the first emitter common differential transistor pair is biased in a reverse bias direction in the holding mode. And a sample-and-hold circuit that sets each of the third pairs of transistors by the collector current of the third pair of emitter common differential transistors. 2. The voltage superimposing means includes: an eighth transistor of a first conductivity type to which a signal from the voltage follower circuit is applied to a base; one end of which is connected to an emitter of the eighth transistor of the first conductivity type; A first resistive element having an end connected to the collector of the fifth transistor of the first conductivity type, one end being the other end of the first resistance element, and the other end being the other end of the seventh transistor of the first conductivity type. The sample and hold circuit according to claim 1, further comprising a second resistance element connected to each of the bases.