JPH0750099A - Sample and hold circuit - Google Patents

Abstract

PURPOSE:To make characteristics of all transistors uniform, let an output voltage correctly follow an input voltage in a tracking state and prevent the change of the output voltage in a holding state, by using only one of a push-type current source or a pull-type current source. CONSTITUTION:All of transistors are of NPN type. A current to be fed to a diode bridge is controlled only by a pull-type constant current source part 25. When a clock CLK is in an H level and an inverted clock XCLK is in an L level, TrQ1b, TrQ2a are turned ON and TrQ1a, TrQ2b are turned OFF, so that a current Ia flows to the DB via a resistor R0. That is, a tracking state is obtained. An output voltage of a terminal 24 changes and correctly follows an input voltage of a terminal 20. Meanwhile, when the tracking state is changed to a holding state, the TrQ1b introducing a current from TrQD2, TrQD4 of the DB is turned OFF and at the same time TrQD2, TrQD4 are reversely biased and turned OFF, so that accumulated charges of a capacitor C1 in the tracking state are correctly held thereby to prevent a voltage change.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sample and hold circuit, and more particularly to a circuit for sample and hold an input voltage according to a clock.

[0002]

2. Description of the Related Art FIG. 3 shows the principle of a sample and hold circuit.
Show. In the figure, diode D₁~ D_FourWith diode
Power supply to the diode bridge with the constant current source 10.
The current is pushed in and the diode current is blocked by the constant current source 11.
The current is being drawn from Ji. Here, the constant current sources 10, 1
Current I of 1_1a, I_2aAre the same and the diode D₁~ D
_FourWhen the characteristics of are all the same, the diode bridge
Due to the symmetry I_1a/ 2 current flows
It At this time, the capacitor C₁Charge is accumulated in the terminal 13
The input voltage of the
State). Next, when the constant current sources 10 and 11 are cut off, the
Densa C₁The accumulated charge of the
The output voltage is held (hold state).

There is a circuit shown in FIG. 4 as a specific circuit for simultaneously connecting / disconnecting the constant current sources 11 and 12. This circuit in parallel with the diode bridge between the constant current source 10, 11 provided transistor Q _0, to turn on / off the transistors Q ₀ by supplying a clock from a terminal 15 to the base of the transistor Q _0. When the transistor Q ₀ is off, the current I _1a flows through the diode bridge and is in a track state, and when the transistor Q ₀ is on, the current I _1a flows through the transistor Q ₀ and is bypassed by the diode bridge, so that it is in a hold state.

[0004]

Since the constant current source 10 in FIGS. 3 and 4 is a push-type current source, it is configured by a PNP transistor, and the constant current source 11 is a pull-in current source and is configured by an NPN transistor. There is a need. However, if the constant current sources 10 and 11 are composed of transistors of a type different from PNP and NPN, the characteristics of the two do not completely match and the output voltage does not accurately follow the input voltage in the track state, or in the hold state. There was a problem that the output voltage fluctuated.

The present invention has been made in view of the above points,
An object of the present invention is to provide a sample hold circuit in which the output voltage accurately follows the input voltage in the track state and prevents the output voltage from varying in the hold state.

[0006]

A sample and hold circuit of the present invention applies a constant current to a diode bridge to apply an input signal to one of the anode / cathode connection points of the diode bridge, and the other anode of the diode bridge. The anode of the diode bridge in a sample hold circuit that causes the output voltage of the capacitor connected to the cathode connection point to follow the input signal voltage and cuts off the constant current flowing in the diode bridge 12 to hold the output voltage of the capacitor. A resistor connected between the (or cathode) connection point and the power supply, and the collector of one transistor whose inverted clock is supplied to the base of the differential pair are connected to the anode (or cathode) connection point of the diode bridge, The other transistor whose clock is supplied to the base Is connected to the cathode (or anode) connection point of the diode bridge and the emitters of both transistors are connected to a constant current source, and an inverted clock is supplied to the bases of the differential pair. The collector of one transistor is connected to the anode (or cathode) connection point of the diode bridge, the clock is supplied to the base, the collector of the other transistor is connected to the power supply, and the emitters of both transistors are connected to the constant current source. And a second differential circuit that has been set.

[0007]

In the present invention, since either the push-in current source or the pull-in current source is used, it is possible to unify the type of transistors to be used, either NPN or PNP, thereby unifying the characteristics of all transistors. it can.

[0008]

1 shows a circuit diagram of an embodiment of the circuit of the present invention. In the figure, the analog input voltage VIN is input to the terminal 20, the clock CLK is input to the terminal 21, and the terminal 2
2 is an inverted clock XCLK that is the inverted clock CLK
Comes in. NPN transistor QD ₁ ~QD ₄ is diode-connected base-collector constitute them in the diode bridge. Input voltage V of terminal 20
IN is the emitter of transistor QD ₁ and transistor Q
It is supplied to one of the anode and cathode connection point of the connection point, i.e. the diode bridge of the collector of D _2, the connection point, that the other of the anode and the cathode connection point of the collector of the emitter and the transistor QD ₄ of the transistor QD ₃ was grounded end While being connected to the other end of the capacitor C ₁ ,
It is connected to the output terminal 24 via a buffer amplifier 23 having a high input impedance.

Transistor QD₁, QD₃Commonly connected
Collector or diode bridge anode connection
One point is the power source V_CCResistor R connected to₀The other end and N
PN transistor Q_1a, Q_2bConnected to each collector
And transistor QD₂, QD_FourCommonly connected
The emitter or diode bridge cathode connection is
NPN transistor Q_1bConnected to the collector.
Transistor Q_1a, Q _1bIs the first differential circuit
The commonly connected emitter is the NPN of the constant current source unit 25.
Transistor Q_TenConnected to the collector. As well
NPN transistor Q_2a, Q_2bConstitutes the second differential circuit
The commonly connected emitters are NPN transistors.
Q₁₁Connected to the collector. The terminal 21 clock
CLK is transistor Q_1b, Q_2aSupplied to the base of
The inverted clock XCLK of the terminal 22 is the transistor Q.
_1a, Q_2bSupplied to the base of. Transistor Q_2aThe
The rector is connected to the power source V_CCIt is connected to the. Electric current
NPN transistor Q of the source unit 25₁₂Is the power supply V
_CCConnected to the base of the resistor R_FourPower through V_CCContact
Continued and NPN transistor Q₁₃Contact the collector of
Has been continued. Transistor Q₁₂The emitter of Transi
Star Q_Ten, Q₁₁, Q₁₃While being connected to each base
Resistance R₃Grounded through the transistor Q_Ten, Q₁₁，
Q₁₃Each emitter is a resistor R₁, R₂, R_FiveThrough each
Grounded to form a current mirror.

Accordingly, the emitter current of the transistor Q ₁₃ is represented by (V _CC -2V _BE ) / (R ₄ + R ₅ ) where the base-emitter voltage of the NPN transistor is V _BE , and the current mirror is used as the transistor Q _13. The emitter currents I _a and I _b of the transistors Q ₁₀ and Q _{11 of the} configuration are constant values corresponding to the resistors R ₁ and R ₂ , respectively.

Here, when the clock CLK is at the H level and the inverted clock XCLK is at the L level, the transistors Q _1b and Q _2a are turned on, Q _1a and Q _2b are turned off, and a current is passed through the resistor R ₀ to the diode bridge. I _a flows,
It becomes a track state. As a result, the output voltage of the terminal 24 changes following the input voltage of the terminal 20. However, the resistance R
Voltage drop of ₀ is R ₀ · I _a, the transistor QD ₁
Since there is a voltage drop of V _BE in each of ~ QD ₄ , the maximum value VIN _MAX of the input voltage must be V _CC − (R ₀ · I _a + V _BE ).

Next, when the clock CLK is at L level and the inverted clock XCLK is at H level, the transistors Q _1b ,
Each of Q _2a is turned off, and each of Q _1a and Q _2b is turned on. At this time, the current I _a flowing through the transistor Q _1a and the current I _b flowing through the transistor Q _2b flow through the resistor R ₀ , and (I _a + I
_b ) A voltage drop of _R0 occurs. Where I _b · R ₀ >
If the current _Ib is set to V _BE , a reverse bias is applied to each of the transistors QD ₁ and QD ₃ and the transistor Q _1b is turned off, and at the same time the current is prevented from flowing into the diode bridge. As a result, the charge stored in the capacitor C ₁ is held, and the holding voltage of the capacitor C ₁ is output from the terminal 24.

The circuit of FIG. 1 has a retractable constant current source section 25.
In order to control the current flowing through the diode bridge,
All the transistors used in the circuit can be NPN transistors, and the output voltage accurately follows the input voltage in the track state. Also, when the track state changes to the hold state, the diode bridge transistor QD
At the same time that the transistor Q _1b that draws current from ₂ and QD ₄ is turned off, the diode bridge transistors QD ₂ and QD
D ₄ is reverse-biased and turned off, the accumulated charge of the capacitor C ₁ in the track state is accurately held, and the fluctuation of the output voltage in the hold state is prevented.

FIG. 2 shows a circuit diagram of a modification of the circuit of the present invention.
You In the figure, the same parts as those in FIG.
The description is omitted. In FIG. 2, the capacitor C₁The other end of
Is the NPN transistor Qb of the buffer amplifier 30.₁The ba
Connected to the computer. NPN transistor Qb₁, Qb₂Is
In the differential configuration, the commonly connected emitter is the constant current source unit 31.
NPN transistor Q₁₄Connected to the collector of Qb₁
Is the power supply V_CCConnected to Qb₂Is a collector
Ioded NPN transistor Qb₃Fixed through
It is connected to the current source 40. Transistor Qb₃This
The NPN transistor Qb_FourConnected to the base of
It Transistor Qb_FourIs the power supply V _CCConnected to
And the emitter is a diode-connected NPN transistor.
Qb_FiveThrough the transistor Q of the constant current source unit 31₁₅The
The output terminal 24 and the transistor
Star Qb₂It is connected to the base of and has a gain of 1.
Also, the transistor Qb_FourIs an NPN transistor
Qb₆Is connected to the base of Qb₆Collector of power
V_CCConnected to the emitter of the diode bridge
Register QD₁, QD₃Connected to the collector.

The constant current source section 31 connects the bases of the transistors Q ₁₄ and Q _{15 in} common with the base of the transistor Q ₁₃ .
The emitter of the transistor Q _14, Q ₁₅ is grounded via a resistor R _6, R _7, there is a current mirror configuration.

Transistor Q of buffer amplifier section 30
b ₃ and Qb ₅ output the base potential of the transistor Qb ₆ to the output terminal 2
This is for making V _BE higher than 4 by connecting the emitter of the transistor Qb ₆ (the same potential as the terminal 24) to the collectors of the diode bridge transistors QD ₁ and QD ₃ to hold the transistor QD ₁ in the hold state. , Q
The collector potential of D ₃ is kept at the same potential as the output terminal 24. As a result, the collectors and emitters of the transistors QD ₁ and QD ₃ have the same potential, and no extreme reverse bias is applied, and high-speed operation is possible when the hold state changes to the track state.

In FIGS. 1 and 2, all the transistors are replaced by PNP transistors, and the power source V _CC and the ground are exchanged, whereby control can be performed only by the push-in current source. The output voltage accurately follows the input voltage, and fluctuations of the output voltage in the hold state are prevented.

[0018]

As described above, according to the sample hold circuit of the present invention, the output voltage accurately follows the input voltage in the track state, and it is possible to prevent the output voltage from varying in the hold state. It is useful.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a circuit of the present invention.

FIG. 2 is a circuit diagram of a circuit of the present invention.

FIG. 3 is a principle diagram of a sample hold circuit.

FIG. 4 is a circuit diagram of a conventional circuit.

[Explanation of symbols]

23 and 30 buffer amplifiers 25 and 31 the constant current source section C ₁ capacitor _{Q 1a ~Q 2b, Qb 1 ~Qb} 6, Q 10 ~Q 15 transistor R ₀ to R ₇ resistance

Claims (3)

[Claims] 1. A diode bridge (QD₁~ QD_Four)
Applying a constant current to the diode bridge
Apply the input signal at the node
Connected to the other anode / cathode connection point of the bridge
Capacitors (C₁) Output voltage is the above input signal voltage
Constant current flowing through the diode bridge 12
Shut off the capacitor to maintain the output voltage of the above capacitor.
In the pull-hold circuit, connect the anode (or cathode) of the diode bridge.
A resistor (R₀) And one of the transformers that is supplied with the inverted clock at the base of the differential pair.
Register (Q_1a) Collector above the diode bridge
Connected to the anode (or cathode) connection point of the base
The other transistor (Q_1b)of
Connect the collector to the cathode (or
Node) connection point, and
First differential circuit in which the switch is connected to the constant current source (31)
(Q_1a, Q _1b) And one of the transformers that is supplied with the inverted clock at the base of the differential pair.
Register (Q_2b) Collector above the diode bridge
Connected to the anode (or cathode) connection point of the base
The other transistor (Q_2a)of
The collector is connected to the power supply and the
Second differential circuit in which the switch is connected to the constant current source (31)
(Q_2a, Q_2b) And a sample ho
Field circuit. 2. The sample and hold circuit according to claim 1, wherein the output voltage of the capacitor is supplied to the output terminal (2).
4) has a buffer amplifier (30) for outputting from 4), and the buffer amplifier includes a circuit (Qb ₆ ) for setting the potential of the anode (or cathode) connection point of the diode bridge to the same potential as the output terminal. A sample and hold circuit characterized in that 3. The sample-hold circuit according to claim 1, wherein each diode of the diode bridge is composed of a diode-connected transistor, and all transistors in the circuit are of the same type. circuit.