JPH10199262A - Sense amplifier circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a sense amplifier which can obtain stable and high speed memory output and assures easier timing control even when the power supply voltage is low. SOLUTION: Current sense amplifiers 1, 2 having a positive feedback loop are formed using MOSFETQ1 to Q4 , MOSFET Q5 to Q8 so that the complementary memory outputs OUT, /OUT are output by detecting the complementary input currents from the bit lines bit, /bit. An output of the current sense amplifier 1 is given as a bias of the sense amplifier 2 and an output of the current sense amplifier 2 is given as the bias of the current sense amplifier 1. Moreover, a switch SW1 for isolating MOSFETQ1 of the current sense amplifier 1 and a switch SW2 for isolating MOSFETQ5 are provided and thereby operation in the current sense mode and latch mode can be enabled through the switching to ON and OFF modes of the switches SW1, SW2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sense amplifier, and is suitably applied to, for example, a current detection type sense amplifier used in a static RAM.

[0002]

2. Description of the Related Art Along with a reduction in power supply voltage, in a static RAM (SRAM) or the like, it is essential to operate a bit line near a power supply voltage in order to secure an operation margin of a memory cell. It is getting. At the same time, current sense amplifiers that detect input current from bit lines tend to be used more frequently in sense amplifiers used for bit line sensing than in voltage detection type sense amplifiers, where gain is difficult to obtain near the power supply voltage. is there. As such a current sense amplifier circuit, a feedback bias type and a latch type are conventionally known.

FIG. 5 shows an example of a configuration in which a conventional feedback bias type current sense amplifier composed of CMOS transistors is used for an SRAM. 5, reference numeral Q ₁₀₁ to Q ₁₁₂ represents a MOSFET. Here, MOSFETs Q ₁₀₁ , Q ₁₀₃ , Q ₁₀₅ , Q
₁₀₇ and Q ₁₀₉ are composed of p-channel MOSFETs.
_{SFETQ 102, Q 104, Q 106} , Q 108, Q 110 ~Q
_{Reference numeral 112} is an n-channel MOSFET. In this case, M
The OSFETs Q _{101 to} Q ₁₀₄ constitute a feedback bias type current sense amplifier 101,
The feedback bias type current sense amplifier 102 is configured by TQ _{105 to} Q ₁₀₈ . Also, MOSFE
The fixed bias circuit 103 is configured by TQ _{109 to} Q ₁₁₂ . Bits and bit bars are bit lines of the SRAM and are precharged to the power supply voltage V _CC .

Current sense amplifiers 101 and 102 detect mutually complementary input currents supplied from bit lines bit and bit bar, respectively. Further, these current sense amplifiers 101 and 102 have a feedback loop for positively feeding back the input current.

[0005] That is, in the current sense amplifier 101, the drain of the MOSFET Q ₁₀₁ and MOSFE
The drains of TQ ₁₀₂ are connected to each other and MOSFET Q
Drains and MOSFET Q _{104 103} are connected to each other. The gate of the gate and MOSFET Q ₁₀₃ of MOSFET Q ₁₀₁ are connected to each other,
The gate of MOSFET Q ₁₀₂ and MOSFET Q ₁₀₄
Are connected to each other. Reference numerals 101a and 101b
Indicates a node. In this case, the MOSFETs Q ₁₀₁ , Q
The drain of MOSFET ₁₀₂ and the gates of MOSFETs Q ₁₀₁ and Q ₁₀₃ are connected to each other at a node 101a.
The drain of the TQ _103, Q ₁₀₄ and MOSFET
The gate of Q _102, Q _104, are connected together at node 101b. On the other hand, the source of MOSFET Q ₁₀₂ and M
The source of OSFETQ ₁₀₄ are connected to each other, and are grounded.

In this current sense amplifier 101, M
The sources of MOSFET Q ₁₀₃ of OSFETQ ₁₀₁ are each input unit, the node 101b is the output unit. In this case, the source of the MOSFET Q ₁₀₁ is connected to the bit line bit, the source of the MOSFET Q ₁₀₃ is connected to the bit line bit bar. Node 1
01b outputs an output signal OUT.

The current sense amplifier 102 has the same configuration as the current sense amplifier 101. That is, in the current sense amplifier 102, the MOSFETs Q _{105 to} Q _105
108 is a MOSFET in the current sense amplifier 101
Corresponding to the Q ₁₀₁ to Q _104. Reference numerals 102a and 102b indicate nodes. In this case, MOSFETs Q ₁₀₅ and Q ₁₀₆
Of the MOSFET Q ₁₀₅ and the gate of the MOSFET Q ₁₀₇ are connected to each other at a node 102a.
_107, the drain of Q ₁₀₈ and MOSFET Q _106, Q
₁₀₈ gates are connected together at node 102b.

In this current sense amplifier 102, M
The sources of MOSFET Q ₁₀₇ of OSFETQ ₁₀₅ are each input unit, the node 102b is the output unit. In this case, the source of the MOSFET Q ₁₀₅ is connected to the bit line bit bar, the source of MOSFET Q ₁₀₇ is connected to the bit line bit. Node 1
The output signal OUT-bar is output from 02b.

As described above, the two current sense amplifiers 1 in which the inputs from the bit lines bit and bit bar are exchanged.
01 and 102 are connected in parallel, so that the bit line b
output signal O with respect to the differential input from the
The UT and OUT bars are taken out in a differential form.

A fixed bias circuit 103 supplies a constant current bias used for stable operation of the current sense amplifiers 101 and 102 to nodes 101a and 102a of the current sense amplifiers 101 and 102. In the fixed bias circuit 103, the drain of the drain and MOSFET Q ₁₁₀ of MOSFET Q ₁₀₉ are connected to each other, the source power supply voltage V _CC of the MOSFET Q ₁₀₉
Is connected to a power supply for supplying a source of MOSFET Q ₁₁₀ is grounded. The gate and the drain of the MOSFET Q ₁₀₉ are connected to each other, the gate and drain of the MOSFET Q ₁₁₀ are connected to each other. MOSFE
The gates of TQ ₁₁₁ and Q ₁₁₂ are connected to the gate of MOSFET Q ₁₁₀ . The source of the MOSFET Q ₁₁₁ is grounded, the drain of the MOSFET Q ₁₁₁ is connected to the node 101a of the current sense amplifier 101. On the other hand, the source of MOSFET Q ₁₁₂ is grounded, and the drain of MOSFET Q ₁₁₂ is connected to node 102 a of current sense amplifier 102.

Here, the above-described current sense amplifier 101,
The operation of the current detection type feedback bias type sense amplifier constituted by the fixed bias circuit 102 and the fixed bias circuit 103 will be described. That is, in the current sense amplifier 101 and 102, MOSFET Q ₁₀₁ consisting of p-channel MOSFET, Q ₁₀₃ and MOSFET Q
Positive feedback is applied to the gate of _105, Q _107. Thereby, the MOSFETs Q ₁₀₁ , Q ₁₀₃ of these input sections
And the apparent transfer conductance of the MOSFETs Q ₁₀₅ and Q ₁₀₇ is improved.

At this time, in the current sense amplifier 101, M
Feedback is applied in the order of OSFETs Q ₁₀₁ , Q ₁₀₃ , Q ₁₀₄ , and Q ₁₀₁ , and in the current sense amplifier 102,
MOSFETs Q ₁₀₅ , Q ₁₀₇ , Q ₁₀₈ , Q ₁₀₆ , Q ₁₀₅
Feedback is given in the order of For example, consider a case where the current of the bit line bit becomes larger than the current of the bit line bit bar. In this case, the current sense amplifier 101, a current of MOSFET Q ₁₀₁ is increased,
Current MOSFET Q _103, current MOSFET Q _104, sequentially increasing the current of the MOSFET Q _102, thereby a current of MOSFET Q ₁₀₁ is increased. On the other hand, in the current sense amplifier 102, to decrease the current of the MOSFET Q ₁₀₅ is, current of MOSFET Q _107, MOSFET Q
The current of _{108 and} the current of MOSFET Q ₁₀₆ decrease sequentially,
Thus current MOSFET Q ₁₀₅ is reduced.

Here, it is assumed that the loop gain of the current sense amplifier 101 is A, and the transfer conductance of the MOSFETs Q _{101 to} Q ₁₀₄ constituting the current sense amplifier 101 is gm ₁₀₁ to gm ₁₀₄ . In this case, the loop gain of the current sense amplifier 101 is A = (gm ₁₀₃ / gm
₁₀₁ ) × (gm ₁₀₂ / gm ₁₀₄ ). At this time, the input resistance of the current sense amplifier 101 is
Proportional to _{(1-A) / gm 103} . That is, the current sense amplifier 101 is represented by an equivalent circuit as shown in FIG. Here, FIG. 6A shows the current sense amplifier 1 shown in FIG.
FIG. 6B shows the equivalent circuit of FIG. 6A. From this equivalent circuit,

[0014]

(Equation 1)

## EQU1 ## Here, when equation (4) is solved for V ₃ ,

[0016]

(Equation 2)

## EQU1 ## By substituting the equation (5) into the equation (3) and solving for V ₂ ,

[0018]

(Equation 3)

## EQU1 ## Here, A is a loop gain. In this case,

[0020]

(Equation 4)

## EQU2 ## Here, assuming that V _IN = V _a −V _b and substituting equation (6) into equations (1) and (2),

[0022]

(Equation 5)

[0023] From these (7) and (8), the input resistance of the current sense amplifier 101 V _IN / (i _a -
_ib ), this input resistance is (1-A) / gm
Probably proportional to ₁₀₃ . Current sense amplifier 102
The same can be said for.

Therefore, current sense amplifiers 101, 1
In 02, when the loop gain approaches 1, the input resistance approaches 0, and these current sense amplifiers 1
Outputs of low amplitude are obtained from 01 and 102, and a high-speed sensing operation is possible.

On the other hand, FIG. 7 shows a configuration example in which a conventional current detection type latch sense amplifier constituted by CMOS transistors is used for an SRAM. 7, reference numeral Q ₂₀₁ to Q ₂₀₄ represents a MOSFET. Current sense amplifier 201 of the latch type is constituted by these MOSFET Q ₂₀₁ to Q _204. In this case, MOS
FETs Q ₂₀₁ and Q ₂₀₃ are composed of p-channel MOSFETs, and MOSFETs Q ₂₀₂ and Q ₂₀₄ are n-channel MOSFETs.
Consists of ET.

In the current sense amplifier 201,
MOSFET Q ₂₀₁ drain and MOSFET Q
The drains of ₂₀₂ are connected together and MOSFET Q ₂₀₃
The drain of drain and MOSFET Q ₂₀₄ is connected to be each other. The gate of the gate and MOSFET Q ₂₀₂ of MOSFET Q ₂₀₁ are connected to each other, MOS
Gates and MOSFET Q ₂₀₄ of FETs Q ₂₀₃ are connected to each other. Reference numerals 201a and 201b indicate nodes. In this case, the drains of the MOSFETs Q ₂₀₁ and Q ₂₀₂ and the gates of the MOSFETs Q ₂₀₃ and Q ₂₀₄
MOSFETs connected together at node 201a
The drains of Q ₂₀₃ , Q ₂₀₄ and MOSFETs Q ₂₀₁ ,
The gate of Q ₂₀₂ are connected together at node 201b. The source of MOSFET Q ₂₀₂ and the MOSF
The sources of the ETQ ₂₀₄ are connected together and grounded.

In this current sense amplifier 201, M
The sources of MOSFET Q ₂₀₃ of OSFETQ ₂₀₁ is an input unit. Also, nodes 201a and 201
b is a latch node and an output unit. In this case, M
The source of OSFETQ ₂₀₁ is connected to the bit line bit, the source of the MOSFET Q ₂₀₃ is connected to the bit line bit bar. Then, the output signal O is output from the node 201a.
The UT is output, and the output signal OUT bar is output from the node 201b.

Reference numerals T ₂₀₁ and T ₂₀₂ indicate transfer gates composed of CMOS transistors. These transfer gates T ₂₀₁ and T ₂₀₂ are connected to the node 201.
a, 201b. here,
Switching of the transfer gate T ₂₀₁ is controlled by the equalizing signal EQ _1, the transfer gates T
₂₀₂ switching is controlled by the equalizing signal EQ _2. Reference numerals 202 to 205 indicate inverters. In this case, equalizing signals EQ ₂₀₁ and EQ ₂₀₂ are supplied to the input terminals of the inverters 202 and 204, respectively. The output terminals of inverters 202 and 204 are connected to transfer gates T ₂₀₁ and T ₂₀₂ , respectively.
Connected to the gate of the channel MOSFET,
Each is connected to the input terminals of the inverters 203 and 205. The output terminals of the inverters 203 and 205 are connected to the gates of the n-channel MOSFETs forming the transfer gates T ₂₀₁ and T ₂₀₂ , respectively.

In this current sense amplifier 201, transfer gate _T201 and transfer gate _T202 are CMOS transistors having different transistor sizes from each other.
It is configured using a transistor. Therefore, the transfer gates T ₂₀₁ and T ₂₀₂ have different current capacities. In this case, the current capability of the transfer gate T ₂₀₂ is designed to be lower than the current capability of the transfer gate T _201.

FIG. 8 is a timing chart for explaining the operation of the latch type current sense amplifier 201. Here, FIG. 8A bit line bit, bit bar potential, the potential of FIG. 8B equalize signal EQ _1, the potential of FIG. 8C equalize signal EQ _2, Figure 8D output signal OUT,
Indicates the potential of OUT bar.

When the bit lines bit and bit bar output data of the selected memory cell, the equalizing signals EQ ₁ and EQ ₂ are used to equalize the nodes 201 a and 201 b of the current sense amplifier 201. From low level (0 [V]) to high level ( _Vcc [V])
Changes to As a result, the transfer gates T ₂₀₁ and T ₂₀₂ are both turned on, and the node 201 is turned on.
a and 201b are short-circuited. At this time, these nodes 201a and 201b are connected to the power supply voltage level (V
_CC [V]) and the ground level (0 [V]). Therefore, at this time, the output signals OUT,
OUT bar has substantially the same potential (V _CC / 2 [V]).

[0032] From this state, when only the equalize signal EQ ₁ is switched to the low level, the transfer gate T
₂₀₁ turns off. Therefore, only transfer gate _T202 is turned on. At this time, MOSF
A current flowing through a pull-up transistor (not shown) precharging the bit line to the power supply voltage V _CC and a current obtained by subtracting a memory cell current from this current flow through ETQ ₂₀₁ and Q ₂₀₃ . Here, the current capability of the transfer gate T _202, by setting so that the difference is out such on-resistance as a voltage difference relative to the current from the bit line, node 201a, the 201b, the current difference and potential difference is caused by the oN resistance of the transfer gate T _202.

[0033] When the equalizing signal EQ ₂ is switched from the high level to the low level, the node 201a, the latch is made in the direction of the potential difference 201b. In this case, the output signals OUT and OUT bar fully swing to the power supply voltage level and the ground level. Thus, a data bus having a large load capacity can be strongly driven.

As described above, the latch-type current sense amplifier 201 reads and performs the current difference between the bit lines bit and bit bar by using the two equalizing signals EQ ₁ and EQ ₂ . At this time, the output signals OUT, O
Since the amplitude of the UT bar fully swings between the power supply voltage level and the ground level, stable data bus drive can be performed, and low-voltage operation is also stable. Further, the circuit scale is smaller than that of the feedback bias type sense amplifier, and the layout scale can be reduced.

[0035]

However, conventional current detection type feedback bias type sense amplifiers and latch type sense amplifiers have the following problems.

That is, in the conventional current detection type feedback bias type sense amplifier shown in FIG. 5, the current sense amplifiers 101 and 102 perform sensing independently and output signals OUT and OU with low amplitude.
Generates a T-bar. Therefore, the current sense amplifier 10
MOSFETs Q _{101 to} Q ₁₀₄ , M
If the circuit characteristics of the two current sense amplifiers 101 and 102 are unbalanced due to the variation in the individual characteristics of the OSFETs Q _{105 to} Q ₁₀₈ , the output signals OUT and OUT
A problem arises in that a stable differential output cannot be obtained due to a shift in the output voltage level of the bar or a difference between the respective amplitudes. In this case, these current sense amplifiers 101, 10
The next and subsequent sense amplifiers that receive the output from 2
Due to this effect, the sensing ability is greatly reduced, or
There is a possibility of malfunction. This is considered to be particularly remarkable when the operation is performed at a low power supply voltage, and is a significant restriction when the sense amplifier that outputs low amplitude is operated at a low voltage.

Further, in the case of the conventional current detection type latch type sense amplifier shown in FIG. 7, it is necessary to perform equalization control inevitably. In this case, there is a risk that erroneous data will continue to be output unless the equalizing operation is performed again. Furthermore, when the power supply voltage is used at a low voltage, the latch operation itself is stable, but the equalizing capability is reduced, so that it becomes difficult to equalize a full-swing output, and the timing control of the equalizing signal itself is also performed at a low voltage. There is a problem that it becomes difficult on the side and causes a malfunction.

Accordingly, an object of the present invention is to solve the above-mentioned problems and to provide a stable and stable operation even when the power supply voltage is low.
An object of the present invention is to provide a sense amplifier that can obtain a high-speed memory output and that can easily control timing.

[0039]

In order to achieve the above object, the present invention relates to a current detection type sense amplifier for detecting a complementary input current supplied from a bit line and extracting a memory output. Complementary input current from the bit line is provided, and a first sense amplifier including a current feedback loop for positively feeding back the input current, and a complementary sense current from the bit line in a direction different from the direction to the first sense amplifier. And a second sense amplifier including a current feedback loop for providing a positive feedback of the input current, and providing an output of the second sense amplifier as a bias to the first sense amplifier. , The output of the first sense amplifier is applied as a bias to the complementary memory output from the first sense amplifier and the second sense amplifier. It is characterized in that it has to take out.

In one embodiment of the present invention, the current feedback loop of the first sense amplifier and the second sense amplifier is turned on, and the current feedback loop detects a complementary input current supplied from the bit line. Switch means is provided for switching between a mode and a latch mode for turning off a current feedback loop of the first sense amplifier and the second sense amplifier and latching information based on a complementary input current supplied from a bit line.

According to the sense amplifier of the present invention, the output of the second sense amplifier is provided as a bias for the first sense amplifier, and the output of the first sense amplifier is provided as a bias for the second sense amplifier. Thereby, in the first sense amplifier and the second sense amplifier which originally independently sensed the complementary input current from the bit line, the output of one sense amplifier is replaced with the output of the other sense amplifier. The output is reflected to the sense amplifier in the form of a feedback bias, and the output levels of the two can be adjusted. Therefore, the memory output can be obtained stably and at high speed in the form of a differential output interlocked with each other.

Since the first sense amplifier and the second sense amplifier are connected to each other when one output is supplied to the other, a part of the first sense amplifier and the second sense amplifier is provided. Can be used to form a latch circuit. The switch means can switch between a current sense mode operating as a feedback bias type sense amplifier and a latch mode operating as a latch type sense amplifier. This allows the device to operate in the high-speed current sense mode at normal power supply voltage, performs sensing in current sense mode when the power supply voltage is low, and amplifies the memory output in latch mode in which the operation at low voltage is stable. Can be latched. In this case, since the equalizing operation is not required in the latch mode, the timing control is simplified.

[0043]

Embodiments of the present invention will be described below with reference to the drawings. First, the first of the present invention
An embodiment will be described. FIG. 1 is a circuit diagram showing a configuration example in the case where a current detection type sense amplifier according to the first embodiment configured using CMOS transistors is used for an SRAM. In FIG. 1, symbols Q _{1 to} Q ₈
Indicates a MOSFET. Here, MOSFETs Q ₁ and Q
₃ , Q ₅ and Q ₇ are composed of p-channel MOSFETs, and M
OSFETs Q ₂ , Q ₄ , Q ₆ and Q ₈ are n-channel MOS
It consists of FET. In this case, the MOSFETs Q _{1 to} Q ₄ constitute a feedback bias type current sense amplifier 1, and the MOSFETs Q _{5 to} Q ₈ constitute a feedback bias type current sense amplifier 2. Further, reference numerals “bit” and “bit bar” indicate bit lines of the SRAM. These bit lines bit and bit bar are connected to the power supply voltage V
Precharged to _CC .

The current sense amplifiers 1 and 2 detect mutually complementary input currents supplied from the bit lines bit and bit bar, respectively, and output mutually complementary output signals OUT and OUT as memory outputs. Further, these current sense amplifiers 1 and 2 have a feedback loop for positively feeding back the input current.

In current sense amplifier 1, MOSF
Drains and MOSFET Q ₂ of ETQ ₁ are connected to each other via a switch SW1, MOSF
Drains and MOSFET Q ₄ of ETQ ₃ are connected to each other. The gate of the gate and MOSFET Q ₃ of MOSFET Q ₁ are connected to each other, M
Gates and MOSFET Q ₄ of OSFETQ ₂ are connected to each other. Reference numerals 1a and 1b indicate nodes. In this case, the node 1a corresponds to the drain connection point of the drain and MOSFET Q ₂ of MOSFET Q _1. On the other hand, the node 1b corresponds to the drain connection point of the drain and MOSFET Q ₄ of MOSFET Q _3. In this case, the drains of MOSFETs Q ₁ and Q ₂ and the gates of MOSFETs Q ₁ and Q ₃ are connected to each other at node 1a, and the drains of MOSFETs Q ₃ and Q ₄ and the gates of MOSFETs Q ₂ and Q ₄ are connected to each other at node 1b. You. The source of the source and MOSFET Q ₄ of MOSFET Q ₂ are connected to each other, and,
Grounded.

In this current sense amplifier 1, MOS
The sources of MOSFET Q ₃ of FETs Q ₁ are each input unit, the node 1b is output. In this case, the source of the MOSFET Q ₁ is bit line b
is connected to it, the source of the MOSFET Q ₃ is connected to the bit line bit bar. The output signal OUT is output from the node 1b.

In current sense amplifier 2, MOSF
Drains and MOSFET Q ₆ of ETQ ₅ are connected to each other via the switch SW2, MOSF
Drains and MOSFET Q ₈ of ETQ ₇ are connected to each other. The gate of the gate and MOSFET Q ₇ of MOSFET Q ₅ are connected to each other, M
Gates and MOSFET Q ₈ of OSFETQ ₆ are connected to each other. Reference numerals 2a and 2b indicate nodes. In this case, the node 2a, the drain and the MOSFET MOSFET Q ₅ when the switch SW2 is turned on
Corresponding to the connection point of the drain of Q _6. On the other hand, node 2b
, The drain of MOSFETQ ₇ and MOSFETQ
Corresponds to drain connection point ₈ In this case, the switch SW1 is turned on, the gate of the drain and MOSFET Q _5, Q ₇ of MOSFET Q _5, Q ₆ are connected to each other at node 2a, the gate of the drain and MOSFET Q _6, Q ₈ of MOSFET Q _7, Q ₈ Are connected to each other at a node 2b. The source of the source and MOSFET Q ₈ of MOSFET Q ₆ are connected to each other, and are grounded.

In this current sense amplifier 2, MOS
The sources of MOSFET Q ₇ of the FETs Q ₅ are each input unit, the node 2b is an output unit. In this case, the source of the MOSFET Q ₅ bit line b
is connected with it bars, the source of the MOSFET Q ₇ is connected to the bit line bit. The output signal OUT bar is output from the node 2b.

Further, node 1b of current sense amplifier 1
And node 2a of current sense amplifier 2 is connected to each other, and node 2b of current sense amplifier 2 and node 1a of current sense amplifier 1 are connected to each other.
C1 is a control signal for controlling ON / OFF of the switches SW1 and SW2. In this case, the switches SW1 and SW2 are turned on while the control signal C1 is at a low level, and the switches SW1 and SW1 are turned on while the control signal C1 is at a high level.
SW2 is turned off. The control signal C1 is supplied from, for example, a circuit (not shown) that receives an output signal from an address transition detection (ATD) circuit (not shown) and generates a low-level pulse for a predetermined period.

In the current detection type sense amplifier configured as described above, the switch SW1 and the switch SW
2 is on, the MOSFE of the current sense amplifier 1
Drain of TQ ₁ is connected to the node 1a, the drain of MOSFET Q ₂ of the current sense amplifier 2 is connected to the node 2a. In this case, in this sense amplifier, two feedback bias type current sense amplifiers 1 and 2 whose inputs are exchanged are connected in parallel to differential inputs from bit lines bit and bit bar, and output signals OUT and OU are output.
T-bar will be taken out in a differential manner and will operate in current sense mode. The operating principle in this case is shown in FIG.
Can be considered to be similar to the conventional feedback bias type sense amplifier shown in FIG.

That is, in the current sense amplifier 1 and the current sense amplifier 2, the MOSFETs Q ₁ , Q ₃ and MOSFETs Q ₅ ,
To the gate of Q _7, positive feedback each is applied. As a result, the apparent transfer conductance of the MOSFETs Q ₁ , Q ₃ and MOSFETs Q ₅ , Q ₇ at these input portions is improved.

At this time, in the current sense amplifier 1, the MOS
Feedback is applied in the order of FETs Q ₁ , Q ₃ , Q ₄ , and Q _1.
Feedback is applied in the order of Q ₅ , Q ₇ , Q ₈ , Q ₆ , Q ₅ . For example, if the current of the bit line bit is larger than the current of the bit line bit bar, the current in the sense amplifier 1, the current increases MOSFET Q _1, the current of the MOSFET Q ₃ receives this, MOSFET Q ₄
Current, MOSFET Q ₂ of current increases sequentially. Thus current MOSFET Q ₁ increases. On the other hand, the current in the sense amplifier 2, the current is decreased MOSFET Q _5, MOSFET Q ₇ of the current response to this, MOSF
The current of the ETQ _{8 and} the current of the MOSFET Q ₆ sequentially decrease. Thus current MOSFET Q ₅ is reduced.

Here, the MOSFE of the current sense amplifier 1
Assuming that the transfer conductance of TQ _{1 to} Q ₄ is gm ₁ to gm ₄ , the loop gain A of the current sense amplifier 1 is
A = (gm ₃ / gm ₁ ) × (gm ₂ / gm ₄ ). The input resistance R _IN of the current sense amplifier 1 is
As in the case of the conventional feedback bias type sense amplifier shown in FIG. 5, it is proportional to (1-A) / gm ₃ . Therefore, when the loop gain A approaches 1, the input resistance R _IN approaches 0. The same can be said for the current sense amplifier 2. Therefore, in this sense amplifier, the voltage amplitude between the bit lines bit and bit bar can be reduced as much as possible, and the bit lines bit and bit
The voltage of t-bar can be almost at the level of the power supply voltage V _CC . As a result, a low-amplitude output is obtained, and a high-speed amplitude operation becomes possible.

In this case, node 1b of current sense amplifier 1 and node 2a of current sense amplifier 2 are connected to each other, and node 2b of current sense amplifier 2 and node 1a of current sense amplifier 1 are connected to each other. , The output signal OUT of the current sense amplifier 1 is given as a feedback bias to the gates of the MOSFETs Q ₅ and Q ₇ of the current sense amplifier 2, and the output signal OUT bar of the current sense amplifier 2
The feedback bias is applied to the gates of the SFETs Q ₁ and Q ₃ .

On the other hand, switch SW1 and switch SW
2 is off, the MOSFE of the current sense amplifier 1
TQ ₁ is disconnected from the node 1a, the MOSFET Q ₅ of the current sense amplifier 2 is disconnected from the node 2a.
Thereby, a part of the current sense amplifier 1 and a part of the current sense amplifier 2 constitute a latch circuit. In this case, consists one inverter circuit by the MOSFET Q ₂ of MOSFET Q ₇ and the current sense amplifier 1 of the current sense amplifier 2, the current sense amplifier 1 MOSFET
Q ₃ and another inverter circuit is constituted by a MOSFET Q ₆ of the current sense amplifier 2. Then, a latch circuit is configured using these inverter circuits.

Therefore, in the sense amplifier according to the first embodiment, when the switches SW1 and SW2 are off, the latch type sense amplifier constituted by a part of the current sense amplifiers 1 and 2 operates, and the power supply Voltage level (V
_Thus , output signals OUT and OUT-bar fully swinging between _CC [V]) and the ground level (0 [V]) are obtained.

As described above, the sense amplifier according to the first embodiment operates in a current sense mode operating as a static feedback bias type current sense amplifier according to the ON / OFF state of the switches SW1 and SW2, and a latch type. And a latch mode operating as a sense amplifier. Therefore, in the case of a normal power supply voltage, this sense amplifier
By always setting 1 to the low level, it is possible to operate only the current detection type feedback bias type sense amplifier. If the power supply voltage is low,
By turning on / off the switches SW1 and SW2 by the control signal C1, it is possible to perform an operation using both the current sense mode and the latch mode. Hereinafter, the operation in this case will be described.

FIG. 2 is a timing chart for explaining an operation example of the sense amplifier. Here, FIG. 2A shows the level of the bit lines bit and bit bar, FIG. 2B shows the level of the control signal C1, and FIG.
Indicates the levels of the output signals OUT and OUT bar.

In the sense amplifier according to the first embodiment, when new data is read during a read cycle, it is necessary to switch the sense amplifier from the latch mode to the current sense mode. In this case, the period of the current sense mode should be a period necessary and sufficient for sensing within a period in which data of the selected memory cell (not shown) is output on the bit lines bit and bit bar. Good.

Now, as shown in FIG. 2A, a case where data inverted from the previous address data is read will be considered. It is assumed that the control signal C1 receives a pulse that goes low for a certain period in response to an address change.
At this time, as shown in FIG. 2B, until the control signal C1 changes from the high level to the low level, the switch S
W1 and SW2 are turned off and operate in the latch mode. In this case, as shown in FIG. 2C, the sense amplifier latches the previous data, and the output signals OUT and OUT bar fully swing between 0 [V] and V _CC [V].

When the control signal C1 goes low and the switches SW1 and SW2 are turned on, the sense amplifier enters the current sense mode in response to this. In this case, the amplitude of the output signals OUT and OUT bar is
The amplitude due to the original gain of the configured feedback bias type current sense amplifier 1 by ETQ ₁ to Q ₄ and MOSFET Q ₅ to Q _8. During this period, when the bit lines bit and bit bar are inverted, the output signals OUT and OUT bar are also inverted. Therefore, the period during which the control signal C1 is at the low level may be longer than the period until the output signals OUT and OUT bar are inverted and the output is determined.

When the control signal C1 changes from the low level to the high level from this state, the switches SW1, SW2
Is turned off, and this sense amplifier operates in the latch mode. At this time, the latch is performed in the direction of the potential difference generated in the current sense mode, so that the output signals OUT and OUT bar fully swing between the power supply voltage level and the ground level. Further, in this sense amplifier, the output signals OUT and OUT bar which have been fully swinged are continuously latched until the control signal C1 switches to the low level next time. For this reason, the timing control and the circuit configuration of the next and subsequent stages are greatly simplified. Also, in this case,
As for the timing of the control signal C1, it is only necessary to pay attention to the timing of switching from the current sense mode to the latch mode, and since equalization is unnecessary, the influence of the access time due to the generation timing of the equalize signal is eliminated.

In an actual circuit, bit lines bit,
a bit bar of a column decoder (not shown) and a sense amplifier are separated by the switch, the output level is configured to be completely the power supply voltage V _CC level.

As described above, according to the sense amplifier of the first embodiment, it is possible to operate only in the high-speed current sense mode at the time of a normal power supply voltage, and to operate the current sense mode at a low voltage. A stable differential output can be obtained by using both the mode and the latch mode. This makes it possible to operate this sense amplifier in a wide voltage range.

When operating in the current sense mode,
The output signal OUT of the current sense amplifier 1 is provided to the current sense amplifier 2 as a feedback bias, and the output signal OUT bar of the current sense amplifier 2 is provided as a feedback bias of the sense amplifier. Output signals OUT, OUT
The levels of the bars can be adjusted, and a stable memory output can be obtained in the form of a differential output linked to each other.

Further, by switching from the static current sense mode to the latch mode, the equalizing operation which is indispensable in the conventional latch type current sense amplifier becomes unnecessary, and the timing control can be simplified.
Further, since the output signals OUT and OUT bar swing from the amplitude level in the current sense mode to the power supply voltage level or the ground level, the output signals OUT and OUT bar are driven at a higher speed than the conventional latch type sense amplifier swinging from the equalize level. High swing speed.

Further, this sense amplifier has two amplifier modes of a feedback bias type and a latch type. In this case, a part of the two current sense amplifiers 1 and 2 constituting the feedback bias type sense amplifier is used. Thus, since a latch-type sense amplifier is configured, an increase in circuit elements can be suppressed.

Next, a second embodiment of the present invention will be described. FIG. 3 is a circuit diagram showing a configuration example when a current detection type sense amplifier according to the second embodiment of the present invention, which is configured using CMOS transistors, is used for an SRAM. In FIG. 3, Q ₁₁ ~Q ₁₈ is MOSFE
T is shown. Here, MOSFETs Q ₁₁ , Q ₁₂ , Q ₁₅ , Q
₁₆ is a p-channel MOSFET, and MOSFET Q
_{13, Q 14, Q 17,} Q 18 is an n-channel MOSFET. Also, bit and bit bar are SRAM bit lines. These bit lines bit, bit bar is precharged to power supply voltage V _CC.

In this case, the gates of MOSFETs Q ₁₁ -Q ₁₄ are connected together at node 11 and
Gates of FETs Q ₁₅ to Q ₁₈ are connected together at a node 12. In addition, the drain of the MOSFETQ ₁₁ and MO
Drain of SFETQ ₁₃ are connected to each other, a MOSFET
Drains and MOSFET Q ₁₄ of TQ ₁₂ are connected to each other, the drain of the MOSFET Q ₁₅ and M
Drain of OSFETQ ₁₇ are connected to each other, MOSF
Drains and MOSFET Q ₁₈ of ETQ ₁₆ are connected to each other.

Further, the drains of the MOSFETs Q ₁₂ and Q ₁₄ and the gates of the MOSFETs Q _{15 to} Q ₁₈ are connected to the node 1.
Are connected to each other by 2, the gates of the drain and MOSFET Q ₁₁ to Q ₁₄ of the MOSFET Q _15, Q ₁₇ is, node 1
1 connected to each other. In addition, MOSFETs Q ₁₁ and Q ₁₃
The gate of the drain and MOSFET Q ₁₁ to Q ₁₄ is,
Transfer gate T composed of CMOS transistor
₁₁ are connected together at node 11 via, MOSFET
The gate of the drain and MOSFET Q ₁₅ to Q ₁₈ of Q _16, Q ₁₈ are connected together at node 12 via the transfer gate T ₁₂ consisting of CMOS transistors.

In this sense amplifier circuit, MOS
The sources of MOSFET Q ₁₅ of FETs Q ₁₁ is connected to the bit line bit, the source of the source and MOSFET Q ₁₆ of MOSFET Q ₁₂ is connected to the bit line bit bar. On the other hand, MOSFETs Q ₁₂ , Q ₁₄ , Q ₁₆ ,
The source of Q ₁₈ is grounded. The output signal OUT bar is output from the node 11, and the output signal O is output from the node 12.
The UT is output.

Reference numerals 13 and 14 indicate inverters. A control signal C1 is supplied to an input terminal of the inverter 13. The output terminal of the inverter 13 is connected to the gates of the n-channel MOSFETs forming the transfer gates T ₁₁ and T _12, and the output terminal of the inverter 13 is connected to the input terminal of the inverter 14. The output terminals of the inverter 14 are transfer gates T ₁₁ , T ₁₂
Is connected to the gate of the p-channel MOSFET.

ON / OFF of transfer gates T ₁₁ and T ₁₂
The off state is controlled by the control signal C1, and when the control signal C1 is at a low level, the transfer gates T ₁₁ and T _11
12 is turned on. In this case, MOSFET Q ₁₁ ,
A feedback bias type sense amplifier is constituted by Q ₁₂ , Q ₁₇ , and Q ₁₈ , and MOSFETs Q ₁₅ , Q ₁₆ ,
Q ₁₂ and Q ₁₃ constitute a feedback bias type current sense amplifier. Further, the MOSFETs Q ₁₁ , Q
_12, as a feedback bias current sense amplifier consisting of _{Q 17, Q 18, MOSFETQ 15} , Q 16, Q 12,
The output of the current sense amplifier consisting of Q ₁₃ is given, MO
The MOSFET Q is used as a feedback bias of a current sense amplifier composed of SFETs Q ₁₅ , Q ₁₆ , Q ₁₂ and Q _13.
11, Q ₁₂ outputs of the current sense amplifier consisting of, Q _17, Q ₁₈ are given.

In this case, in the conventional current detection type feedback bias type sense amplifier shown in FIG.
Considering that the constant current bias supplied from the fixed bias circuit 103 is replaced with a bias that can be varied in a differential manner, the operation principle is basically the same as that of a conventional feedback bias type sense amplifier. It is believed that there is. In this case, the MOSFETs Q ₁₁ , Q ₁₂ , Q ₁₈ , Q
_17, the feedback in the order of Q ₁₁ is multiplied, MOSFE
Feedback is applied in the order of TQ ₁₆ , Q ₁₅ , Q ₁₃ , Q ₁₄ , and Q ₁₆ . For example, if the current of the bit line bit is bi
If t is larger than the bar, the current is increased MOSFET Q _11, MOSFET Q ₁₂ receives this, Q _18, Q ₁₇
Current increases sequentially. Thus current MOSFET Q ₁₁ is increased. On the other hand, the current is decreased MOSFET Q _16, In response to this MOSFET Q _15, Q _13, current Q ₁₄ decreases sequentially. Thus current MOSFET Q ₁₆ is reduced.

When the control signal C1 is at a high level, the transfer gates T ₁₁ and T ₁₂ are turned off, and the drains of the MOSFETs Q ₁₁ , Q ₁₃ , Q ₁₆ and Q ₁₈ are disconnected from the nodes 11 and 12. . In this case, M
The OSFETs Q ₁₂ , Q ₁₄ , Q ₁₅ and Q ₁₇ constitute a latch-type current sense amplifier. Therefore, as in the case of the first embodiment, the current sense mode and the latch mode can be switched. The operation in this case is the same as that of the first embodiment, and the description is omitted. As described above, the same effect as the sense amplifier according to the first embodiment can be obtained by the sense amplifier according to the second embodiment.

Next, a third embodiment of the present invention will be described. FIG. 4 is a circuit diagram showing a configuration example when a current detection type sense amplifier according to the third embodiment of the present invention, which is configured using CMOS transistors, is used for an SRAM. In FIG. 4, the same or corresponding portions as in FIG. 3 are denoted by the same reference numerals, and description thereof will be omitted.

As shown in FIG. 4, the sense amplifier according to the third embodiment has the same structure as the sense amplifier according to the second embodiment shown in FIG.
2 has an equalizing circuit for equalizing. The equalizing circuit is constituted by the transfer gates T ₁₃ and an inverter 15. The code EQ is
A equalizing signal for controlling on / off of the transfer gate T _13. In this equalize circuit, the transfer gate T ₁₃ is connected between node 11 and node 12. The equalizing signal EQ is supplied to an input terminal of the inverter 15. Inverter 15
The output terminal, p constituting the transfer gate T ₁₃
Connected to the gate of the channel MOSFET,
Connected to the input terminal of inverter 16. Inverter 1
Output terminal 6 is connected to the gate of n-channel MOSFET constituting the transfer gate T _13.

According to the sense amplifier of the third embodiment, the following effect can be obtained in addition to the same effect as the sense amplifier of the first embodiment. That is, since this sense amplifier has an equalizing circuit between the node 11 which is the output section of the output signal OUT and the node 12 which is the output section of the output signal OUT, when the mode changes from the latch mode to the current sense mode. Higher swing speed and equalization of output before sensing are possible, and further higher speed can be achieved.
The present invention is not limited to the above embodiment, and various modifications based on the technical idea of the present invention are possible. For example, the configurations and the like described in the embodiments are merely examples, and the present invention is not limited thereto. Specifically, for example, in the above-described third embodiment, two types of equalizing circuits may be provided as in the conventional latch-type sense amplifier. In this case, the control signal C1 can always be set to the high level, and only the operation of the current detection type latch type sense amplifier can be performed.

[0079]

As described above, according to the present invention, a current detection type sense amplifier having both advantages of a static feedback bias type sense amplifier and advantages of a latch type sense amplifier is provided in one circuit. Even when the power supply voltage is low, a stable and high-speed memory output can be obtained, and the timing control can be simplified.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration example when a current detection type sense amplifier according to a first embodiment of the present invention is used in an SRAM;

FIG. 2 is a timing chart for explaining the operation of the current detection type sense amplifier according to the first embodiment of the present invention;

FIG. 3 is a circuit diagram showing a configuration example when a current detection type sense amplifier according to a second embodiment of the present invention is used in an SRAM;

FIG. 4 is a circuit diagram showing a configuration example when a current detection type sense amplifier according to a third embodiment of the present invention is used in an SRAM;

FIG. 5 is a circuit diagram showing a configuration example in the case where a conventional current detection type foot-back bias type sense amplifier is used in an SRAM.

FIG. 6 is a circuit diagram showing an equivalent circuit of the current sense amplifier 101 shown in FIG.

FIG. 7 is a circuit diagram showing a configuration example when a conventional current detection type latch sense amplifier is used in an SRAM.

FIG. 8 is a timing chart for explaining an operation of a conventional current detection type latch type sense amplifier.

[Explanation of symbols]

1, 2,..., Current sense amplifier, 1a, 1b, 2a, 2
b ··· _{node, Q 1 ~Q 8 ··· MOSFET,} SW
1, SW2 ... switch, bit, bit bar ...
Bit line, OUT, OUT bar ... output signal, C1
··Control signal

Claims (3)

[Claims] 1. A current detection type sense amplifier which detects a complementary input current supplied from a bit line to take out a memory output, wherein a complementary input current from the bit line is supplied, and A first sense amplifier including a current feedback loop for positively feeding a current; and a complementary input current from the bit line in a direction different from the direction to the first sense amplifier.
A second sense amplifier including a current feedback loop that positively feeds back the input current, wherein an output of the second sense amplifier is provided as a bias for the first sense amplifier, and a bias for the second sense amplifier is provided. A sense amplifier for receiving an output of the first sense amplifier and extracting a complementary memory output from the first sense amplifier and the second sense amplifier; 2. The first sense amplifier and the second sense amplifier.
A current sense mode for turning on the current feedback loop of the sense amplifier and detecting a complementary input current supplied from the bit line by the current feedback loop; and a current sense mode for the first sense amplifier and the second sense amplifier. 2. The sense amplifier according to claim 1, further comprising switch means for turning off the current feedback loop and switching between a latch mode for latching information based on a complementary input current supplied from the bit line. 3. The first sense amplifier and the second sense amplifier.
3. The sense amplifier according to claim 2, further comprising an equalizing circuit for equalizing a complementary memory output from said sense amplifier.