JPH10198466A - Ic for monitoring power supply voltage - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the generation time of a reset signal to be applied to a system after the generation of a data saving command from being unstabilized due to the disturbance or the like of a voltage drop waveform in the main power supply and to prevent data saving from being failed due to the reset of the system during the writing of saving data in the system for saving/storing data in a non-volatile memory at the time of turning off the main power supply. SOLUTION: A power supply voltage monitoring IC 33 for outputting a data saving signal from an INT terminal 7 to the system when the main power supply VCC is dropped over backup voltage is provided with an input terminal 34 for a reset permission signal generated after the execution of data saving processing by the system and a counter 42 for starting count from the generation of the data saving signal and executing count-up after the lapse of time necessary for data saving, and when either one of the reset permission signal and the count-up signal is generated, a reset signal is outputted from a gate circuit 41.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power supply voltage monitor which is incorporated in a microcomputer system and is used to save and store a series of plural bytes of data in a memory which is non-volatile by a battery backup or the like when a main power supply is turned off. Related to ICs.

[0002]

2. Description of the Related Art A microcomputer system which saves data in a non-volatile memory by a battery backup when the power is turned off, reads the data when the power is turned on again, and resumes the operation, detects the timing of saving the data. For this purpose, it is common to incorporate a power supply voltage monitoring IC.

FIG. 6 shows an internal equivalent circuit of a conventional power supply voltage monitoring IC. In FIG. 6, reference numeral 1 denotes a VCC terminal, which is connected to the main power supply of the system + 5V. Reference numeral 2 denotes a TC terminal for connecting an external capacitor, and this capacitor determines the time for resetting the microcomputer when the main power is turned on. 3 is a ground terminal of the system. Reference numeral 4 denotes a VOUT terminal for supplying power to a power supply terminal of a memory for saving data. A VBAT terminal 5 is supplied with power from a backup power source such as a battery. Reference numeral 6 denotes a CS bar terminal, which outputs a backup control signal to a nonvolatile memory. Reference numeral 7 denotes an INT terminal which outputs an interrupt signal for causing the microcomputer to save data when the main power supply voltage VCC drops to the backup reference voltage. 8
Is a RESET bar terminal, which outputs a reset signal to the microcomputer.

In the configuration shown in FIG. 6, a switching voltage detection circuit 92 monitors the input voltage from the VCC terminal 1 by a comparator with hysteresis, and outputs a high level signal when the voltage is higher than 3.3 V, and outputs a high level signal when the voltage is higher than 3.3 V. If it is low, a low level signal is output.

When this high level signal is output, both the transistors 10 and 11 are turned on, and the voltage of the VCC terminal 1 is supplied to the VOUT terminal 4. When the low level signal is output, both the transistors 10 and 11 are turned off, and the voltage of the VBAT terminal 5 is supplied to the VOUT terminal 4 through the backflow preventing shet key barrier diode 12.

The backup voltage detecting circuit 91 monitors the input voltage from the VCC terminal 1 by a comparator with hysteresis, and outputs a low level signal when the voltage is lower than 4.75 V, and outputs a low level signal when the voltage is higher than 4.75 V. Outputs a high level signal. This low-level signal is inverted by the Schmitt trigger input inverter 13 and output from the INT terminal 7 as an interrupt signal to save data to an external microcomputer.

The reset voltage detection circuit 93 is connected to the VCC terminal 1
Is monitored by a comparator with hysteresis, and outputs a low-level signal when the voltage is lower than 4.2 V, and outputs a high-level signal when the voltage is higher than 4.2 V. This output is received by an open collector or open drain buffer 14. This buffer 1
4 is connected to a TC terminal 2 which receives a current from a constant current source 15.

When the reset voltage detecting circuit 93 outputs a high level signal, the external capacitor connected to the TC terminal 2 is charged to +5 V by the current from the constant current source 15. When the voltage detection circuit 93 outputs a low-level signal, the TC terminal 2 becomes +0 V by the ground output of the buffer 14.

The voltage at the TC terminal 2 is determined to be high or low by the inverter 16 of the Schmitt trigger input, and the inverted output is divided by the resistors 17 and 18 to drive the transistor 19. That is, the transistor 19 is turned on when the power supply voltage is lower than 4.2 V and the voltage detection circuit 93 outputs a low level signal, and sets the RESET bar terminal 8 to a low level (reset signal to the system).

A signal obtained by inverting the output of the inverter 16 by the inverter 20 drives the transistor 23 through the resistors 21 and 22. This transistor 2
3 is turned off at the time of reset when the reset voltage detection circuit 93 outputs a low level signal, and the CS bar terminal 6 is set to the same voltage as the VOUT terminal through the resistor 24;
Is turned on when outputting a high-level signal, and the CS bar terminal 6 is set to low level.

FIG. 7 shows a connection example of a microcomputer system using the above-mentioned conventional power supply voltage monitoring IC.
In FIG. 7, 25 is a power supply voltage monitoring IC, 26 is a microcomputer, 27 is a nonvolatile memory by battery backup, 28 is a backup power supply,
An external capacitor 29 determines a reset time after power is turned on.

In the configuration shown in FIGS. 6 and 7, when the main power is turned off and the voltage drops to 4.75 V, an interrupt signal is output from the INT terminal 7 to the microcomputer 26 to save data. The microcomputer 26 is
Based on this interrupt signal, the nonvolatile memory 27
, Data is saved. The content of the save data is a series of data of a plurality of bytes.

When the voltage further drops to 4.2 V, the CS bar terminal 6 is set to a low level, the CE1 bar terminal of the memory 27 storing the save data is set to a high level, and a low-level reset signal is output from the RESET bar terminal 8. .

When the voltage further drops to 3.3 V, the memory 2
7 is supplied from the main power supply VCC to the backup power supply 2
Switch to 8. This state continues even if the main power supply VCC is not supplied to the power supply voltage monitoring IC 25.

When the main power supply VCC is turned on again,
When the voltage of the main power supply VCC rises to 3.3V,
The power supply to the memory 27 is switched from the backup power supply 28 to the main power supply VCC. When the power supply rises to 4.2 V, the reset state is released, and the CE1 bar terminal of the memory 27 storing the save data is set to low level. I do. As a result, the operation is resumed by the data saved in the memory 27.

[0016]

In the above-described conventional power supply voltage monitoring IC 25, the microcomputer 2 is connected to the INT terminal 7 through the INT terminal 7 in order to save data when the main power supply is turned off.
The reset signal output from the RESET bar terminal 8 and the interrupt signal output to 6 are the determination results of low / high by the comparators 13 and 16 with hysteresis.

However, since the comparators 13 and 16 have characteristic variations and accuracy errors, and the voltage waveform of the main power supply VCC may be disturbed by noise or the like, the interrupt signals output from these comparators after the main power supply is turned off. And the reset signal generation time is not constant.

For example, as shown in FIG. 8, if the noise 30 is mixed during the fall of the main power supply VCC and the voltage waveform is disturbed, the data saving may fail.

In FIG. 8, the voltage of the main power supply VCC is 4.
When the voltage drops to 75 V, an interrupt signal T11 is output, and a data saving operation is started. Here, a series of data saved is 3 bytes of D0, D1, and D2. Normally, reset is normally performed at the timing of 32, and the data D0, D1, and D2 are all correctly written and backed up. However, in the case of FIG.
Is reset at the timing of 31.
At this timing, the data D0 is written but the data D1 and D2 are not written and the data saving fails.

When the main power supply VCC is subsequently turned on and the processing is performed using the saved data, an erroneous result occurs, and in some cases, the system goes out of control. Further, it is necessary to perform complicated processing to take measures.

[0021]

In order to solve the above-mentioned problems, a power supply voltage monitoring IC provided by the present invention monitors a main power supply voltage and, when the main power supply is turned off, converts a series of data consisting of a plurality of bytes. A backup voltage detection circuit for determining timing for storing and saving in a non-volatile memory and timing for resetting the system, wherein the backup voltage detection circuit detects that the main power supply voltage has dropped below the backup reference voltage; An output terminal for outputting the detection signal to an external device, an input terminal for receiving a reset permission signal generated after the external device that has received the detection signal has completed a predetermined data storage process, and a clock having the detection signal as a start signal A counter that counts pulses and generates a count-up signal after a lapse of a predetermined time during which data storage processing is completed; When at least one of the serial reset permission signal and the count-up signal is generated, characterized in that a gate circuit for outputting a reset signal to an external device.

When the main power supply voltage drops below the backup reference voltage, the microcomputer system incorporating the power supply voltage monitoring IC receives a detection signal output from the IC and receives a backup signal comprising a series of plural bytes. Means for storing data in a non-volatile memory, means for outputting a reset permission signal to the IC after the storage processing, and means for resetting the system by a reset signal output from the IC Is configured as

[0023]

FIG. 1 shows a power supply voltage monitoring I according to the present invention.
It is a figure showing an internal equivalent circuit of C33. In FIG.
Reference numeral 1 denotes a VCC terminal, which is connected to the main power supply of the system + 5V. Reference numeral 2 denotes a TC terminal for connecting an external capacitor, which determines the time for resetting an external device such as a microcomputer when the main power is turned on.

Reference numeral 34 denotes a RESIN terminal for inputting a reset permission signal from an external device, which is pulled down by a resistor 35. The input to the RESIN terminal 34 indicates that the reset is not permitted by a low level input and the reset is permitted by a high level input.

Reference numeral 36 denotes a CLK terminal for inputting a clock of a microcomputer or the like, and reference numeral 3 denotes a ground terminal 3 of the system.

Reference numeral 4 denotes a VOUT terminal for supplying power to a power supply terminal of a memory for saving data. The power supply is supplied from a VCC terminal 1 when the main power supply is on, and a VBAT terminal 5 when the main power supply is off.
Power is supplied from a backup power supply such as a battery connected to the power supply.

Reference numeral 6 denotes a CS bar terminal for outputting a backup control signal to the data saving memory. Reference numeral 7 denotes an INT terminal which outputs an interrupt signal for causing the microcomputer to save data when the main power supply voltage VCC drops to the backup reference voltage. A reset bar terminal 8 outputs a reset signal to an external device.

In the configuration shown in FIG. 1, the switching voltage detecting circuit 92 monitors the input voltage from the VCC terminal 1 by a comparator with hysteresis, and outputs a high level signal when the voltage is higher than 3.3 V, and outputs a high level signal when the voltage is higher than 3.3 V. If it is low, a low level signal is output.

When this high level signal is output, both the transistors 10 and 11 are turned on, and the voltage of the VCC terminal 1 is supplied to the VOUT terminal 4. When the low level signal is output, both the transistors 10 and 11 are turned off, and the voltage of the VBAT terminal 5 is supplied to the VOUT terminal 4 through the backflow preventing shet key barrier diode 12.

The backup voltage detecting circuit 91 monitors the input voltage from the VCC terminal 1 by a comparator with hysteresis, and outputs a low level signal when the voltage is lower than 4.75 V, and outputs a low level signal when the voltage is higher than 4.75 V. Outputs a high level signal. This low level signal is inverted by the Schmitt trigger input inverter 13 and output from the INT terminal 7 as an interrupt signal for instructing the external device to save data.

Reference numeral 15 denotes a constant current source which supplies a constant current to a capacitor which is externally connected to the TC terminal 2 and which determines a time for resetting an external device when the power is turned on.

Reference numerals 36 and 37 denote open collector or open drain buffers. Reference numeral 38 denotes a Fast Attack Slow Release peak hold circuit for holding a reset state. The buffer 36, after being cleared by a low level input to the CLR bar terminal, or after the main power supply VCC is turned on,
The output terminal OUT is kept at a low level (reset state holding signal) until the external capacitor connected to the TC terminal 2 is charged to a predetermined level.

Reference numeral 39 denotes a Schmitt trigger input inverter for inverting the output of the peak hold circuit 38. Numeral 40 denotes a NOR circuit which takes the logical sum of the reset permission signal input to the RESIN terminal 34 and the reset state holding signal of the peak hold circuit 38.

Reference numeral 41 denotes a gate circuit that outputs a reset signal to an external device via a circuit described later when any of a low level signal of the peak hold circuit 38, a reset permission signal, and a count-up signal is generated. , NOR
It is constituted by a logical sum circuit which takes the logical sum of the output of the circuit 40 and the count-up output of the counter 42.

Reference numeral 43 denotes an inverter for inverting the reset permission signal input to the RESIN terminal 34, and reference numeral 44 denotes a RESIN terminal 3
4 is a logical sum circuit for calculating the logical sum of the reset permission signal input to the counter 4 and the count-up output of the counter 42.

The counter 42 starts counting the clock input to the CLK terminal when the backup voltage detection circuit 91 outputs a low level, and counts the low level from the COUNT UP bar terminal when the count value reaches a predetermined value. Generates up output. This predetermined value is determined so that the time required for completing the data saving operation is secured. This count value is obtained when the low level output of the OR circuit 41 is R
Cleared by input to the ESET bar terminal.

FIG. 2 shows an internal equivalent circuit of the counter 42. 45 is a Schmitt trigger input inverter, 4
6, 47, 48, 49, 50, and 51 are NAND and 52
Is a counting circuit.

Returning to FIG. 1, the voltage obtained by inverting the output of the OR circuit 41 by the inverter 53 is divided by the resistors 17 and 18 to drive the transistor 19. That is, the transistor 19 is turned on when the OR circuit 41 outputs a low level signal, and sets the RESET bar terminal 8 to low level (reset signal to the system).

The output of the OR circuit 41 is a resistor 2
The transistor 23 is driven through 1 and 22. That is, the transistor 23 is turned off at the time of reset when the OR circuit 41 outputs a low-level signal, and the CS bar terminal 6 is set to the same voltage as the VOUT terminal 4 through the resistor 24, and is turned on when the OR circuit 41 outputs a high-level signal. To set the CS bar terminal 6 to low level.

When the output of the OR circuit 41 is high or low, the CS bar terminal 6 is at a low level and the RESET bar terminal 8 is at a high level (non-reset state). The state where the terminal 8 is at a low level (reset state) is switched.

The high / low state of the OR circuit 41 is determined under the following conditions. The reason why the output of the OR circuit 41 becomes low level and enters the reset state is when the peak hold circuit 38 outputs low level,
Either a case where a high-level reset permission signal is input to the ESIN terminal 34 or a case where the counter 42 outputs a low-level count-up signal. Becomes

The output of the OR circuit 41 becomes high level and enters the non-reset state when none of the above conditions is satisfied. A case where the conditions for determining the reset state are satisfied will be described.

When the peak hold circuit 38 outputs a low level signal, the power supply is turned on immediately after the main power supply VCC is turned on.
When the external capacitor connected to the terminal 2 has not been charged to the predetermined voltage, the OR circuit 44 which takes the logical sum of the reset enable signal and the count-up signal outputs a low level to clear the peak hold circuit 38. Is the case. At the time of this clearing, the low level output of the OR circuit 44 discharges the external capacitor connected to the TC terminal 2 via the buffer 37.
The output 8 changes from low level to high level only when the main power supply VCC becomes higher than 4.75 V and the backup voltage detection circuit 91 becomes high level when the external capacitor connected to the TC terminal 2 is connected. This is the case where the charging is continued to the predetermined voltage.

The high-level reset enable signal input to the RESIN terminal 34 is output after an external device such as a microcomputer that has received an interrupt signal for data saving from the INT terminal 7 completes the data saving process. Things.

The counter 42 outputs a low-level count-up signal because the backup voltage detection circuit 91 uses a low-level signal output when the voltage of the main power supply VCC falls below 4.75 V as a start signal.
The clock input from the K terminal 36 is counted, and this count value reaches a predetermined value determined to complete the data saving operation. Once the counting operation is started, even if the voltage of the VCC terminal 1 becomes higher than 4.75 V and the backup voltage detecting circuit 91 outputs a high level signal, the counting operation is not stopped, and the OR circuit 41
Is continued until a low level output is received.

FIG. 3 shows the power supply voltage monitoring IC of the present invention.
1 is a connection example of a microcomputer system in which is incorporated. In FIG. 3, reference numeral 33 denotes a power supply voltage monitoring IC;
Is a microcomputer, and 27 is a static RA which is a non-volatile memory by a battery backup.
M. Reference numeral 28 denotes a battery serving as a backup power supply.
Connected to BAT terminal 5. An external capacitor 29 determines the reset time when the main power is turned on, and is connected to the TC terminal 2.

When the main power supply VCC drops below the backup reference voltage, the microcomputer 26 receives a voltage drop detection signal output from the power supply voltage monitoring IC 33 and stores a series of backup data consisting of a plurality of bytes in a nonvolatile manner. Means for storing the data in the memory 27, a means for outputting a reset permission signal to the power supply voltage monitoring IC after the storage processing, and a reset operation of the system by the reset signal output from the power supply voltage monitoring IC. Reset means for performing the following.

INT of power supply voltage monitoring IC 33 of the present invention
Terminal 7 is an interrupt input IN of the microcomputer 26
It is connected to the TPn terminal. The RESIN terminal 34 receiving the reset permission signal is connected to the output port Pm terminal. The RESET bar terminal 8 for outputting the reset signal is pulled up and connected to the RESET bar terminal of the microcomputer 26. The CLK terminal 36 is connected to the CLKOUT terminal of the microcomputer 26. The CS bar terminal 6 is a C for backup control of the memory 27.
Connected to E1 bar terminal. The VOUT terminal 4 is connected to the VCC terminal of the memory 27.

The address bus A15... 0 terminal and the data bus D7.
The terminals are connected to the address bus A15... 0 terminals and the data bus D7.

The RD bar terminal of the microcomputer 26 for controlling the data reading is connected to the OE bar terminal for controlling the data output of the memory 27, and the WR bar terminal for controlling the data writing is controlled by the data writing control of the memory 27. WE bar terminal.

The external device selection CS terminal of the microcomputer 26 is connected to the chip selection CE2 terminal of the memory 27.

Next, the operation of the circuits shown in FIGS. 1 and 3 will be described. When the main power supply VCC starts up, the power supply voltage monitoring IC 33
When the voltage of the main power supply VCC rises to 3.3 V, the power supply to the non-volatile memory 27 is switched from the backup power supply 28 to the main power supply VCC by the high level output of the switching voltage detection circuit 92. When the main power further rises to 4.75 V, the output of the backup voltage detecting circuit 91 goes high. Due to this high level signal, the output of the buffer 36 becomes high impedance and the output of the buffer 37 is also high impedance, so that the capacitor 29 connected to the TC terminal 2 is charged from the constant current source 15.

Until the capacitor 29 is charged to a predetermined voltage, the voltage of the output OUT of the peak hold circuit 38 is low.
A reset signal is output from the ESET bar terminal 8 to hold the microcomputer 26 in a reset state. When a predetermined time has elapsed and the voltage of the capacitor 29 rises, the voltage of the output OUT of the peak hold circuit 38 rises and the output of the inverter 39 goes low. This gives R
The ESET bar terminal 8 becomes high impedance, the reset terminal of the microcomputer 26 pulled up becomes high level, the reset is released, and the operation starts.

After reset release, the microcomputer 2
Reference numeral 6 reads a series of data of a plurality of bytes from the memory 27 and performs a calculation process using the read data.

After the calculation process is completed, the calculation result is written into the static RAM 27. The microcomputer 26 is
This process is repeated.

Thereafter, when the backup voltage detecting circuit 91 detects a voltage drop of the main power supply VCC when the main power supply is turned off,
Data saving and resetting are performed according to the procedure shown in the control flowchart of FIG.

The voltage drop detection signal of the backup voltage detection circuit 91 is output from the INT terminal 7 to the INTPn terminal of the microcomputer 26 via the Schmitt trigger input inverter 13 as a high-level interrupt signal.

The microcomputer 26 that has received the data save interrupt signal starts an interrupt process and performs a data save process. For example, as shown in FIG. 5, assuming that the microcomputer 26 generates the fifth byte of a series of 10-byte data into the memory 27 as shown in FIG. 5 byte data in memory 27
Write to immediately.

After all data has been written, a reset such as NOP processing is performed to obtain a good state, and a high-level reset permission signal is output from the output port Pm terminal to the RESIN terminal of the power supply voltage monitoring IC 33. Power supply voltage monitoring IC33
, The transistor 19 is turned on through the NOR circuit 40, the OR circuit 41, and the inverter 53, and the RESET bar terminal 8 is set to the ground output state. The microcomputer 26 resets this signal.
Reset by receiving on the bar terminal.

At this time, the transistor 23 is turned off, and the CS terminal 6 outputs a high-level signal to the C
Output to the E1 bar terminal. The reset permission signal passes through the inverter 43 and the OR circuit 44 to output the buffer 37 to the ground, and at the same time, the peak hold circuit 3
8 CLR bar terminals. As a result, TC
At the same time as discharging the external capacitor connected to the terminal 2, the peak hold circuit 38 is cleared, and the output voltage of the peak hold circuit 38 is set to 0V.

The voltage drop signal output from the backup voltage detecting circuit 91 is output to the INT terminal 7 and at the same time, is input to the counter 42 as a count start signal.
To count. Therefore, this counter 42
If the reset permission signal is not input before the count-up is performed, this count-up output is output to the microcomputer as a reset signal through the OR circuit 41, the inverter 53, and the transistor 19, and at the same time, the OR circuit is output. Through 44, the peak hold circuit 38 is cleared.

As described above, since the counter 42 is provided, even if the power supply monitoring IC 33 of the present invention is incorporated in a system that does not control the reset permission signal, a series of plural bytes must be output before resetting when the main power supply is turned off. Can be reliably stored in the non-volatile memory 27, and runaway of the system can be prevented.

Since the counter 42 is reset by the low level signal (reset signal) output from the OR circuit 41, when the output of the peak hold circuit 38 is at a low voltage, when the reset permission signal is input, In both cases when the count-up output is performed, the count value is cleared and the initial state is established.

When the voltage further drops to 3.3 V, the memory 2
7 is supplied from the main power supply VCC to the backup power supply 2
8 and continues even if the main power supply VCC is no longer supplied to the power supply voltage monitoring IC 33.

When the main power supply VCC is turned on again,
When the voltage of the main power supply VCC rises to 3.3V,
The power supply to the nonvolatile memory 27 is switched from the backup power supply 28 to the main power supply VCC. When the power supply rises to 4.75 V, the CE1 bar terminal CS of the memory 27 storing the save data is set to the low level to release the reset. I do.
By this reset release, the operation is resumed by the saved data.

The reference voltage for distinguishing between high and low of the switching voltage detecting circuit 92 and the backup voltage detecting circuit 91 is set to an appropriate value depending on the voltage level of the system.

According to the present invention, a kind of delay is applied to the generation of the reset signal when the main power supply VCC is off.
It is necessary to design a power supply capacity for maintaining the power supply voltage so that the external device can operate until all the backup data has been written.

[0068]

As described above, the power supply voltage monitoring IC according to the present invention has the following conditions for outputting a reset signal to an external device such as a microcomputer when the main power supply VCC is off.
When a reset permission signal generated after the external device stores a series of data of a plurality of bytes in the non-volatile memory is output, or after the data saving instruction is issued, the data saving / storing is completed. Since any one of the cases where the passage of time is counted is performed, even if the main power supply is cut off under any conditions, a series of data can be all written without error, and it is possible to prevent runaway of the system.

[Brief description of the drawings]

FIG. 1 is a diagram showing an internal equivalent circuit of an embodiment of a power supply voltage monitoring IC of the present invention.

FIG. 2 is an internal block diagram of a counter (42) of FIG.

FIG. 3 is a diagram showing an example in which the power supply voltage monitoring IC of FIG. 1 is incorporated in a microcomputer system.

FIG. 4 is a flowchart showing an operation from a time when a main power is turned off to a time when the system is reset in the system shown in FIG. 3;

FIG. 5 is a diagram showing an example of output waveforms of each terminal when the main power supply is turned off in the system of FIG. 3;

FIG. 6 is a diagram showing an internal equivalent circuit of a conventional power supply voltage monitoring IC.

FIG. 7 is a diagram showing a connection example of a microcomputer system using a conventional power supply voltage monitoring IC.

8 is an output waveform diagram of each terminal when noise is mixed when the main power supply VCC is turned off in the system of FIG. 7;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Main power supply terminal 2 Connection terminal of external capacitor for setting reset time 3 Ground terminal 4 Power supply terminal to nonvolatile memory 5 Backup power supply terminal 6 Terminal for supplying backup control signal to nonvolatile memory 7 Output terminal of interrupt signal for commanding data saving / storing 8 Output terminal of reset signal 91 Backup voltage detection circuit 92 Switching voltage detection circuit 10, 11 Switching power supply from main power supply VCC and backup power supply to non-volatile memory Supplying transistor 12 Schottky barrier diode 13, 39, 45 Inverter with Schmitt trigger 15 Constant current source 17, 18, 21, 22, 24, 35 Resistance 19, 23 Transistor 26 External device (microcomputer) 27 Non-volatile memory (Static AM) 28 Backup power supply (battery) 29 Capacitor that determines reset time 30 Noise on main power supply waveform 31 Reset signal output due to noise 32 Reset signal output in the absence of noise 33 Power supply voltage monitoring IC 34 Reset Input terminals 36 and 37 for the enable signal 36 and 37 Open collector buffer 38 Fast Attack Slow Release peak hold circuit 40 NOR circuit 41 Gate circuit (OR circuit) 44 OR circuit 42 Counter 43, 53 Inverter 46, 47, 48, 49, 50, 51 NAND circuit 52 Counter circuit

Claims (2)

[Claims] 1. A power supply voltage monitor for monitoring a main power supply voltage and determining a timing for storing and saving a series of data of a plurality of bytes in a non-volatile memory when the main power supply is turned off and a timing for resetting a system. A backup voltage detection circuit for detecting that the main power supply voltage has dropped below the backup reference voltage, an output terminal for outputting the detection signal to an external device, and an external device for receiving the detection signal. An input terminal for receiving a reset permission signal generated after completing a predetermined data storage process, and counting the clock pulse using the detection signal as a start signal, and generating a count-up signal after a predetermined period of time when the data storage process is completed. And at least one of the reset permission signal and the count-up signal occurs. , Power supply voltage monitor IC that includes a gate circuit that outputs a reset signal to an external device. 2. A power supply voltage monitoring IC according to claim 1, wherein when the main power supply voltage falls below a backup reference voltage, a detection signal output from the IC is received, and a series of a plurality of bytes are received. Means for storing backup data in a non-volatile memory, means for outputting a reset permission signal to the IC after the storage processing, and reset for performing a system reset operation by a reset signal output from the IC. A microcomputer system comprising means.