JPH10198447A - Band gap reference circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a high-accuracy band gap reference circuit with which an output voltage is fixed even in the case of fluctuation in a power supply potential by composing the circuit of MOS type transistors. SOLUTION: The respective gate lengths and gate width of respective PMOS transistors P1-P6 are set to be equal, for example, the gate length of NMOS transistor N2 is sized equal with that of N1 and the gate width is set to be M-fold as well. Further, since the gate lengths and gate width of NMOS transistors N1 and N3 are set equal respectively, a reference voltage Vref reducing power supply potential VDD dependency can be generated. Namely, even when a power supply potential VDD is further increased in comparison with a ground potential GND, the drain/source voltage of PMOS transistor P3 becomes equal to the gate/source voltage of PMOS transistor P2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a band gap reference circuit, and more particularly to a CMOS (Comp
elementary Metal-Oxide Sem
The present invention relates to a power-supply-independent band gap reference circuit mounted on an insulator type semiconductor device.

[0002]

2. Description of the Related Art Referring to FIG. 5, which shows an example of a conventional band gap reference circuit of this type, a high-potential power supply potential (hereinafter referred to as a power supply potential) VDD and a low-potential power supply potential (hereinafter, referred to as a power supply potential). A first series connection in which a P-channel MOS transistor (hereinafter referred to as a P-type MOS transistor) P1 and an N-type MOS transistor (hereinafter referred to as an N-type MOS transistor) N1 are connected in series between GND. Circuit, a P-type MOS transistor P2 and an N-type MOS transistor between a power supply potential VDD and a ground potential GND.
A second series connection circuit in which an S transistor N2 and a resistance element R1 are connected in series; a P-type MOS transistor P3 and a resistance element R2 between a power supply potential VDD and a ground potential GND;
And a third series-connected circuit in which a diode having the resistor element side as an anode is connected in series, and a gate electrode of the P-type MOS transistor P1, a gate electrode and a drain electrode of the P-type MOS transistor P2, and a P-type The gate electrode of the MOS transistor P3 is commonly connected, and
The gate electrode and the drain of the N-type MOS transistor N1 are commonly connected to the gate of the N-type MOS transistor N2, and the drain electrode of the P-type MOS transistor P3 is connected to the output terminal of the ref voltage. A potential between the output terminal and the ground potential GND is defined as a reference voltage Vref (hereinafter, referred to as a reference voltage Vref).

In the band gap reference circuit having the above-described configuration, the P-type MOS transistor P
1, the gate length and gate width of P2 and P3 are the same size, and the gate length of N2 is the same size for N-type MOS transistor N1, and the gate width is M
(M is a natural number other than 0) times, ideally, the reference position pressure Vref can be expressed by the following equation.

Vref = N ・ (k ・ T / q) ・ lnM + VF (D1) (1) where N; (resistance of R2) / (resistance of R1) q; charge of electron Quantity, k: Boltzmann's constant, T: absolute temperature VF (D1); forward voltage of D1.

On the other hand, another example of a conventional band gap reference circuit is disclosed in Japanese Patent Application Laid-Open No. 58-76918. Referring to FIG. 6 which shows a circuit diagram of the band gap reference circuit described in the publication, this circuit includes a current mirror circuit section 3, an output circuit section 4 thereof, and an output terminal 5 for a Vref voltage output from the output circuit. Consists of The current mirror circuit section 3 includes PNP transistors Q1 and NP between a power supply potential VCC and a ground potential GND.
PNP between a first series connection circuit in which N transistors Q5 are connected in series and power supply potential VCC and ground potential GND
A second series connection circuit in which the transistor Q2 and the NPN transistor Q6 are connected in series; an emitter electrode connected to the power supply potential VCC; a base electrode commonly connected to the base electrodes of the PNP transistors Q1 and Q2; A PNP transistor Q3 connected to terminal 5 and PNP transistors Q1 and Q
2 and Q3, the collector electrode is connected to ground potential GND, and the base electrode is connected to P
A PNP transistor Q4 connected to the base electrode of the NP transistor Q2, the emitter electrodes of the NPN transistors Q5 and Q6 are commonly connected,
The base electrode of the PN transistor Q6 is connected to the collector electrode of the PNP transistor Q1.

The output circuit section 4 has a resistance element R3, an NPN transistor Q7 and a resistance element R2 connected in series between the collector electrode of the PNP transistor Q3 of the current mirror circuit section 3 and the ground potential GND.
Is connected to the emitter electrode of NPN transistor Q6, the collector electrode of NPN transistor Q7 is further connected to the base electrode of NPN transistor Q8, the collector electrode of NPN transistor Q8 is connected to output terminal 5, and the emitter electrode is connected to It is connected to the ground potential GND, and extracts the sum of the voltage between the terminals of the resistor R3 of the output circuit unit 4 and the voltage between the base and the emitter of the NPN transistor Q8 as an output voltage Vref.

In the band gap reference circuit having the above configuration, the PNP transistors Q1 and Q
2 and Q3 with the same emitter area, NPN
If the emitter area of transistor Q5 is set to M times the emitter area of NPN transistor Q7, reference voltage Vr
ef can be expressed by the following equation.

Vref = N × (k × T / q) × lnM + VF (D1) (1) where N; (resistance of R3) / (resistance of R2) q; Quantity, k: Boltzmann's constant, T: absolute temperature VF (Q8); forward voltage of Q8.

[0009]

In the above-described conventional band gap reference circuit shown in FIG. 5, when the power supply potential VDD fluctuates, the reference voltage Vre is changed.
There is a problem that f also changes.

The reason is that, for example, when the power supply potential VDD becomes higher than the ground potential GND, the voltage between the drain and source electrodes of the P-type MOS transistor P1 increases,
As a result, the drain current flowing into the N-type MOS transistor N1 increases due to the Early effect.

As a result, the N-type MOS transistor N1 forming a mirror together with the N-type MOS transistor N1
2, the drain current of the P-type MOS transistor P2 also increases with the current due to the Early effect of itself.

Accordingly, the P-type MOS transistor P which forms a mirror together with the P-type MOS transistor P2
The drain current of No. 3 also increases. This current increase is represented by Δid
(1). Further, the drain current increases due to the Early effect of the P-type MOS transistor P3 itself. Assuming that the current increase is Δid (2), Δid is as follows: Δid = Δid (1) + Δid (2)... (3).

When the current Δid flows into the resistance element R2 and the diode D1, the reference voltage Vref fluctuates. If this variation is ΔVref, it can be expressed by the following equation.

Vref = Δid × R2 + (k × T / q) × ln {(Δid + IDS (P3)) / IDS (P3)} (4) where (4) , IDS (P3); the drain current before receiving the power supply potential dependence of P3.

In another example of the conventional band gap reference circuit shown in FIG. 6 described above, since the transistors Q1 and Q2 together form the current mirror circuit 3, the collector electrode of the PNP transistor Q1 is formed. Although the same amount of collector current flows as the transistor Q2, the collector current of the PNP transistor Q2 is equal to the collector current flowing into the transistor Q6.

Next, if the power supply potential VCC rises and the collector current of the PNP transistor Q2 increases, the current flowing through the resistance element R1 increases and the emitter-base voltage VBE of the NPN transistor Q5 increases. The collector current of NPN transistor Q5 increases. As a result, the base potential of NPN transistor Q6 is lowered, and NPN transistor Q6
Operates so as to reduce the collector current.

Therefore, the current mirror circuit 3 including the PNP transistors Q1 and Q2 flows out a substantially constant current even if the power supply potential VCC changes, and this current is mirrored by the PNP transistor Q3.
Of the NPN transistor Q8 and the current flowing into the resistance element R3 are also constant.

Therefore, the second term of the above-mentioned equation (2), NP
Forward voltage of N transistor Q8 (hereinafter, VF (Q8)
) Is substantially constant even when the power supply potential VCC changes, and the first term of the equation (2) is also determined by the constants N and M. Therefore, the first term is constant even when the power supply potential VCC changes.
This band gap reference circuit is constant even when the power supply potential VCC changes.

However, in the circuit configuration of another example of the above-described conventional circuit, although the bipolar transistor for driving the base current is effective, the MO for driving the gate voltage is effective.
This is not feasible for S transistors.

An object of the present invention has been made in view of the above-mentioned drawbacks of the prior art, and comprises a MOS transistor, and furthermore, a high-precision band gap reference which has a constant output reference voltage even when the power supply potential fluctuates. It is to provide a circuit.

[0021]

SUMMARY OF THE INVENTION A feature of the band gap reference circuit of the present invention is that a band gap for obtaining a constant reference voltage from a given high-side first power supply and a low-side second power supply.・ In the reference circuit,
One end of each of the first, second, third and fourth field effect transistors of the first conductivity type is commonly connected to a first power supply, and the other end of the first field effect transistor of the first conductivity type Is connected to one end and a gate electrode of a first field-effect transistor of the second conductivity type, and the other end of the first transistor of the second conductivity type is connected to a second power supply. The gate electrodes of the first, second and third field effect transistors are commonly connected to the other end of the second field effect transistor of the first conductivity type and one end of the second field effect transistor of the second conductivity type, respectively. And the second
A gate electrode of a second field-effect transistor of the conductivity type is connected to a gate electrode of the first transistor of the second conductivity type, and the other end of the second field-effect transistor of the second conductivity type and a second power supply A first resistance element is connected therebetween, and the other end of the third field effect transistor of the first conductivity type is connected to the first resistance element.
Connected to one end of a conductive fifth field effect transistor,
The other end of the fourth field effect transistor of the first conductivity type is connected to one end of a sixth field effect transistor of the first conductivity type, and a gate electrode and a drain electrode of the transistor are connected to the fifth field effect transistor of the first conductivity type. And the other end of the third field-effect transistor of the second conductivity type is connected to a second power supply. A second resistance element and a diode element having the resistance element side as an anode electrode side are connected in series between the other end of the fifth field effect transistor of the first conductivity type and a second power supply; The other end of the conductive fifth transistor is used as a reference voltage output terminal.

Further, even when the predetermined potential of the first power supply changes to a higher potential, the gate-source voltages of the second and third field effect transistors of the first conductivity type become equal. As described above, the first, second, third, fourth, fifth, and sixth field effect transistors of the first conductivity type have the same gate length and gate width, and the first conductivity type first, second, third, fourth, and fifth field effect transistors have the same gate length and first width. The gate length of the second transistor of the second conductivity type is equal to the gate width of the second transistor of the second conductivity type, and the gate width of the second transistor of the second conductivity type is the same as that of the first transistor of the second conductivity type. The gate length and the gate width are set to equal values.

Further, instead of the direct connection with the other end of the first field-effect transistor of the first conductivity type and one end of the first field-effect transistor of the second conductivity type, a seventh field-effect transistor of the first conductivity type is used. A field effect transistor may be inserted in a series connection state, and a gate electrode of the seventh field effect transistor of the first conductivity type may be connected to a gate electrode of the fifth field effect transistor of the second conductivity type.

Further, even when the predetermined power supply potential changes to a higher potential, the first conductivity type first
And the first, second, third, fourth, fifth, sixth and seventh electric fields of the first conductivity type so that the respective gate-source voltages of the second field effect transistor are equal. The gate length and the gate width of each of the effect transistors are equal, and the gate length of the second transistor of the second conductivity type is equal to that of the first transistor of the second conductivity type. The gate length and the gate width of the second transistor of the second conductivity type are set to be equal to those of the first transistor of the second conductivity type.

Also, instead of a direct connection with the other end of the second field effect transistor of the first conductivity type and one end of the second field effect transistor of the second conductivity type, a depletion type second conductivity type transistor is used. A fourth field-effect transistor is inserted in a series connection state, and the gate electrode of the fourth field-effect transistor of the second conductivity type is connected to the gate electrode of the second field-effect transistor of the second conductivity type. Good.

Further, even when the predetermined power supply potential fluctuates to a higher potential, the potential difference corresponding to this fluctuation is determined by the drain / drain potential of the fourth field effect transistor of the second conductivity type.
The first, second, third, fourth, fifth, sixth, and seventh field-effect transistors of the first conductivity type have the same gate length and gate width so as to absorb between the sources, and The gate length of the second transistor of the second conductivity type is equal to that of the first transistor of the second conductivity type, the gate width is M times larger, and the second transistor of the second conductivity type is the same as that of the first transistor of the second conductivity type. The gate length of the depletion type fourth transistor of the second conductivity type is set to a value equal to the gate length and gate width of the third transistor of the type and longer than a predetermined value.

Furthermore, a depletion type second conductivity type transistor is used instead of the direct connection with the other end of the first conductivity type sixth field effect transistor and one end of the second conductivity type third field effect transistor. Is connected in series, and the gate electrode of the fifth field effect transistor of the second conductivity type is connected to the gate electrode of the fourth field effect transistor of the second conductivity type of the depletion type. You may connect.

Further, even when the predetermined power supply potential changes to a higher potential, the potential difference corresponding to the change is absorbed between the drain and the source of the depletion type fifth field effect transistor of the second conductivity type. And the first
The first, second, third, fourth, fifth, sixth and seventh field effect transistors of the conductivity type have the same gate length and gate width, and are different from the first transistor of the second conductivity type. The second transistor of the second conductivity type has the same gate length and the gate width M times that of the second transistor of the second conductivity type, and the gate length and the gate of the third transistor of the second conductivity type are different from those of the first transistor of the second conductivity type. The gate length of the fourth transistor of the second conductivity type and the gate length of the fifth transistor of the second conductivity type of the depletion type are set to values equal to each other and longer than a predetermined value.

[0029]

Embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram showing a first embodiment of the present invention. Referring to FIG. 1, power supply potential VD
A first series connection circuit in which a P-type MOS transistor P1 and an N-type MOS transistor N1 whose drain and gate are connected between D and a ground potential GND, and a P-type MOS transistor P1 between a power supply potential VDD and the ground potential GND; N-type MOS in which MOS transistor P2 is connected between drain and gate
A second series connection circuit in which a transistor N2 and a resistor R1 are connected in series; a P-type MOS transistor P3, a P-type MOS transistor P5, a resistor R2, and an anode connected to the resistor R2 between the power supply potential VDD and the ground potential GND; A third series-connected circuit in which a diode D1 is connected in series;
A P-type MOS transistor P4 having a gate and a drain connected between the power supply potential VDD and the ground potential GND, and a gate
A fourth series connection circuit in which a P-type MOS transistor P6 whose drains are connected and an N-type MOS transistor N3 are connected in series; These series connected circuits are
The gate electrodes of the P-type MOS transistors P1, P2 and P3 are commonly connected, and the N-type MOS transistor N
1, the gate electrodes of N2 and N3 are commonly connected, the gate electrodes of P-type MOS transistors P5 and P6 are commonly connected, and the reference voltage Vref is applied to the output terminal ref from the drain electrode of P-type MOS transistor P5. It is configured to take out.

In the above-described band gap reference circuit, for example, the gate length and gate width of each of the P-type MOS transistors P1 to P6 are set to be equal, and the N-type MOS transistor N
With respect to 1, the gate length of N2 is set to be the same size, and the gate width is also set to be M times. Further, since the gate lengths and the gate widths of the N-type MOS transistors N1 and N3 are set to be equal to each other, the reference voltage Vre having little dependency on the power supply potential VDD is set.
f can be generated.

That is, the power supply potential VDD is changed to the ground potential GND.
, The drain-source voltage of the P-type MOS transistor P3 (hereinafter, referred to as VDS (P3)) and the gate-source voltage of the P-type MOS transistor P2, as shown in the following equation. (Hereafter, VGS
(Referred to as (P2)).

VDS (P3) = VG (P5) −VGS (P5) = VG (P6) −VGS (P6) = VGS (P4) = VGS (P2) (5) VG (P5); gate potential of P5 with respect to power supply potential VDD VGS (P5); gate-source voltage of P5 VG (P6); gate potential of P6 with respect to power supply potential VDD VGS (P6); gate-source voltage of P6 VGS (P4); The gate-source voltage of P4.

Therefore, the current increase due to the Early effect of the P-type MOS transistor P3 is eliminated, and as a result,
The second term on the right side of the equation (3) is Δid (2) = 0........... The variation ΔVref of the reference voltage Vref is reduced. The same effect can be obtained even if the gate length and gate width of each of P4, P5, and P6 are arbitrarily set.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention. Referring to FIG. 2, the difference from the first embodiment is that a P-type MOS transistor P7 is connected in series instead of the series connection between P-type MOS transistor P1 and N-type MOS transistor N1 shown in FIG. And the gate electrode of the P-type MOS transistor P7 is
That is, it is connected to the gate of the type MOSP6. The other components are the same, and the same components are denoted by the same reference numerals and description thereof will be omitted.

In the band gap reference circuit of the second embodiment, for example, the gate length and the gate width of each of the P-type MOS transistors P1 to P7 are set to be equal, and the N-type MOS transistor N1 is set. , The gate length of N2 is also set to be the same size, and the gate width is also set to be M times. Further, N-type MOS transistors N1 and N3
Are set so as to be equal to each other, it is possible to generate the reference voltage Vref with even less dependence on the power supply potential VDD.

That is, the power supply potential VDD and the ground potential G
Even when the voltage between ND and ND is further increased, the voltage between the drain and source of the P-type MOS transistor P1 (hereinafter, referred to as VDS (P1)) and the P-type
The gate-source potential of the S transistor P2 (hereinafter referred to as V
GS (P2)).

VDS (P1) = VG (P6) −VGS (P7) = VG (P6) −VGS (P6) = VGS (P4) = VGS (P2) (7) where: VG (P6): Gate potential of P6 with respect to power supply potential VDD VGS (P7); Gate-source voltage of P7 VGS (P6); Gate-source voltage of P6 VGS (P4); Gate-source voltage of P4 I do.

Therefore, since the current increase due to the Early effect of the P-type MOS transistor P1 is eliminated, (3)
The first term on the right side of the equation becomes smaller, and the variation ΔVref of the reference voltage Vref shown in equation (4) also becomes smaller.

FIG. 3 is a circuit diagram showing a third embodiment of the present invention. Referring to FIG. 3, the difference from the second embodiment is that an N-type MOS transistor N4 is connected in series instead of the series connection between P-type MOS transistor P2 and N-type MOS transistor N2 shown in FIG. The N-type MOS transistor N4 is formed of a depletion type MOS transistor, and the gate electrode is connected to the gate electrode of the N-type MOS transistor N1. The other components are the same, and the same components are denoted by the same reference numerals and description thereof will be omitted.

In the band gap reference circuit according to the third embodiment, for example, the gate length and the gate width of each of the P-type MOS transistors P1 to P7 are set to be equal, and the N-type MOS transistor N2 has the same gate length as N1
Each is set so that the gate width becomes M times. Further, the gate lengths and the gate widths of the N-type MOS transistors N1 and N3 are set to be equal to each other, and the gate length of the depletion-type N-type MOS transistor N4 is set to a certain length for preventing leakage. Reference voltage Vr with less dependency on power supply potential VDD
ef can be generated.

That is, the power supply potential VDD and the ground potential G
Even if the voltage between ND fluctuates to the higher side, the voltage between the drain and source of the N-type MOS transistor N2 (hereinafter, VDS
(Referred to as (N2)) is derived from the gate-source voltage of the N-type MOS transistor N4 (hereinafter referred to as VGS (N4)) from the gate-source potential of the N-type MOS transistor N1 (hereinafter referred to as VGS (N1)). The power supply potential VDD fluctuates in the higher direction.
Absorption occurs between the drain and source of this N-type MOS transistor N4.

Accordingly, since the current increase due to the Early effect of the N-type MOS transistor N2 is eliminated, (3)
The first term on the right side of the equation becomes smaller, and the variation ΔVref of the reference voltage Vref shown in equation (4) also becomes smaller.

FIG. 4 is a circuit diagram showing a fourth embodiment of the present invention. The difference from the third embodiment is that an N-type MOS transistor N5 is inserted in series instead of the series connection between the P-type MOS transistor P6 and the N-type MOS transistor N3 shown in FIG. That is, the type MOS transistor N5 is formed of a depletion type MOS transistor, and the gate electrode is connected to the gate electrode of the N type MOS transistor N1.

The other components are the same, and the same components are denoted by the same reference characters and description thereof will not be repeated.

In the band gap reference circuit according to the fourth embodiment, for example, the gate lengths and the gate widths of the P-type MOS transistors P1 to P7 are set to be equal, and the N-type MOS transistor N1 is set. Are set so that the gate length of N2 is the same size and the gate width is M times. Further, the gate lengths and the gate widths of N-type MOS transistors N1 and N3 are set to be equal, and the gate lengths of depletion-type N-type MOS transistors N4 and N5 are set to be somewhat longer to prevent leakage. Therefore, the reference voltage Vref that does not depend on the power supply potential VDD can be generated.

That is, the power supply potential VDD is changed to the ground potential GND.
, The drain-source voltage of the N-type MOS transistor N3 (hereinafter, VDS (N2)
) Is equal to the gate-source voltage (hereinafter, referred to as VGS (N4)) of the N-type MOS transistor N5 from the gate-source potential of the N-type MOS transistor N1 (hereinafter, referred to as VGS (N1)). Determined by the reduced voltage,
The amount by which the power supply potential VDD fluctuates to the higher side
It is absorbed between the drain and source of the S transistor N5.

That is, since the current increase due to the Early effect of the N-type MOS transistor N3 is eliminated, (3)
The first term on the right side of the equation is Δid (1) = 0......... The expression (3) is obtained by combining the expression (6) with the expression (3). Δid = Δid (1) + Δid (2)... (9) Therefore, ΔVref = Δid × R2 + (k × Y / q) × ln ｛(Δid + IDS (P3)｝ = 0 (10), and the variation ΔVref of the reference voltage Vreff is eliminated.

[0048]

As described above, according to the present invention, the source electrodes of the first, second, third, and fourth P-type MOS transistors are commonly connected to the power supply potential, and the first P-type MOS transistor is connected. The first N-type M
The first, second and third P-type MOS transistors are connected to the drain electrode and the gate electrode of the OS transistor, and the source electrode of the first N-type MOS transistor is connected to the power supply potential.
A gate electrode of each of the S transistors and a second P-type MOS
The drain electrode of the transistor and the drain electrode of the second N-type MOS transistor are commonly connected, and the gate electrode of the second N-type MOS transistor is connected to the first.
Connected to the gate electrode of the N-type MOS transistor of
Connecting the first resistance element between the source electrode of the N-type MOS transistor and the ground potential, connecting the drain electrode of the third P-type MOS transistor to the source electrode of the fifth P-type MOS transistor, The drain electrode of the P-type MOS transistor is connected to the source electrode of the sixth P-type MOS transistor, the gate electrode and drain electrode of this transistor, the gate electrode of the fifth P-type MOS transistor, and the source of the third N-type MOS transistor. And the source electrode of the third N-type MOS transistor is connected to the power supply potential.
A second resistance element and a diode element having this resistance element side as the anode electrode side are connected in series between the drain electrode of the MOS transistor and the ground potential,
M having the drain electrode of the transistor as a reference voltage output terminal
The first, second, third, and third transistors are constituted by OS transistors so that the gate-source voltages of the second and third P-type MOS transistors are equal even when the power supply potential changes to a higher potential. The gate length and gate width of each of the fourth, fifth and sixth P-type MOS transistors are equal, and the gate length of the second N-type MOS transistor is equal to that of the first N-type MOS transistor. Since the gate length and the gate width of the third N-type MOS transistor are set equal to those of the first N-type MOS transistor by a factor of M, respectively, there is no variation ΔVref of the reference voltage Vref with respect to the power supply potential variation. A highly accurate band gap reference circuit can be obtained.

Further, a seventh P-type MOS transistor is provided between the drain electrodes of the first P-type MOS transistor and the first N-type MOS transistor, and a second P-type MOS transistor is provided.
A depletion-type fourth N-type MOS transistor is connected between the drain electrodes of the S transistor and the second N-type MOS transistor, and a drain electrode between each of the sixth P-type MOS transistor and the third N-type MOS transistor. , The first, second, third, fourth, fifth, sixth and seventh P-type MOS transistors may be independently or entirely inserted with depletion-type fifth N-type MOS transistors. Have the same gate length and gate width, and the gate length of the second N-type MOS transistor is equal to that of the first N-type MOS transistor, the gate width is M times larger than that of the first N-type MOS transistor. The gate lengths of the fourth and fifth N-type MOS transistors are set equal to the gate length and gate width of the third N-type MOS transistor. Long, since each is set, the same effect can be obtained.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a third embodiment of the present invention.

FIG. 4 is a circuit diagram showing a fourth embodiment of the present invention.

FIG. 5 is a circuit diagram of an example of a conventional circuit.

FIG. 6 is a circuit diagram of another example of a conventional circuit.

[Explanation of symbols]

 P1 to P7 P-type MOS transistor N1 to N5 N-type MOS transistor R1 to R3 Resistance element D1 Diode Q1 to Q4 PNP transistor Q5 to Q8 NPN transistor

Claims (8)

[Claims] 1. A band gap reference circuit for obtaining a constant reference voltage from a given first power supply on a higher side and a second power supply on a lower side, wherein the first, second, and second conductive types of the first conductivity type are provided. One end of each of the third and fourth field-effect transistors is commonly connected to a first power supply, and the other end of the first field-effect transistor of the first conductivity type is connected to the first field-effect transistor of the second conductivity type. And the other end of the first transistor of the second conductivity type is connected to a second power supply, and the first, second, and third field effect transistors of the first conductivity type are connected to each other. Each of the gate electrodes, the other end of the second field-effect transistor of the first conductivity type and one end of the second field-effect transistor of the second conductivity type are connected in common, respectively, and the second of the second conductivity type is Field effect transistor Is connected to the gate electrode of the first transistor of the second conductivity type, and a first resistance element is connected between the other end of the second field effect transistor of the second conductivity type and a second power supply. The other end of the third field effect transistor of the first conductivity type is connected to one end of a fifth field effect transistor of the first conductivity type, and the other end of the fourth field effect transistor of the first conductivity type. Is connected to one end of a sixth field effect transistor of the first conductivity type, the gate electrode and the drain electrode of this transistor, the gate electrode of the fifth transistor of the first conductivity type, and the third electric field of the third conductivity type. The other end of the third field effect transistor of the second conductivity type is connected to a second power supply, and the other end of the third field effect transistor of the first conductivity type is connected to one end of the fifth field effect transistor of the first conductivity type. End and end A second resistance element and a diode element having the resistance element side as the anode electrode side are connected in series between the second power sources, and the other end of the first transistor of the first conductivity type is used as a reference voltage output terminal. A band gap reference circuit, characterized in that: 2. The method according to claim 1, wherein the first and second field-effect transistors of the first conductivity type have respective gates even when the predetermined potential of the first power supply changes to a higher potential.
The first, second, third, fourth, fifth and sixth field-effect transistors of the first conductivity type have the same gate length and gate width so that the source-to-source voltages are equal, and For the first transistor of the two conductivity type, the second transistor is used.
The second transistor of the second conductivity type is different from the first transistor of the second conductivity type in that the gate length of the second transistor of the conductivity type is equal and the gate width is M (M is a natural number other than 0) times. 2. The band gap reference circuit according to claim 1, wherein the gate length and the gate width are set to equal values. 3. A seventh transistor of a first conductivity type instead of a direct connection with the other end of the first field effect transistor of the first conductivity type and one end of the first field effect transistor of the second conductivity type. 2. A field effect transistor is inserted in a state of being connected in series, and a gate electrode of a seventh field effect transistor of the first conductivity type is connected to a gate electrode of a fifth field effect transistor of the second conductivity type. The described band gap reference circuit. 4. Even when a predetermined power supply potential fluctuates to a higher potential, the gate-source voltages of the first and second field-effect transistors of the first conductivity type are equalized. A first of the first conductivity type,
The second, third, fourth, fifth, sixth, and seventh field-effect transistors have the same gate length and gate width, and have the second conductivity type with respect to the first transistor of the second conductivity type. A gate length and a gate width of the second transistor are equal to each other, and a gate length and a gate width of the third transistor of the second conductivity type are equal to those of the first transistor of the second conductivity type; Claim 3 set respectively
The described band gap reference circuit. 5. A depletion type second conductivity type transistor instead of a direct connection with the other end of the first conductivity type second field effect transistor and one end of the second conductivity type second field effect transistor. A fourth field effect transistor is inserted in a series connection state, and the gate electrode of the second field effect transistor of the second conductivity type is connected to the gate electrode of the second field effect transistor of the second conductivity type. The band gap reference circuit according to claim 3. 6. Even when a predetermined power supply potential changes to a higher potential, the potential difference corresponding to the change is absorbed between the drain and the source of the fourth field-effect transistor of the second conductivity type. The first, second, third, fourth, fifth, sixth and seventh field effect transistors of the first conductivity type have the same gate length and gate width, and
The gate length of the second transistor of the second conductivity type is equal to that of the first transistor of the conductivity type, and the gate width is M times larger than that of the first transistor of the second conductivity type. 6. A band according to claim 5, wherein the gate length and the gate width of the third transistor are set equal to each other, and the gate length of the depletion type fourth transistor of the second conductivity type is set longer than a predetermined value.・ Gap reference circuit. 7. A depletion type second conductivity type transistor instead of a direct connection with the other end of the first conductivity type sixth field effect transistor and one end of the second conductivity type third field effect transistor. A fifth field effect transistor is inserted in a series connection state, and a gate electrode of the fifth field effect transistor of the second conductivity type is connected to a gate electrode of the fourth field effect transistor of the second conductivity type of the depletion type. 6. The band gap reference circuit according to claim 5, wherein: 8. Even when a predetermined power supply potential changes to a higher potential, a potential difference corresponding to the change is absorbed between the drain and the source of the second field-effect transistor of the second conductivity type. The first, second, third, fourth, fifth, sixth and seventh field effect transistors of the first conductivity type have the same gate length and gate width, and the second conductivity type of the first The second transistor of the second conductivity type has the same gate length and the gate width as M times that of the first transistor of the second conductivity type with respect to the first transistor of the second conductivity type. The gate length of the fourth transistor of the second conductivity type and the gate length of the fifth transistor of the second conductivity type of the depletion type are set to be equal to the gate length and the gate width, respectively, to be equal to or greater than a predetermined value. The band gap reference circuit according to claim 7, wherein