JPH10191392A - Image signal processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To attain pixel number transformation in an optional ratio that corresponds to an optional chroma format and a scan line number. SOLUTION: A SIMD controlled linear array type multi parallel processor 1 is used, and pixel number transformation processing in an optional ratio is performed with only software processing. At this time, in the case of 4:4:4 format, same pixel number transformation is respectively performed for luminance and chroma. In the case of 4:2:2 format, cubic interpolation is performed for a luminance signal and linear interpolation is performed for a chroma signal and the pixel number transformation is performed. Or it is transformed into 4:4:4 format and the same pixel number transformation is performed. In the case of 4:1:1: format, it is transformed into 4:2:2 format and the same pixel number transformation processing is performed. Or 4:2:2 format into which is transformed is further transformed into 4:4:4 format and the same pixel number transformation processing is performed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an image signal processing apparatus for performing image signal processing such as pixel number conversion processing and scanning line conversion.

[0002]

2. Description of the Related Art In recent years, digital signal processing of video signals has been performed with the improvement of semiconductor technology and processing speed performance of semiconductors. Recently, image display devices have been replaced with conventional cathode ray tubes, and LCDs (Liquor
id Crystal Display (Liquid Crystal Display) Fixed pixel display devices such as display devices and plasma display devices are becoming widespread.

Recently, the so-called NTSC (Nationa
l Television System Committee) signal, PAL (Phase A
lternation by Line) signals, as well as HDTV (High Definition Televisio
n) signal, VGA (Video Graphics Array) signal, SVG
It is required to be able to display signals in various formats such as A (Super VGA) signal and XVGA (extended VGA) signal.

[0004] In these various formats, the number of pixels to be handled is different. When displaying video signals of various formats having different numbers of pixels, an analog display device such as the above-mentioned cathode ray tube can change the deflection speed of the electron beam according to the number of pixels per scanning line time. I'm done.

However, in the above-mentioned fixed pixel display device, the number of pixels that can be handled is fixed, so that the conventional analog technology as in the case of the above-mentioned cathode ray tube cannot be used. Therefore, in order to display these signals of various formats on the above-described fixed pixel display device, it is essential to convert the number of pixels or the number of scanning lines by digital signal processing.

The outline of the above-mentioned pixel number conversion processing will be described below.

The number-of-pixels conversion process is a process of increasing or decreasing the number of output pixels to a desired number of pixels with respect to the number of input pixels in one scanning line period. For example, when the input / output sampling frequency is the same. If the number of pixels is increased, the input image is enlarged (enlarged pixel number conversion processing). Conversely, if the number of pixels is decreased, the input image is reduced (reduced pixel number conversion processing). In other words, in terms of input / output pixels and pixel sampling, rather than the number of pixels, data at a point different from the original sampling position is created from data at the original sampling point. This corresponds to generating an interpolated pixel by interpolating point data from input pixel data.

There are various interpolation methods, and the following three methods are known.

1. Nearest Neighbor Interpolation Method This method is a method of picking up the data at the position closest to the pixel position after the pixel number conversion from the pixel data of the input pixel, and the hardware configuration can be realized by a very simple logic operation. However, the image quality after conversion deteriorates considerably. At the time of reduction, a thin line disappears or a small figure is distorted, and at the time of enlargement, jagged edges are generated.

[0010] 2. Bilinear interpolation method In this method, two points of data located closest to the position of a pixel after pixel number conversion are picked up from pixel data of an input pixel, and linear interpolation is performed from the two points of data.
The image quality is less deteriorated than the above-described nearest neighbor interpolation method. However, when the size is reduced to 2: 1 or less, a so-called pixel dropout phenomenon occurs, and the image quality deteriorates at a stretch. Also, in this method, since a gentle low-pass filter is applied, the image quality becomes blurred as a whole, especially at the edge portion. In addition, the hardware becomes more complicated at once than the nearest neighbor interpolation method.

3. Filter Switching Interpolation Method This method is used for high-quality image signal processing, and is a method of performing conversion using a digital filter of an FIR filter (for example, a finite response filter) adapted to a size conversion ratio. However, if this method is to be implemented by hardware, it will be drastically complicated and large-scale, so that it is almost always performed by a bilinear interpolation method.

Hereinafter, as an example of the filter switching interpolation method, an interpolation method using a cubic interpolation function described later will be described.

First, the principle of the 2: 3 enlarged pixel number conversion for producing three output pixels for two input pixels will be described.

FIG. 36 is a diagram for explaining the principle of the above-mentioned 2: 3 enlarged pixel number conversion. In FIG. 36,
The values of each input pixel are represented by R _i−1 , R _i , R _{i + 1} , R _{i + 2} ,
R _{i + 3} ,..., And the value of each output pixel is Q _j , Q
_{j + 1} , Q _{j + 2} , Q _{j + 3} ,... Also,
In FIG. 36, P ₁ , P ₂ , P ₃ , P ₁ ,... Indicate a phase shift (phase information) between the input pixel and the output pixel.

Here, in the above-mentioned 2: 3 enlarged pixel number conversion, three output pixels are generated for two input pixels as shown in FIG. 36, and the relationship between the input pixels and the output pixels is as follows. The relationship is that the value of the output pixel is calculated from the input pixels in the vicinity. How much range should be used as the neighborhood range for generating the output pixel, or what coefficient value should be used as the value of each coefficient when calculating the output pixel from the input pixel by interpolation Although there are various interpolation methods, the following description exemplifies cubic interpolation in which interpolation is performed from a range of four points (four pixels) as the above-described neighborhood range.

FIG. 37 shows a cubic interpolation function Cub (x) used in the above cubic interpolation, and its function formula is shown in equation (1). Here, it is assumed that the horizontal axis of the cubic interpolation function shown in Expression (1) is normalized by the sampling interval when the original image is sampled into a digital signal.

Cub (x) = | x | ³ −2 | x | ² +1 (when | x | ≦ 1) Cub (x) = − | x | ³ +5 | x | ² −8 | x | +4 ( 1 <| x | ≦ 2) Cub (x) = 0 (when 2 <| x |) (1) In the case of conversion of the number of enlarged pixels, the interpolation value of each output pixel is obtained by sampling the input pixel. It is expressed by a convolution operation of the value and the cubic function, and the interpolation value of the output pixel can be expressed by the following equation (2). Q _j = Cub (x ₁₁ ) * R _i-1 + Cub (x ₁₂ ) * R _i + Cub (x ₁₃ ) * R _{i + 1} + Cub (x ₁₄ ) * R _{i + 2} Q _{j + 1} = Cub (x ₂₁ ) * R _i-1 + Cub (x ₂₂ ) * R _i + Cub (x ₂₃ ) * R _{i + 1} + Cub (x ₂₄ ) * R _{i + 2} Q _{j + 2} = Cub (x ₃₁ ) * R _i + Cub (x ₃₂ ) * R _{i + 2} + Cub (x ₃₃ ) * R _{i + 2} + Cub (x ₃₄ ) * R _{i + 3} (2) Each coefficient Cub (x) of the equation (2) is calculated from the cubic interpolation function. This is calculated from the phase indicating how much the output pixel to be obtained is shifted from the input pixel. For example, 2: 3 shown in FIG.
, The phase of the output pixel of Q _j matches the phase of the input pixel near it (eg, the input pixel of R _i ), so that its phase information P ₁ becomes zero. since Q j _{+ 1} output pixel of the phase is 2/3 shifted from the phase of the input pixel in the vicinity thereof (for example, an input pixel of the R _i) the phase information P ₂ is 2/3, the Q _{j + 2} Since the phase of the output pixel is shifted by _{１ ／} from the phase of the input pixel in the vicinity thereof (for example, the input pixel of R _{i + 1} ), the phase information P
_{Since 3} is 1/3, the above equation (2) can be rewritten as equation (3).

Q _j = Cub (-1) * R _i-1 + Cub (0) * R _i + Cub (1) * R _{i + 1} + Cub (2) * R _{i + 2} Q _{j + 1} = Cub (-5 / 3) * R _i-1 + Cub (-2/3) * R _i + Cub (1/3) * R _{i + 1} + Cub (4/3) * R _{i + 2} Q _{j + 2} = Cub (-4 / 3) * R _i + Cub (-1/3) * R _{i + 1} + Cub (2/3) * R _{i + 2} + Cub (5/3) * R _{i + 3} ... (3) Cub (x) above And each value R _i−1 , R _i , R _{i + 1 of} the input pixel,
Since R _{i + 2} is a known value, the interpolation data of each output pixel can be calculated from Expression (3). For example, as far as the output pixel of Q _j is concerned, from the above equation (1), C
ub (-1) = 0, Cub (0) = 1, Cub (1) = 0, Cub
Since (2) = 0, Q _j = 0 * R _i-1 + 1 * R _i + 0 * R _{i + 1} + 0 * R _{i + 2} = R _i (4), which is the value of the input pixel itself .

The above description has been made by taking the case of the 2: 3 enlarged pixel number conversion as an example, but the same applies to an arbitrary enlarged ratio. If the phase of the output pixel is known, the equation (1)
, The respective coefficients of the cubic function may be obtained, and convolution operation may be performed with four input pixels near the interpolation pixel.

Next, the principle of the 3: 2 reduced pixel number conversion for producing two output pixels for three input pixels will be described.

FIG. 38 is a view for explaining the principle of the 3: 2 reduced pixel number conversion. In FIG. 38, as in FIG. 36, the value of each input pixel is set to R
_i-1 , R _i , R _{i + 1} , R _{i + 2} , R _{i + 3} ,..., and the value of each output pixel is Q _j , Q _{j + 1} , Q _{j + 2} ,. It is expressed as Further, P ₁ , P ₂ , P ₁ ,... In FIG.
Represents the phase shift (pixel phase information) between the input pixel and the output pixel.

Here, also in the 3: 2 reduced pixel number conversion, similarly to the enlarged pixel number conversion, the relationship between the input pixel and the output pixel is such that the value of the output pixel is calculated from the input pixel in the vicinity. Has become. Also in this 3: 2 reduced pixel number conversion, an example will be described in which cubic interpolation in which an output pixel (interpolated pixel) is calculated from four input pixels in the vicinity thereof by interpolation as described above.

That is, in the case of the conversion of the number of reduced pixels in FIG. 38, the interpolation formula of the interpolation value (for example, Q _j , Q _{j + 1} ) of each output pixel is as the following formula (5).

Q _j = Cub (x ₁₁ ) * R _i-1 + Cub (x ₁₂ ) * R _i + Cub (x ₁₃ ) * R _{i + 1} + Cub (x ₁₄ ) * R _{i + 2} Q _{j + 1} = Cub (x ₂₁ ) * R _i + Cub (x ₂₂ ) * R _{i + 1} + Cub (x ₂₃ ) * R _{i + 2} + Cub (x ₂₄ ) * R _{i + 3} (5) Even in the reduced pixel conversion, Each coefficient C in the above equation (5)
ub (x) is a value calculated from the cubic function, which is calculated from a phase indicating how much the output pixel to be obtained is shifted from the input pixel. In the case of the 3: 2 reduction pixel number conversion shown in FIG. 38, the phase of the output pixel of Q _j coincides with the phase of the neighboring input pixel (for example, the input pixel of R _i ). ₁
Is zero. Similarly, the phase of the output pixel of Q _{j + 1} is shifted by １ ／ from the phase of the input pixel in the vicinity thereof (for example, the input pixel of R _{i + 1} ), so that the pixel phase information P ₂ is 1 / 2
Thus, equation (5) can be rewritten as equation (6).

Q _j = Cub (-1) * R _i-1 + Cub (0) * R _i + Cub (1) * R _{i + 1} + Cub (2) * R _{i + 2} Q _{j + 1} = Cub (-3 / 2) * R _i + Cub (-1/2) * R _{i + 1} + Cub (1/2) * R _{i + 2} + Cub (3/2) * R _{i + 3} (6) The above Cub (x ) And input pixel values R _i−1 , R _i , R _{i + 1} ,
Since each of R _{i + 2} ,... Is a known value, interpolation data of each output pixel can be calculated from Expression (6). For example, as far as the output pixel of Q _j is concerned, the above equation (1)
Thus, Cub (-1) = 0, Cub (0) = 1, Cub (1) =
0, Cub (2) = 0, so that Q _j = 0 * R _i-1 + 1 * R _i + 0 * R _{i + 1} + 0 * R _{i + 2} = R _i (7), and the value of the input pixel It becomes itself.

Although the case of the 3: 2 reduction pixel number conversion has been described as an example, the same applies to an arbitrary reduction ratio. If the phase of the output pixel is known, the phase of the cubic function can be calculated from the above equation (1) by the phase. What is necessary is just to calculate each coefficient and perform convolution operation with the four input points near the interpolation pixel.

Conventionally, the above-described conversion of the number of pixels is realized by a hard wired configuration as shown in FIG. 39, for example. Here, the image signal is described as being limited to the luminance signal, and the description of the chroma signal will be described later.

In the configuration shown in FIG. 39, registers 101 to 104 connected in series delay supplied data by one sample, so that these registers constitute a four-stage shift register. ing. When the input shift control signal IE is at the “H” level, the registers 101 to 104 sequentially delay the input pixel data supplied from the input terminal 100 and output image data shifted by one sampling. On the other hand, these registers 101 to 10
4, the input shift control signal IE is set to "L".
In the case of a level, the previous value is retained without shifting. Each image data obtained by being shifted by each of the registers 101 to 104 is input to a corresponding one of the multipliers 111 to 104.
It is sent to 114.

Further, the cubic coefficient generator 105
The cubic coefficients C _{1 to} C ₄ are generated for each pixel, and these cubic coefficients C _{1 to} C ₄ are respectively assigned to the corresponding multipliers 11.
1 to 114 are supplied as multiplication coefficients. Therefore, the multipliers 111 to 114 multiply the cubic coefficients generated by the cubic coefficient generator 105 by the input pixel data shifted by the shift registers 101 to 104, respectively. This multiplier 11
The multiplication results of 1 to 114 are added by an adder 107 and input to a FIFO (first in first out) memory 108. However, the memory 108 may be a one-dimensional pixel storage element, for example, a line memory or the like.

The FIFO memory 108 is provided to output pixel data intermittently in the case of the reduced pixel number conversion processing, and the output skip supplied from the controller 106 in the case of the reduced pixel number conversion processing. The pixel data is skipped on the basis of the pixel control signal SC and output to the output terminal 109. In addition,
The FIFO memory 108 is used simply as a FIFO memory in the case of the enlarged pixel number conversion processing, and is merely a delay element.

The controller 106 controls the output skip pixel control signal SC of the FIFO memory 108, which is an output port memory, and the shift registers 101 to 1 based on the conversion ratio at the time of converting the number of enlarged or reduced pixels.
04 for generating the input shift control signal IE and for controlling the timing for the cubic coefficient generator 105.

[0032] Figure 40 is the diagram 39 2 in the hardware configuration of: shows the relationship between the pixel arrangement and the cubic coefficient at 3 number larger pixel converting process _{C 1, C 2, C 3} , C 4,
In the case where the 2: 3 enlarged pixel number conversion process is performed, FIG.
0, the input shift control signal IE
The operation of shifting the input pixel data by three pixels and not shifting the pixel data of one pixel before is repeated. The input data D ₁ to each of the multipliers 111 to 114 in FIG.
D ₂ , D ₃ , D ₄ are the multiplier inputs D ₁ , D ₂ ,
D ₃ and D ₄ , and as shown in equation (8), a desired result can be obtained by performing a convolution operation between these multiplier inputs and the cubic coefficients C ₁ , C ₂ , C ₃ and C _4. Can be

Q = C ₁ * D ₁ + C ₂ * D ₂ + C ₃ * D ₃ + C ₄ * D ₄ (8) For simplicity, an example of 2: 3 enlarged pixel number conversion is shown. However, in the case of an arbitrary enlargement ratio, the principle is the same except for the timing control, and therefore, the description thereof is omitted.

Further, in FIG. 41 FIG 39 3 in the hardware configuration of: shows the relationship between the pixel arrangement and the cubic coefficient at 2 reduced the number of pixel converting process _{C 1, C 2, C 3} , C 4 . In the figure, Skip indicates an output pixel to be skipped. In the case of the reduction pixel number conversion process, unlike the case of the enlargement pixel number conversion, the input shift control signal IE is always at the "L" level, and the input pixel data directly enters the registers 101 to 104. Therefore, the input data D _{1 to} D _{4 of} each of the multipliers 111 to 114
Are as shown in the multiplier inputs D _{1 to} D ₄ in FIG. 41. By performing the convolution operation of the cubic coefficients C _{1 to} C ₄ with equation (8), a desired result can be obtained. However, in the case of the 3: 2 reduced pixel number conversion, three pixels to be output are
Since one input pixel becomes unnecessary, the unnecessary pixel is skipped by controlling writing to the FIFO memory 108. The control signal for this is the output skip pixel control signal SC as shown in FIG. That is, the output skip pixel control signal SC skips when it is at “H” level,
FIF not to skip when L level
This is a signal for controlling the O memory 108.

Here, for the sake of simplicity, an example of 3: 2 reduced pixel number conversion has been described. However, in the case of an arbitrary reduction ratio, the principle is the same except that the timing control is different. Is omitted.

Next, as with the pixel number conversion, the outline of the scanning line number conversion processing will be described below.

In the scanning line number conversion processing, the same concept can be applied by replacing each pixel in the pixel number conversion processing described above with each scanning line. That is, the scanning line number conversion is a process of increasing or decreasing the number of output lines to the number of desired lines with respect to the number of input lines in one vertical scanning line period. For example, when the number of input / output lines is the same If the number of lines is increased, the input image is enlarged in the vertical direction (enlarged line number conversion processing). Conversely, if the number of lines is decreased, the input image is reduced in the vertical direction (reduced line). Number conversion processing).

As this interpolation method, there are various methods similar to the pixel number conversion. Among them, an interpolation method using a cubic interpolation function capable of improving image quality will be described below.

First, the principle of the 2: 3 expanded line number conversion for producing three output lines for two input lines will be described.

FIG. 42 is a diagram for explaining the principle of the above-mentioned 2: 3 enlarged line number conversion. In FIG. 42, the values of each input line are represented by R _i−1 , R _i , R _{i + 1} ,
R _{i + 2} , R _{i + 3} ,..., And the value of each output line is represented as Q _j , Q _{j + 1} , Q _{j + 2} , Q _{i + 3} ,. In FIG. 42, P ₁ , P ₂ , P ₁ ,... Indicate a phase difference between the input line and the output line (line phase information).
Is represented.

Here, in the above 3: 2 enlarged line number conversion, as shown in FIG. 42, three output lines are created for two input lines, and the relationship between the input lines and the output lines is as follows. The relationship is such that the value of the output line is calculated from the input line in the vicinity. How much range should be used as the neighborhood range for generating the output line, or what coefficient value should be used as the value of each coefficient when calculating the output line by interpolation from the input line Although there are various interpolation methods, the following description exemplifies cubic interpolation in which interpolation is performed from a range of four points (for four lines) as the above-described neighborhood range.

In the case of the expansion line number conversion, the interpolation value of each output line is represented by a convolution operation between the values of the input four lines and the cubic function, and the interpolation value of the output line is represented by the following equation (9). be able to.

Q _j = Cub (x ₁₁ ) * R _i-1 + Cub (x ₁₂ ) * R _i + Cub (x ₁₃ ) * R _{i + 1} + Cub (x ₁₄ ) * R _{i + 2} Q _{j + 1} = Cub (x ₂₁ ) * R _i-1 + Cub (x ₂₂ ) * R _i + Cub (x ₂₃ ) * R _{i + 1} + Cub (x ₂₄ ) * R _{i + 2} Q _{j + 2} = Cub (x ₃₁ ) * R _i + Cub (x ₃₂ ) * R _{i + 2} + Cub (x ₃₃ ) * R _{i + 2} + Cub (x ₃₄ ) * R _{i + 3} (9) Each coefficient Cub (x) in the expression (9) is A value calculated from the cubic interpolation function, which is calculated from the phase indicating how much the output line to be obtained is shifted from the input line. For example, FIG.
For 3 of the enlarged line number conversion, the line phase information P ₁ because the phase of the output lines of the Q _j is coincident with the phase of the input line in the vicinity thereof (for example, the input lines of the R _i)
Is zero, and similarly, the phase of the output line of Q _{j + 1} is shifted by ／ from the phase of the input line in the vicinity thereof (for example, the input line of R _i ), so that the line phase information P ₂ is 2/3. Since the phase of the output line of Q _{j + 2} is shifted by 1/3 from the phase of the input line in the vicinity thereof (for example, the input line of R _{i + 1} ), the line phase information P ₃ becomes 1 /
Since Equation 3 is obtained, Equation (9) can be rewritten as Equation (10).

Q _j = Cub (-1) * R _i-1 + Cub (0) * R _i + Cub (1) * R _{i + 1} + Cub (2) * R _{i + 2} Q _{j + 1} = Cub (-5 / 3) * R _i-1 + Cub (-2/3) * R _i + Cub (1/3) * R _{i + 1} + Cub (4/3) * R _{i + 2} Q _{j + 2} = Cub (-4 / 3) * R _i + Cub (-1/3) * R _{i + 1} + Cub (2/3) * R _{i + 2} + Cub (5/3) * R _{i + 3} ... (10) The above Cub (x) And the values R _i−1 , R _i ,
Since R _{i + 1} and R _{i + 2} are known values, interpolation data of each output line can be calculated from the equation (10).
For example, As far as the output line of the Q _j, the equation from (1), Cub (-1) = 0, Cub (0) = 1, Cub
Since (1) = 0 and Cub (2) = 0, Q _j = 0 * R _i-1 + 1 * R _i + 0 * R _{i + 1} + 0 * R _{i + 2} = R _i (11), which is the value of the input line itself.

Although the above description has been made by taking the case of the 2: 3 enlargement line number conversion as an example, the same applies to an arbitrary enlargement ratio.
If the phase of the output line is known, each coefficient of the cubic function can be obtained from the equation (1) based on the phase, and convolution operation can be performed with four input lines near the interpolation line.

Next, the principle of the 3: 2 reduced line number conversion for producing two output lines for three input lines will be described.

FIG. 43 is a diagram for explaining the principle of the 3: 2 reduction line number conversion. In FIG. 43, similarly to FIG. 42, the values of the input lines are denoted by _Ri-1 , _Ri , _{Ri + 1} , _{Ri + 2} , _{Ri + 3} ,. The values of the output pixels are represented as Q _j , Q _{j + 1} , Q _{j + 2} ,. 43, P ₁ , P ₂ , P ₁ ,
.. Also indicate the phase shift (line phase information) between the input line and the output line.

Here, in the above-described 3: 2 reduction line number conversion, similarly to the expansion line number conversion, the relationship between the input line and the output line is such that the value of the output line is calculated from the input line in the vicinity. Has become. This 3: 2
In the conversion of the number of reduced lines, as in the case described above, an example of cubic interpolation in which an output line (interpolation line) is calculated from four input lines in the vicinity thereof by interpolation will be described.

That is, in the case of the conversion of the number of reduced lines in FIG. 43, the interpolation formula of the interpolation value (for example, Q _j , Q _{j + 1} ) of each output line is as the following formula (12).

Q _j = Cub (x ₁₁ ) * R _i-1 + Cub (x ₁₂ ) * R _i + Cub (x ₁₃ ) * R _{i + 1} + Cub (x ₁₄ ) * R _{i + 2} Q _{j + 1} = Cub (x ₂₁ ) * R _i + Cub (x ₂₂ ) * R _{i + 1} + Cub (x ₂₃ ) * R _{i + 2} + Cub (x ₂₄ ) * R _{i + 3} (12) Also in the reduction line number conversion Each coefficient Cub (x) in the above equation (12) is a value calculated from the cubic function, and is calculated from a phase indicating how much the output line to be obtained is shifted from the input line. . In the case of the 3: 2 reduced line number conversion shown in FIG.
The Q _j of the output line of the phase is the line phase information P ₁ so match the phase of the input line in the vicinity thereof (for example, the input lines of the R _i) is zero, as well as the Q _{j + 1}
The phase of the output line of the input line (for example, R
Since the phase is shifted by） from the phase of the ( _{i + 1} input line), the line phase information P ₂ is １ ／.
2) can be rewritten as equation (13).

Q _j = Cub (-1) * R _i-1 + Cub (0) * R _i + Cub (1) * R _{i + 1} + Cub (2) * R _{i + 2} Q _{j + 1} = Cub (-3 / 2) * R _i + Cub (-1/2) * R _{i + 1} + Cub (1/2) * R _{i + 2} + Cub (3/2) * R _{i + 3} (13) The above Cub (x ) And input line values R _i−1 , R _i ,
Since R _{i + 1} , R _{i + 2} ,... Are each known values,
From this equation (13), the interpolation data of each output line can be calculated. For example, speaking only to the output line of the Q _j,
From the above formula (1), Cub (-1) = 0, Cub (0) = 1,
Since Cub (1) = 0 and Cub (2) = 0, Q _j = 0 * R _i-1 + 1 * R _i + 0 * R _{i + 1} + 0 * R _{i + 2} = R _i (14) , The input line value itself.

The above description has been made by taking the case of the 3: 2 reduction line number conversion as an example, but the same applies to any reduction ratio.
As long as the phase of the output line is known, the coefficients of the cubic function can be obtained from the equation (1) based on the phase, and convolution operation can be performed with four input points near the interpolation line.

Conventionally, the line number conversion as described above is performed by
For example, it is realized by a hard wired configuration as shown in FIG. In the line number conversion, the luminance signal and the chroma signal need not be distinguished by the chroma format as in the pixel number conversion, and the same circuit may be used for the luminance signal and the chroma signal.

In the configuration shown in FIG. 44, the line memories 201 to 204 connected in series delay the supplied data by one scanning line, so that a four-stage line memory is constituted. Have been. In the line memories 201 to 204, when the input shift control signal IE is at the “H” level, the input data for the input lines supplied from the input terminal 200 is sequentially delayed, and the image data shifted by one scanning line time is used. Is output. On the other hand, these line memories 201
If the input shift control signal IE is at "L" level, the line value is not shifted and the line value is held. The image data obtained by line shifting in the line memories 201 to 204 are sent to the corresponding multipliers 211 to 214.

Further, the cubic coefficient generator 205
The cubic coefficients C _{1 to} C ₄ are generated for each line, and these cubic coefficients C _{1 to} C ₄ are respectively assigned to the corresponding multipliers 2.
It supplies to 11-214 as a multiplication coefficient. Therefore, in these multipliers 211 to 214, the cubic coefficient generated by the cubic coefficient generator 205 is
The line memories 201 to 204 multiply the input line data by line shifting. The multiplication results of the multipliers 211 to 214 are added by an adder 207 and input to a FIFO (first in first out) field memory 208.

The FIFO field memory 210
This is provided to output line data required in the case of the enlargement line number conversion process, and based on the input skip line control signal SCI supplied from the controller 206 in the case of the enlargement line number conversion. Whether to retain the value of the line before outputting the line data is switched and output to the line memory 201. Note that the FIFO field memory 210 is used as a simple FIFO memory in the case of the reduced line number conversion processing,
It is just a delay element.

The FIFO field memory 208 is
This is provided to output the line data required in the case of the reduced line number conversion process in an intermittent manner, and is based on the output skip line control signal SCO supplied from the controller 206 in the case of the reduced line number conversion process. Line data is skipped and output terminal 209 is skipped.
Output to The FIFO field memory 208
Is used as a simple FIFO memory in the case of the expansion line number conversion processing, and is merely a delay element.

The controller 206 outputs an output skip line control signal SCO of the FIFO field memory 208 as an output port memory and an input shift line of the line memories 201 to 204 on the basis of the conversion ratio at the time of conversion of the number of enlarged or reduced lines. The control signal IE is generated, and timing control for the cubic coefficient generator 205 is performed.

FIG. 45 shows the relationship between the line arrangement and the cubic coefficients C ₁ , C ₂ , C ₃ , and C ₄ in the 2: 3 expanded line number conversion process in the hardware configuration of FIG. 44. As shown in FIG. 45, when performing the conversion processing of the number of expanded lines of three, the input shift line control signal IE shifts the input line data by three lines and does not shift the line data one line before. repeat. The input data D ₁ , D ₂ , D ₃ , and D ₄ to each of the multipliers 211 to 214 in FIG. 44 are as shown in the multiplier inputs D ₁ , D ₂ , D ₃ , and D ₄ in FIG. As shown in (15), a desired result can be obtained by performing a convolution operation of these multiplier inputs and the cubic coefficients C ₁ , C ₂ , C ₃ , and C ₄ .

Q = C ₁ * D ₁ + C ₂ * D ₂ + C ₃ * D ₃ + C ₄ * D ₄ (15) For simplicity, an example of 2: 3 enlarged line number conversion is shown. However, in the case of an arbitrary enlargement ratio, the principle is the same except for the timing control, and therefore, the description thereof is omitted.

[0061] Further, in FIG. 46 FIG 44 hardware configuration at 3: shows the relationship between the line arrangement and the cubic coefficient at 2 reduced lines number conversion process _{C 1, C 2, C 3} , C 4 . In the figure, Skip indicates an output line to be skipped. In the case of the reduction line number conversion processing, unlike the case of the enlargement line number conversion, the input shift line control signal IE is always at "L" level, and the input line data is stored in each line memory 201-2.
04, the multipliers 211 to 21
Input data D ₁ to D ₄ of 4 multipliers input D ₁ to D ₄ in FIG. 46
The desired result can be obtained by performing Equation (15) for the convolution of the cubic coefficients C _{1 to} C ₄ with this. However, in the case of the 3: 2 reduction line number conversion,
One input line becomes unnecessary for the three output lines, and the unnecessary lines are skipped by controlling the writing to the FIFO field memory 208. The control signal for this is an output skip line control signal SCO as shown in FIG.
Becomes That is, the output skip line control signal SCO skips when it is at “H” level,
FIF not to skip when L level
This is a signal for controlling the O field memory 208.

Here, for the sake of simplicity, an example of 3: 2 reduction line number conversion has been described. However, in the case of an arbitrary reduction ratio, the principle is the same except for the timing control, so that the description will be made here. Is omitted.

As described above, the conversion of the number of pixels or the number of scanning lines is performed by a so-called ASIC (Appli
cation Specific Integrated Circuit: Application Specific I
This is realized using a high-speed product-sum circuit such as C).

[0064]

However, in a situation where various new formats have been proposed to cope with the various formats as described above, and in recent years, various circuit formats have been proposed in the case of the ASIC. Or the lack of flexibility due to changes in bit precision after design, changes in the number of pixels conversion algorithm, addition of specifications for the new format, etc., making it difficult to commercialize the product in accordance with market needs. ing. That is, AS
In order to realize the conversion of the number of pixels by an IC, it is necessary to limit the conversion ratio to a fixed conversion ratio with a small degree of freedom, or to switch between several conversion ratios at most. Not get. In addition, the above ASI
In C, once a circuit is created, it is not easy to change the bit precision, and the VGA, SV
It is practically impossible to support not only various signal formats such as GA, XVGA, and HDTV, but also various formats including new formats that will appear in the future.

It can be said that it is practically impossible to change the horizontal and vertical conversions by the filter switching interpolation method which is complicated in real time by the ASIC in terms of the circuit configuration.

In particular, when the number of scanning lines is converted, a field memory for storing an image signal outside is absolutely required. From this field memory, only the data necessary for interpolation is read and written, and the number of lines to be interpolated is determined. It is difficult to synchronize the timing with the external memory control except for a fixed ratio in taking out a phased one.

In the above description, only the processing of the luminance signal (Y signal) among the input signals has been described, but the processing of the chroma signal (C signal) differs depending on the input format.

The so-called 4: 4: 4 format structure, 4: 2: 2 format structure, and 4: 1: 1 format structure are shown in FIGS. 47, 48, and 49, respectively, as digital video signals. Since the format structure of these digital video signals is already widely known, a detailed description thereof will be omitted here.

For example, in the case of a 4: 4: 4 format such as a so-called D1 component format signal shown in FIG. 47, two color difference signals (RY (Cr) signals,
Since the BY (Cb) signal) has the same format as the luminance signal (Y signal), the same processing as in the case of the luminance signal described above may be performed on these two color difference signals.

However, in the case of the 4: 2: 2 format such as the so-called D2 format, the input chroma signal switches between Cr and Cb for each sample as shown in FIG. 48, and is therefore the same as the luminance signal (Y signal). No processing can be performed.

The reason is that the two color difference signals Cr and Cb of the chroma signal in the 4: 2: 2 format are multiplexed so as to repeat Cr, Cb, Cr, Cb,... And therefore
The output side must have a configuration in which Cr and Cb are repeated for each sample in the same order as at the time of input.

However, in the above-described enlargement or reduction pixel number conversion processing, when pixels are skipped by shift control of input pixel data by a shift register or skip control of output pixel data, the above-mentioned Cr and Cb are lost. May be interchanged depending on the pixel position, and an image in which Cr and Cb are interchanged may be obtained. In this case, in order to maintain the arrangement of Cr and Cb, it is only necessary to perform a setting such that Cr and Cb are skipped in the input section. However, this makes it difficult to match the number of pixels after luminance and chroma conversion.

Even if processing is performed by focusing on only one of Cr and Cb, the input Cr and Cb data itself exists only every other sample. Even if the data is subjected to pixel number conversion processing using some method (for example, data is skipped one by one at the input unit), after the pixel number conversion processing, the luminance signal (Y signal) and the pixel position are returned again. Must be reconfigured to correspond.

For this reason, the simplest method of performing the pixel number conversion processing including the chroma signal in the 4: 2: 2 format is to convert the 4: 2: 2 format into the 4: 4: 4 format once. For example, there is a method of converting the data and reconstructing the 4: 2: 2 format again at the output unit.

Similarly, the 4: 1: 1 format often used in consumer video signal processing devices also has a format structure as shown in FIG. 49, so that the chroma signal is used as it is when calculating. Can not. In this case, the 4: 1: 1 format is first converted into the 4: 2: 2 format as shown in FIG.
Conversion to a 4: 4 format is performed.

Therefore, when the chroma signal is in the 4: 2: 2 format or the 4: 1: 1 format, the format signal is once converted to the 4: 4: 4 format to obtain the same format as the luminance signal. After the conversion into the format format, the same pixel number conversion processing circuit as the luminance signal is prepared, the pixel number conversion is performed, and after the pixel number conversion process, the input format format (4: 2: 2 format or 4: (1: 1 format).

The conversion of the number of pixels as described above is performed by the ASIC.
When realizing with a hard wired configuration such as
4: 4 format, 4: 2: 2 format, 4:
In order to support all the arbitrary chroma formats such as the 1: 1 format, there is a problem that a circuit size at least three times or more the pixel number conversion configuration for the luminance signal is required. Therefore, due to practical limitations on circuit size,
When the pixel number conversion processing is realized by the ASIC, the method is limited to a method in which only a fixed conversion ratio is enabled, or a method in which only a few types of conversion ratios are enabled and these are switched and used. As a result, the degree of freedom of the pixel number conversion process is very small.

Accordingly, the present invention has been made in view of such circumstances, and makes it possible to realize digital signal processing for converting the number of pixels and the number of scanning lines at an arbitrary ratio. Flexibility to handle pixel count conversion and high-definition television with different conversion ratios depending on the horizontal position, as well as flexible changes in bit precision after design or addition of new format specifications It is another object of the present invention to provide an image signal processing apparatus which can perform the conversion of the number of pixels at an arbitrary ratio corresponding to an arbitrary chroma format.

[0079]

SUMMARY OF THE INVENTION According to the present invention, there is provided a method for arranging a plurality of pixels which are arranged corresponding to each pixel in a one-dimensional direction of a digitized two-dimensional image and each pixel data in the one-dimensional direction is sequentially input in a time series. An image signal processing apparatus comprising: an element processor; and control means for commonly controlling each of the element processors, wherein each of the element processors includes a temporary storage unit for temporarily storing pixel data of luminance and color difference; Input pixel data storage means for storing the input pixel data of the chrominance and transferring it to the temporary storage means, pixel attribute information storage means for storing at least pixel attribute information representing the attribute of the pixel of luminance, and pixel data of luminance and chrominance Pixel skip information storage means for storing pixel skip information for skipping pixel data, and input pixel data for luminance and chrominance or a neighboring element program based on pixel attribute information. Arithmetic operation means for performing a predetermined operation using the luminance and chrominance pixel data of the sensor, and input and output luminance and chrominance pixel data or luminance and chrominance pixel data after operation extracted from the temporary storage means The above-mentioned problem is solved by having the output pixel data storage means. Further, the present invention enables the conversion of the number of scanning lines by performing the same processing for each scanning line.

Here, in the image signal processing device of the present invention,
In each element processor, the same processing is performed on pixel data of luminance and chrominance represented in 4: 4: 4 format. In the image signal processing device of the present invention,
4: 2: 2 in arithmetic operation means of each element processor
Color difference (or color difference obtained by converting a 4: 1: 1 format to a 4: 2: 2 format) by performing an interpolation operation using values of four neighboring pixels on the pixel data of the format luminance.
A linear interpolation operation using the values of neighboring pixels is performed on the pixel data of. In the image signal processing device of the present invention, 4:
A format conversion unit is provided for converting pixel data having a color difference of 2: 2 format (or color difference of 4: 1: 1 format) into 4: 4: 4 format, and each element processor has luminance and luminance of 4: 4: 4 format. The same processing is performed on the color difference pixel data.

That is, according to the present invention, the pixel number conversion processing and the scanning line number conversion processing at arbitrary ratios independent of each other in real time can be realized only by software processing using a linear array type multi-parallel processor controlled by SIMD. ,
Each conversion ratio can be changed in real time. Further, according to the present invention, for example, not only in 4: 4: 4 format, but also in 4: 2: 2 format and 4: 1,: 1 format, the pixel number conversion processing and the scanning line at an independent arbitrary ratio are performed. Number conversion processing can be realized. Further, by calculating the control signal of the field memory provided externally by a linear array type multi-parallel processor under SIMD control, an external memory control circuit becomes unnecessary and the conversion ratio can be changed in real time.

[0082]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings.

In the image signal processing apparatus according to the embodiment of the present invention, in order to overcome the problem of digital signal processing for converting the number of pixels or the number of scanning lines by the above-described hardware configuration, a hard wired such as the ASIC is used. Instead of the configuration, the digital signal processing is realized by a software program using a DSP (digital signal processor).

As described above, by performing the digital signal processing by the software program, it is possible to flexibly cope with the specification change, and it is possible to switch and execute various different signal processing only by rewriting the software program. . In addition, there is no need to change the hardware at all when the specification is changed.
(Time-Axis Trnsform System) period can be considerably shortened compared to the past.

As a DSP for realizing the above-described pixel number conversion processing and scanning line number conversion processing by a software program, for example, the basic internal configuration and basic operation of a so-called linear array type multi-parallel processor will be described below. I do.

The linear array type multi-parallel processor is, for example, as shown in FIG. 1, in which element processors 40 corresponding to one input pixel are arranged one-dimensionally for one scanning line, and parallel processing is performed for each one scanning line. It is characterized by doing.

In FIG. 1, serial input data SID which is time-series input pixel data supplied to the input terminal 30 is temporarily stored after being input to the input register 41 of each element processor 40. To the local memory 43 for Further, the memory address generator 31 and the instruction generator 32 for generating the memory address of the local memory 43 include:
Control common to all the element processors 40, that is, so-called SIMD (Single Instruction Multiple Data)
a Stream) control.

As described above, although being a feature of the linear array type multi-parallel processor, the data once taken into the DSP is subjected to the same processing for all the element processors 40 corresponding to one scanning line. More specifically, the data transferred to the local memory 43 of each element processor 40 is sent to the output register 42 after being subjected to the operation necessary for the interpolation with the arithmetic processing unit 44, and is finally sent to the output register 42. By being output from each output register 42 of each of these element processors 40, interpolated pixel data for one scanning line is extracted as output pixel data (serial output data SOD) from the DSP.

Each of the element processors 40 corresponds to each pixel of one scanning line as described above.
Each element processor 40 has a structure capable of accessing data in the local memory 43 of another element processor 40 near the left and right. By having such a structure, the DSP can load pixel data in the vicinity of the left and right with respect to pixel data for one scanning line as a whole written in the local memory 43 of each element processor 40. A so-called horizontal FIR filter (non-recursive filter) can be realized by performing transmission and reception with each processing unit 44 and performing calculations.

In the DSP, pixel data for one scanning line as a whole can be discretely stored in the local memory 43 of each element processor 40. Therefore, for example, pixel data is stored every other element processor 40 at the time of input. It is also possible to memorize. Similarly, the DSP can discretely output pixel data corresponding to one scanning line as a whole stored in each local memory 43 of each element processor 40.

The conversion of the number of pixels and the conversion of the number of scanning lines can be realized simultaneously by using the DSP. However, each processing is basically independent of each other and can be considered separately. . That is, as the signal processing, it is possible to first perform the pixel number conversion processing and then perform the scanning line number conversion processing, or to perform the scanning line number conversion processing first and then perform the pixel number conversion processing. Is also possible. Of course, the pixel number conversion processing and the scanning line number conversion processing can be performed simultaneously. In the following description, the pixel number conversion processing and the scanning line number conversion processing will be performed separately for convenience of explanation. First, the process of converting the number of pixels of the luminance signal and the chroma signal will be described.

Here, in the linear array type multi-parallel processor in which the SIMD control is performed as described above, the pixel number conversion processing of an arbitrary conversion ratio such as a conversion ratio of 2 times or more or 1/2 times or less can be easily performed. A description will be given of a method of realizing the above and a method of realizing pixel number conversion with chroma signals of various formats which cannot be realized with the above-described hard wired configuration. Although the configuration of FIG. 2 is basically controlled by SIMD in the same manner as in FIG. 1, only the main parts are shown in FIG. 2 for simplification.

First, the method for realizing the pixel number conversion at the above-mentioned arbitrary ratio will be described.

Each element processor 10 of the linear array type multi-parallel processor 1 according to the embodiment of the present invention shown in FIG.
Are the input register 11 and the output register 13 as described above.
Data is transmitted and received between an input skip register 12 and an output skip register 14 described later, a local memory 15 having a working area, and the local memory 15 or the local memory 15 of another element processor 10 in the vicinity. An arithmetic processing unit 16 for performing a required operation (filter operation) is provided as a main component. Each element processor 10 has one of the input pixels.
These element processors 10 correspond to pixels and are arranged one-dimensionally for one scanning line. In the linear array type multi-parallel processor 1, the element processors 10 for each one scanning line are processed in parallel.

Since the internal configuration of the processor 1 shown in FIG. 2 is substantially the same as that of FIG. 1 described above, the description of each function is omitted here, but the configuration of FIG. Input skip register 1
2 and the output skip register 14.
The operation of the input skip register 12 and the output skip register 14 will be described below in connection with other components.

In the linear array type multi-parallel processor 1 shown in FIG. 2, each element processor 10 can discretely or continuously store input pixel data for one scanning line, and Can be output discretely or continuously.

Here, in order to input or output the discrete or discrete pixel data in each of the element processors 10 of the linear array type multi-parallel processor 1, for example, "1" is skipped, and "0" is skipped. Pixel skip information that has the meaning of not being
What is necessary is just to assign to the input or output side of each element processor 10. In the processor 1 of the present embodiment, in order to allocate such one-bit pixel skip information to the input and output sides of each of the element processors 10, the one-bit pixel skip information is assigned to each of the element processors 10. The input skip register 12 is provided on the input side, and the output skip register 14 is provided on the output side. If the above-described pixel skip information is stored in advance in the input skip register 12 and the output skip register 14, it is possible to determine whether or not to skip a pixel at the time of input or output in each element processor 10 as described later. Can be set. That is, each element processor 10
By referring to the pixel skip information stored in the input skip register 12 and the output skip register 14, it is possible to determine whether to skip the input pixel data or the output pixel data.

More specifically, the pixel skip information stored in the input skip register 12 is information for skipping pixel data during the enlarged pixel number conversion processing. The input register 11 of the element processor 10 discretely stores the supplied input pixel data based on the pixel skip information,
The stored input pixel data is transferred to the local memory 15. That is, for example, the input register 11 stores the input pixel data when the pixel skip information is, for example, “0”, and does not store the input pixel data when the pixel skip information is, for example, “1” (skipped or described later). To store dummy data whose value is not specified).
The output skip register 1 at the time of conversion of the number of enlarged pixels
4 are all "0",
Therefore, the output register 13 outputs the pixel data as it is, that is, continuously outputs.

On the other hand, the pixel skip information stored in the output skip register 14 is information for skipping pixel data during the reduction pixel number conversion processing. The register 13 discretely stores and outputs the pixel data read from the local memory 15 based on the pixel skip information. That is, for example, the output register 13 stores pixel data when the pixel skip information is, for example, “0”, and does not store (skips) the pixel data when the pixel skip information is, for example, “1”. In addition,
The pixel skip information stored in the input skip register 12 at the time of the conversion of the number of reduced pixels is all "0". Therefore, the input register 11 in this case transfers the input pixel data as it is, that is, continuously to the local memory 15.

As described above, each element processor 10 corresponds to each pixel of one scanning line, and each element processor 10 has its own local memory 1.
5, the data stored in the local memory 15 of another element processor 10 near the left and right sides can be accessed.
With this mechanism, in the linear array type multi-parallel processor 1, all the element processors 10 can simultaneously load the data stored in the local memory 15 of the other element processors 10 near the left and right. The arithmetic processing unit 16 can realize, for example, an FIR filter operation described later using these data. The pixel data generated by the filter operation in the operation processing section 16 is stored in its own local memory 15 again.

However, the same processing is performed in all the element processors 10 corresponding to one scanning line by the SIMD control which is a feature of the linear array type multi-parallel processor. That is, although not shown in FIG. 2, the instruction generator 32 for generating the instruction code of the arithmetic processing unit 16 and the memory address generator 31 for generating the address data of the local memory 15
Performs common control for all element processors 10. The access to the other element processors 10 in the vicinity of the left and right is also performed by all the element processors 1 by the SIMD control.
0 is a common operation, and different accesses cannot be made for each element processor 10 at the same time.

The pixel data stored in the local memory 15 is sent to the output register 13, and the output register 13 finally outputs data for one scanning line as serial output data SOD.

In the case of the reduced pixel number conversion, pixel data read from the local memory 15 is discretely stored in the output register 13 based on the pixel skip information stored in the output skip register 14. The stored pixel data is output from the output register 13.

Next, a description will be given of a method of realizing the pixel number conversion using the cubic interpolation function in the linear array type multi-parallel processor 1 shown in FIG.
In the pixel number conversion, in addition to the enlargement and reduction of the number of pixels, there is also one-to-one (that is, 1: 1) conversion. However, this is a boundary condition for enlargement or reduction and can be included in either of them.
Here, the unity conversion is included in the enlargement.

First, an example of conversion of the number of enlarged pixels will be described.

In the conversion of the number of enlarged pixels, as described with reference to FIG. 40, it is necessary to arrange input pixel data at intervals according to the conversion ratio (enlargement ratio) when inputting pixel data.

In the present embodiment, the above-described pixel skip information is used as information for arranging input pixel data intermittently (output pixels are continuously arranged) during the conversion of the number of enlarged pixels. Further, in the enlarged pixel number conversion, output pixel data is calculated from four pieces of input pixel data in the vicinity of a desired output pixel excluding pixels skipped at the time of input and phase information corresponding to each pixel. It must be generated by performing a convolution operation with the cubic coefficient of the point. As described above, in order to perform the enlarged pixel number conversion, the above-described pixel skip information, the phase information corresponding to each pixel for calculating the cubic coefficient, and the vicinity of the output pixel for generating a desired output pixel. Four pieces of pixel data are required.

FIG. 3 shows the overall flow of the enlarged pixel number conversion processing. Here, as the above-mentioned enlarged pixel number conversion,
An example in which L is expanded to K is given. Here, K and L are positive integers, and K ≧ L. In the case of K = L, the same-size conversion (1: 1) is performed.

In FIG. 3, first, at step ST1
Then, the conversion ratio (enlargement ratio) of L: K is set.

In the next step ST2, all element processors 10 calculate pixel skip information and phase information. The details of the calculation of the pixel skip information and the phase information in step ST2 will be described later.

In step ST3, it is determined whether or not the input of the pixel data of the next line is possible, and this determination is repeated until the input of the pixel data of the next line is enabled.
When the input of the pixel data of the next line is enabled in the step ST3, the input of the pixel data of one line is performed in the next step ST4.

In step ST5, the input pixel data to the own element processor 10 and the pixel data of the four element processors 10 in the vicinity of the own element processor 10 (pixel data of four neighboring points) are converted into the own element processor. 10 is stored in the local memory 15. The details of the process in step ST5 will be described later.

In step ST6, a cubic coefficient is calculated from the phase information. That is, the calculation using the above-described equation (1) is performed.

At step ST7, at step ST6
The convolution operation of the cubic coefficient obtained in the above and the pixel data of the above four neighboring points is performed. The details of the convolution operation will be described later in Expression (16).

In step ST8, the operation for one line is performed, and the obtained interpolated pixel data is output. Thereafter, the process returns to the process after step ST3.

Next, the pixel skip information and the phase information in the above-described step ST2 are calculated in advance by a preprocessor such as a CPU (central processing unit) outside the linear array type multi-parallel processor (DSP), and are actually calculated. Before performing the convolution operation with the pixel data of
For example, it is possible to input the information through the input unit 1. The pixel skip information is stored in the input skip register 12 and the output skip register 14, and the phase information is stored in, for example, a phase information storage register provided in the local memory 15.

On the other hand, the pixel skip information and the phase information can be calculated inside the SIMD-controlled linear array type multi-parallel processor 1, for example, during a video blanking interval or when power is turned on. That is, for example, in the case of pixel number conversion in which the conversion ratio is constant in one scan line in which the conversion ratio does not change depending on the position of the pixel in the horizontal direction, the pixel skip information and the phase information are stored in the processor (DSP) 1. You can easily calculate within. If all the processes including the generation of the pixel skip information and the phase information are realized only inside the processor 1, the entire system configuration can be simplified. In this case, the pixel skip information is also stored in the input skip register 1
2 is stored in the output skip register 14 and the phase information is stored in the phase information storage register in the local memory 15.

Hereinafter, a method of calculating pixel skip information and phase information inside the above-mentioned SIMD-controlled processor 1 during the conversion of the number of enlarged pixels will be described. Although the calculation of the pixel skip information and the calculation of the phase information need not always be performed at the same time, there are many common operations in the setting of the pixel skip information and the calculation of the phase information. Since it is more efficient to share the register resources, the program memory area, the number of execution steps, and the like, an example of an algorithm for obtaining pixel skip information and phase information at the same time is shown here. This calculation may be performed in the video blanking interval or after the power is turned on as described above.

FIG. 4 shows a procedure for calculating the pixel skip information and the phase information inside the linear array type multi-parallel processor 1 under the SIMD control.

In step ST2, which proceeds after step ST1 in FIG. 3, step ST11 shown in FIG.
The following processing is performed.

First, in step ST11, an area for storing phase information (the phase information storage register d _Ph ) is secured in the local memory 15.

In step ST12, one of the element processors 10 on the left
_Is added to the value (phase information) stored in the phase information storage register d _Ph of the local memory 15, and the obtained value is added to the phase information storage register d of its own local memory 15.
Store in _Ph .

In the next step ST13, it is determined whether or not the value added in step ST12 and stored in the phase information storage register d _Ph is equal to or larger than the value of K. When it is determined in step ST13 that the value is equal to or more than the value of K, the process proceeds to step ST14, and when it is determined that the value is less than the value of K, the process proceeds to step ST16.

In step ST14, K is subtracted from the value stored in the phase information storage register d _Ph , and the obtained value is stored again in the phase information storage register d _Ph . In the next step ST15, the input skip register 12
Is stored as "0". That is, the element processor 1
Pixel data input to 0 is input as it is without skipping.

On the other hand, in step ST16, which proceeds when it is determined in step ST13 that the value stored in the phase information storage register d _Ph is less than the value of K, "1" is stored in the input skip register 11. That is, the pixel data input to the element processor 10 is skipped by one and input.

The above steps ST15 and ST1
After 6, the process proceeds to step ST17. This step ST
At 17, it is determined whether or not the above-described processing has been completed for all the pixels (at least the number of all the element processors 10) for one line, and if it is determined that the processing has not been completed, the process returns to step ST12 to return to the above-described step ST12. Repeat the process,
When it is determined that the process has been completed, the next process, that is, the process shown in FIG.
The process proceeds to step ST3.

However, in the algorithm shown in FIG. 4, each element processor 10 performs an operation of storing the value stored in the phase information storage register d _Ph of the left element processor 10 in its own element processor 10. However, since the leftmost element processor 10 does not exist, its value is not determined. Therefore, in the case of the leftmost element processor 10, "0" is always stored in the phase information storage register d _Ph .

Next, the processing in step ST5 of the flowchart of FIG.
0, pixel data (pixel data of four neighboring points) from its four neighboring element processors
The procedure for storing the value in 0 will be described with reference to the flowcharts of FIGS.

In step ST5, which proceeds after step ST4 in FIG. 3, the processing after step ST21 shown in FIG. 5 is performed. At this time, as a result of the operation shown in the flowchart of FIG. 4, the input skip register 1 is stored in the local memory 15 of each element processor 10.
2 stores input pixel data skip input based on the pixel skip information stored in 2 and phase information corresponding to each pixel.

First, in step ST21, in all the element processors 10, the internal local memory 1
5, areas for storing four neighboring pixel data (registers d _L1 , d _C , d _R1 , and D 4) excluding pixels skipped at the time of input by the four neighboring element processors 10.
d _R2 ) and a 1-bit register d
Secure _SC . Note that the conversion ratio (enlargement ratio) is, for example, 1
If the number is doubled to doubled, the register d _L1 stores pixel data from the element processor 10 immediately to the left of one's own element processor 10, and the register d _C stores pixel data of the own element processor 10. , The register d _R1 has one element processor 1 to the right of its own element processor 10.
The pixel data from 0 is stored in the register d _R2 from the two next right element processors of the own element processor 10. Since the register d _SC stores pixel skip information, the register d _SC is hereinafter referred to as a skip information storage register d _SC .

In the next step ST22, in all the element processors 10, it is determined whether or not the pixel skip information stored in the input skip register 11 is "1". Is step ST23
If it is determined that the value is not "1" (it is "0"), the process proceeds to step ST25.

If it is determined in step ST22 that the pixel skip information stored in the input skip register 11 is "1", in step ST23, one of the element processors
Is stored in the register d _{C of} its own element processor 10. In the next step ST24, all the element processors 10 store the value of the input skip register 11 of the element processor 10 one to the left next to the skip information storage register d _SC in the local memory 15 of the own element processor 10.

On the other hand, if it is determined in step ST22 that the pixel skip information stored in the input skip register 11 is not "1" (is "0"), the process proceeds to step ST22.
In step 25, the values of the input pixel data of the respective element processors 10 are stored in the registers d _C of the respective element processors 10 in all element processors 10, and in the next step ST26, the values of the input skip registers 11 of the respective element processors 10 are stored. The value is stored in the skip information storage register d in the local memory 15 of the own element processor 10.
Store in _SC .

Next, in step ST27, it is determined whether or not the value (bit) of the register d _SC in the local memory 15 of the one adjacent one of the element processors 10 is "1" in all the element processors 10. And “1”
When it is determined that is, the process proceeds to step ST28 and thereafter, and when it is determined that it is not “1” (is “0”), the process proceeds to step ST29 and thereafter.

If it is determined in step ST27 that the value is "1", in step ST28, the pixel data in the local memory 15 of the element processor 10 which is two blocks to the left of the own element processor 10 in all the element processors 10 _Is stored in the register d _L1 of the own local memory 15.

On the other hand, if it is determined in step ST27 that it is not “1”, in step ST29, all the element processors 10
Local memory 15 of the element processor 10 to the left of
The upper pixel data is stored in the register d _L1 of its own local memory 15.

Next, the process proceeds to step ST31 of the flowchart in FIG. 6. In this step ST31, the skip information storage register d _{SC in} the local memory 15 of the one next to the right one in all the element processors 10 is read. It is determined whether or not the value (bit) is "1". When it is determined that the value (bit) is "1", the process proceeds to step ST32 and thereafter, and when it is determined that the value (bit) is not "1"("0"). Proceeds to step ST34 and subsequent steps.

If it is determined in step ST31 that the value is "1", then in step ST32, the pixel data in the local memory 15 of the element processor 10 which is two elements to the right of each element processor 10 in all the element processors 10 respectively. Is stored in the register d _R1 of the local memory 15 of the own device.
The value of _SC is shifted left by two (sequentially shifted to the register d _SC of the two left element processors 10).

On the other hand, if it is determined in step ST31 that it is not "1", in step ST34, all the element processors 10
Local memory 15 of the element processor 10 immediately to the right of
The upper pixel data is stored in the register d _R1 of the local memory 15 of its own, and in step ST35, the value of the register d _SC is shifted left by one (to the register d _SC of one element processor 10 on the left side). shift.

In the next step ST36, one of the element processors 1 on the right side is
It is determined whether or not the value (bit) of the register d _SC on the local memory 15 of “0” is “1”. When it is determined that the value is “1”, the process proceeds to step ST37 and the subsequent steps.
If it is determined that it is not 1 "(it is" 0 "), the process proceeds to step ST38 and thereafter.

If it is determined in step ST36 that the value is "1", then in step ST37, the pixel data in the local memory 15 of the element processor 10 immediately to the right of the element processor 10 by two in each of the element processors 10 is determined. _Is stored in the register d _R2 of the own local memory 15.

On the other hand, if it is determined in step ST36 that the value is not "1", in step ST38, all the element processors 10
Local memory 15 of the element processor 10 immediately to the right of
The upper pixel data is stored in the register d _R2 of the local memory 15 of the self.

Thereafter, the process proceeds to the next process, that is, the process of step ST6 in FIG.

In the above-described processing, in the linear array type multi-parallel processor 1, for example, the repetition of the processing of moving / not moving data is instructed by a flag, for example, so that the calculation is completed with a very small number of steps. In addition,
The reason why the enlargement ratio is limited to 1 to 2 is to simplify the concept. When the enlargement ratio is 2 or more, only the range in which pixel data is communicated between neighboring element processors is widened. Also in this case, the basic concept is the same, and the description is omitted.

The above-described step ST2 of FIG. 3 (FIG. 4)
And the flow chart), and in the operation of the step ST5 in FIG. 3 (the flowchart of FIG. 5 and FIG. 6), register d _L1 of the local memory _{15, d C, d R1,} d R2
And the phase information corresponding to each pixel similarly stored in the phase information storage register d _Ph of the local memory 15 has a relationship as shown in FIG. FIG. 7 also shows pixel skip information stored in the input skip register 12 and the output skip register 14, respectively. In the example of FIG. 7,
One element processor 10 corresponds to one column in the vertical direction in FIG. 7, where Y and Q indicate pixel data, respectively, and Ph indicates phase information. In this FIG.
In the case of the enlarged pixel number conversion, dummy data M is inserted in a portion skipped by the pixel skip information, and the total number of pixels is made equal to the number of output pixels at the input stage.
Note that the dummy data M is used to increase the number of pixels in advance at the time of input and make the data array suitable for SIMD control. The dummy data M is not used in an actual convolution operation. Therefore, the value of the dummy data M does not matter. The setting of whether or not to insert the dummy data M, in other words, whether or not to skip the input pixel data, requires only one bit. That is, for example, the dummy data M may be inserted at “1” (input pixel data is skipped), and the dummy data M may not be inserted at “0” (input pixel data is not skipped). Information indicating whether or not to insert such dummy data M is the pixel skip information.

Next, the processing in step ST7 of the flowchart of FIG. 3, that is, the convolution operation of the cubic coefficient at the time of conversion of the number of enlarged pixels and the pixel data of the above four neighboring points will be described.

As described above, the data of the four neighboring pixels stored in the registers d _L1 , d _C , d _R1 and d _R2 on the local memory 15 and the phase information stored in the phase information storage register d _Ph Is obtained, cubic coefficients corresponding to these pixels are obtained, and convolution operation is performed.

The cubic coefficient is calculated from the above equation (1), but is actually divided into two cases depending on the magnitude of | x |, and the final output is given by the following equation (16). In the case of the enlarged pixel number conversion, all the pixel skip information of the output skip register 14 is set to “0”, and the output pixel data is not skipped. Becomes

Q = C ₁ ((K + Ph) / K) * d _L1 + C ₂ (Ph / k) * d _C + C ₂ ((k-Ph) / K) * d _R1 + C ₁ (( 2K−Ph) / K) * d _R2 (16) where C ₁ (x) = − | x | ³ +5 | x | ² −8 | x | +4 C ₂ (x) = | x | ³ −2 | x | ² +1 Next, the case of reduced pixel number conversion will be described.

In the conversion of the number of reduced pixels, contrary to the above-described conversion of the number of enlarged pixels, input pixel data is not arranged at intervals according to the conversion ratio (reduction ratio) when pixel data is input. As described with reference to FIG. 41, when pixel data is output, output is performed while skipping output pixel data in accordance with a conversion ratio (reduction ratio). In the present embodiment, the above-described pixel skip information is used as information for arranging output pixel data discretely (input pixels are continuously arranged) during the conversion of the number of reduced pixels. In addition, the interpolation pixel data in the case of the conversion of the number of reduced pixels is the same as that at the time of the enlargement. Each of the four pixel data calculated from the input pixel data of four points near the desired output pixel and the phase information corresponding to each pixel. It is generated by performing a convolution operation with the cubic coefficient of a point. In order to perform such a reduced pixel number conversion, the above-described pixel skip information, phase information corresponding to each pixel for calculating a cubic coefficient, and the above four neighboring pixels for generating a desired output pixel Data is needed.

FIG. 8 shows the overall flow of the reduced pixel number conversion processing. Note that here, as the above-described reduced pixel number conversion,
An example in which the size is reduced to L: K is given. Here, K and L are positive integers, and K <L.

In FIG. 8, first, at step ST4
At 1, the L: K conversion ratio (enlargement ratio) is set.

In the next step ST42, all element processors 10 calculate pixel skip information and phase information. The details of the calculation of the pixel skip information and the phase information in step ST42 will be described later.

In step ST43, it is determined whether or not the input of the pixel data of the next line is possible, and this determination is repeated until the input of the pixel data of the next line is enabled. When the input of the pixel data of the next line is enabled in the step ST43, the input of the pixel data of one line is performed in the next step ST44.

In step ST45, the input pixel data to the own element processor 10 and the pixel data of the four element processors 10 in the vicinity of the own element processor 10 (pixel data of four neighboring points) are converted to the own element processor. 10 is stored in the local memory 15. The details of the process in step ST45 will be described later.

In step ST46, a cubic coefficient is calculated from the phase information. That is, the calculation using the above-described equation (1) is performed.

In step ST47, the above-mentioned step ST
The convolution operation of the cubic coefficient obtained at 46 and the pixel data of the above four neighboring points is performed. The details of the convolution operation will be described later in Expression (17).

In step ST48, the calculation for one line is performed, and the obtained interpolation pixel data is output. After that, the process returns to the process after step ST43.

In the case of the conversion of the number of reduced pixels, as in the case of the conversion of the number of enlarged pixels, the pixel skip information and the phase information in step ST42 described above are stored in, for example, a CPU outside the linear array type multi-parallel processor (DSP). It is possible to calculate in advance by a preprocessor such as a central processing unit) and input the data via the input register 11 before performing the convolution operation with the actual pixel data.
The pixel skip information is stored in the input skip register 12 and the output skip register 14, and the phase information is stored in, for example, a phase information storage register provided in the local memory 15. Further, the pixel skip information and the phase information are, as in the case of the conversion of the number of enlarged pixels,
SIMD-controlled linear array type multi-parallel processor 1
It is also possible to calculate internally, for example, during a video blanking interval or when power is turned on. That is, for example, in the case of pixel number conversion in which the conversion ratio is constant in one scan line in which the conversion ratio does not change depending on the position of the pixel in the horizontal direction,
The pixel skip information and the phase information are stored in the processor (D
SP) 1 can be easily calculated. If all the processes including the generation of the pixel skip information and the phase information are realized only inside the processor 1, the entire system configuration can be simplified. In this case, the pixel skip information is stored in the input skip register 12 and the output skip register 14, and the phase information is stored in the phase information storage register in the local memory 15.

Hereinafter, a method of calculating pixel skip information and phase information inside the processor 1 that has been subjected to the SIMD control as described above during conversion of the number of reduced pixels will be described. In the case of this reduced pixel number conversion as well, the calculation of the pixel skip information and the calculation of the phase information need not always be performed at the same time, but there are many common operations in the setting of the pixel skip information and the calculation of the phase information. Since it is more efficient to share the resources of the registers in the local memory 15 of the processor 1, the program memory area, the number of execution steps, and the like, an example of an algorithm for obtaining pixel skip information and phase information at the same time is shown here. This calculation may be performed in the video blanking interval or after the power is turned on as described above.

FIG. 9 shows a procedure for calculating pixel skip information and phase information in the above-described reduced pixel number conversion inside the linear array type multi-parallel processor 1 controlled by SIMD.

In step ST2 following step ST41 in FIG. 8, step ST5 shown in FIG.
The processing after step 1 is performed.

First, in step ST51, an area for storing phase information (the phase information storage register d _Ph ) and a working register are secured in the local memory 15.

In step ST52, in all the element processors 10, one element processor
_Is added to the value (phase information) stored in the phase information storage register d _Ph of the local memory 15, and the obtained value is stored in the working register of the local memory 15.

In the next step ST53, each element processor 10 subtracts K from the value stored in the phase information storage register d _Ph of the element processor 10 immediately to the left of one of its own element processors 10, _Is stored in the phase information storage register d _Ph in the local memory 15 of the element processor 10.

In step ST54, step ST54 is executed.
At 52, it is determined whether or not the value stored in the working register is smaller than twice the value of K. If it is determined in step ST54 that the value is smaller than twice the value of K, the process proceeds to step ST55. If it is determined that the value is equal to or more than twice the value of K, the process proceeds to step ST57.

In step ST55, L is added to the value stored in the phase information storage register d _Ph , and the obtained value is stored again in the phase information storage register d _Ph . In the next step ST56, the output skip register 14
Is stored as "0". That is, the element processor 1
The pixel data fetched from the 0 local memory 15 is stored in the output register 13 without skip and output.

On the other hand, in step ST57, which proceeds when it is determined in step ST54 that the value stored in the working register is not less than twice the value of K, "1" is stored in the output skip register 14. That is, the pixel data extracted from the local memory 15 of the element processor 10 is skipped by one and output from the output register 13.

Steps ST56 and ST5
After step 7, the process proceeds to step ST58. This step ST
At 58, it is determined whether or not the above-described processing has been completed for all pixels of one line (at least larger than the number of all element processors 10). Repeat the process,
When it is determined that the process has been completed, the next process, that is, FIG.
The process proceeds to step ST43.

However, also in the algorithm shown in FIG. 9, each element processor 10 stores the value stored in the phase information storage register d _Ph of the left element processor 10 in the same manner as in the above-described enlarged pixel number conversion. Is stored in the element processor 10, the value of the leftmost element processor 10 is not determined because the left element processor does not exist. Therefore, in the case of the leftmost element processor 10, "0" is always stored in the phase information storage register d _Ph .

Next, the processing in step ST45 of the flow chart of FIG. 8, that is, in each element processor 10, pixel data (pixel data of four neighboring points) from four neighboring element processors is stored in its own element processor 10. The storing procedure will be described with reference to the flowchart of FIG.

In step ST45 following step ST44 in FIG. 8, step ST6 shown in FIG.
The processing after step 1 is performed. At this time, as a result of the operation shown in the flowchart of FIG. 8, the local memory 15 of each element processor 10 stores input pixel data and phase information corresponding to each pixel.

First, in step ST61, in all the element processors 10, the internal local memory 1
5, areas for storing four neighboring pixel data (registers d _L1 , d _C , d _R1 , and D 4) excluding pixels skipped at the time of input by the four neighboring element processors 10.
d _R2 ) and a 1-bit skip information storage register d _SC . Assuming that the conversion ratio (enlargement ratio) is, for example, 1 to 2 times, the register d _L1 stores pixel data from the element processor 10 immediately to the left of the own element processor 10 and the register d _C. Contains the pixel data of its own element processor 10,
The pixel data from the element processor 10 immediately to the right of the own element processor 10 is stored in the register d _R1.
R2 stores pixel data from the element processor two adjacent to the element processor 10 to the right. This is the same as in the case of the above-described conversion of the number of enlarged pixels.

In the next step ST62, in all the element processors 10, the value of the input pixel data is stored in the register d _C of the local memory 15.

In the next step ST63, in all element processors 10, their own element processors 10
The input pixel data stored in the register d _C of the element processor 10 immediately to the left of the element processor 10 is stored in the register d _L1 of its own element processor 10.

In step ST64, in all the element processors 10, the input pixel data stored in the register d _C of the element processor 10 immediately to the right of the own element processor 10 is read.
0 is stored in the register d _R1 .

In the next step ST65, all the element processors 10 execute their own element processors 10
The input pixel data stored in the register d _C of the element processor 10 immediately to the right of the element processor 10 is stored in the register d _R2 of its own element processor 10.

Thereafter, the process proceeds to step ST46 in the flowchart of FIG.

The above processing is completed in the linear array type multi-parallel processor 1 with a very small number of steps required to use the communication function of the pixel data near each of the element processors 10.

By performing the operations of FIGS. 8 to 10 described above, the registers d _L1 , d _C ,
The relationship between the four pixel data stored in d _R1 and d _R2 and the phase information corresponding to each pixel stored in the phase information storage register d _Ph of the local memory 15 also has a relationship as shown in FIG. . Note that FIG. 11 shows the same as FIG. 7, and shows the output pixel data in which Gs in FIG. 11 is skipped.

Next, the processing in step ST47 of the flowchart of FIG. 8, that is, the convolution operation of the cubic coefficient at the time of conversion of the number of reduced pixels and the pixel data of the above four neighboring points will be described.

As described above, the data of the four neighboring pixels stored in the registers d _L1 , d _C , d _R1 , and d _R2 on the local memory 15 and the phase information stored in the phase information storage register d _Ph Is obtained, cubic coefficients corresponding to these pixels are obtained, and convolution operation is performed.

The cubic coefficient is calculated from the above equation (1), but is actually divided into two cases depending on the magnitude of | x |, and the final output is given by the following equation (17). In the case of the reduced pixel number conversion, the pixel data obtained by the interpolation operation is a value obtained by discretely outputting a value based on the following equation (10) based on the pixel skip information stored in the output skip register 14.

Q = C ₁ ((K + Ph) / K) * d _L1 + C ₂ (Ph / k) * d _C + C ₂ ((k-Ph) / K) * d _R1 + C ₁ (( 2K−Ph) / K) * d _R2 (17) where C ₁ (x) = − | x | ³ +5 | x | ² −8 | x | +4 C ₂ (x) = | x | ³ -2 | x | ² +1 As described above, the SIMD-controlled linear array type multi-parallel processor 1 can simultaneously calculate output pixel data for all pixels at most once according to the above-described equations. As described above, the linear array type multi-parallel processor 1 according to the embodiment of the present invention can perform the pixel number conversion process with a small number of steps by utilizing the SIMD control.

In the above description, the luminance signal is taken as an example, and a specific example in which the number of pixels of the chroma signal is converted in the SIMD-controlled linear array type multi-parallel processor 1 will be described below.

First, in the above-described conversion of the number of pixels of the chroma signal in the 4: 4: 4 format, since the format of the chroma signal is the same as the format of the luminance signal,
The same processing as the above-described conversion of the number of pixels of the luminance signal may be performed. In the linear array type multi-parallel processor 1, there is no need to add any hardware and only to add software for chroma signals, so that there is no additional circuit.

Next, the conversion of the number of pixels of the chroma signal in the 4: 2: 2 format will be described.

In the 4: 2: 2 format, as shown in FIG. 48, Cr and Cb are alternately and repeatedly arranged for each pixel, and each color difference signal exists only every other signal. In addition, as described above, in order to match the pixel position of the luminance and the color with the number of pixels, Cr and Cb are skipped at the time of inputting the pixel data, similarly to the luminance signal. However, since the order of arrangement of the color difference signals is changed at that time, the same processing as that for the luminance signal cannot be performed.

Therefore, in the present embodiment, a method is used in which cubic interpolation is performed for the luminance signal, and linear interpolation is performed for the chroma signal from data near the interpolation pixel.

FIG. 12 shows an example of 4: 2: 2 using this method.
1 shows an overall flow of a process of converting a chroma signal of a format into the number of pixels.

In FIG. 12, in order to perform the pixel number conversion processing of the 4: 2: 2 format chroma signal based on the SIMD control, an area for a flag register to be described later is first secured in the local memory 15 in step ST71. And
Information required for interpolation for the conversion of the number of enlarged pixels or the number of reduced pixels is calculated, and the obtained value is stored in the flag register. The details of the enlarged pixel number conversion process and the reduced pixel number conversion in step ST71 will be described later.

In the next step ST72, a step ST72 is executed.
Using the value of the flag register obtained at 71, the interpolation pixel neighborhood data, and the phase information obtained at the time of interpolation of the luminance signal, a linear interpolation process of the chroma signal is performed. The details of the process in step ST72 will be described later.

FIG. 13 shows a procedure for calculating information to be stored in the flag register in step ST71 in FIG. 12, for example, when converting the number of enlarged pixels.

In FIG. 13, first, in step ST81, in order to perform the pixel number conversion processing under the SIMD control, in each of the element processors 10, the flag registers F _IS ,
F _ICr , F _ICb and F _OCr are secured. The flag registers F _ICr and F _ICb are registers for storing a flag indicating whether the data input to the element processor 10 corresponds to the Cr signal or the Cb signal. For (RY signal), "1" is set and stored in the flag register F _ICr , and for Cb (BY signal), "1" is set and stored in the flag register F _ICb . In the following description, they will be referred to as a Cr input flag register F _ICr and a Cb input flag register F _ICb for distinction, respectively. Further, when these Cr and Cb are skipped, “0” is set and stored in the Cr input flag register F _ICr and the Cb input flag register F _ICb corresponding to the pixel. The flags stored in the flag register F _OCr correspond to the pixels to which Cr is to be output, and are “1” and “1”.
0 ”are alternately and repeatedly stored. In the following description,
The flag register F _{OCr is changed} to the Cr output flag register F
_I'll call it _OCr . Here, when “1” is stored in the Cr output flag register F _OCr , Cr is
On the other hand, when "0" is stored, Cb is output.

In the next step ST82, in all the element processors 10, the pixel skip information (the input skip register 12) is stored in the flag register F _IS of the local memory 15 at the time of the conversion of the number of enlarged pixels obtained by the processing of FIG. Copy the stored pixel skip information). As described above, the pixel skip information indicates that “1” indicates skipping and “0” indicates that it does not skip. Hereinafter, the flag register F _IS on the local memory 15 to which the pixel skip information is copied from the input skip register 12 will be referred to as an input skip flag register F _IS .

[0196] Next, in step ST83, a determination is made as to whether or not the input skip flag register F values are stored in the _IS "1" or, the process proceeds to step ST84 when the "1", "1" not equal ( If "0", the process proceeds to step ST85.

[0197] At step ST84 proceeds when the value stored in the input skip flag register F _IS in step ST83 is determined to be "1", in all the element processors 10, one of its own element processor 10, respectively the Cr input flag register F value stored in _ICr element processors 10 adjacent on the left, and stores the Cr input flag register F _ICr of its own element processor 10.

[0198] On the other hand, in step ST85 proceeds when the value stored in the input skip flag register F _IS in step ST83 is determined as "0", in all the element processors 10, self respective element processors 10 The inverted value of the value stored in the Cr input flag register F _ICr of the element processor 10 _immediately to the left is written into the Cr input flag register F of its own element processor 10.
_Store in _ICr .

Step ST84 and step ST84
After 85, the process proceeds to step ST86. Step S
At T86, in all the element processors 10, the Cr input flag registers F of the element processors 10 in which the value of the input skip flag register F _IS obtained in steps ST84 and ST85 is "1" are respectively set.
The value of _ICr is set to “0”.

In the next step ST87, all the element processors 10 store the inverted values stored in their own Cr input flag registers F _ICr in their own Cb input flag registers F _ICb .

In step ST88, in all the element processors 10, the element processors 10 in which the value of their own input skip flag register F _IS is "1" are set.
Then, the value of the Cb input flag register F _ICb is set to "
0 ”.

At next step ST89, all element processors 10 have their own element processors 10
Then, a value obtained by inverting the value stored in the Cr output flag register F _OCr of the element processor 10 _immediately to the _left of the _above is stored in the Cr output flag register F _OCb in its own element processor 10.

Thereafter, in step ST90, it is determined whether or not the above processing has been completed for all pixels of one line (at least more than the number of all element processors 10). ST8
3 and repeats the above-described processing. When it is determined that the processing has been completed, the processing proceeds to step ST72 in FIG.
That is, the process proceeds to the process of the flowchart shown in FIG.

Since the leftmost element processor 10 does not have a left element processor, the value of each flag register is not determined. Therefore, in the case of the leftmost element processor 10, "0" is always stored in each flag register.

Next, the above-described FIG.
The details of the linear interpolation processing in step ST72 of the flowchart of FIG. 14 will be described with reference to the flowchart of FIG.

That is, in the process of converting the number of expanded pixels, when a chroma signal is input, data is fetched into the local memory 15 by skipping with the same pixel skip information as the luminance signal. This local memory 1
5, a linear interpolation operation is performed from the value of the input chroma signal on 5 and the value stored in the flag register. In this linear interpolation, data at two points on the left and right sides of a desired interpolation point is searched, and interpolation is performed by linear addition according to phase information obtained by calculation at the time of processing the luminance signal.

The interpolation procedure is shown in the flowchart of FIG. Note that, here, for simplicity, the conversion ratio (enlargement ratio) is described up to twice. When the conversion ratio is 2 or more, the algorithm is basically the same except that the communication range with the neighboring element processors is widened. Although the following description focuses on processing with a Cr signal, the same applies to a Cb signal. In this case, in the flowchart of FIG. 14, the Cr right register d _CrR in each step described later is replaced by a Cb right register d _CbR , and similarly, the Cr left register d
The _CrL the Cb left register d _CbL, may be explained by replacing the Cr input flag register F _ICr the Cb input flag register F _{IC b.}

In FIG. 14, in step ST111, the local memory 15 stores the leftmost pixel value and the rightmost pixel value of each interpolation pixel for the Cr signal in the local memory 15.
The r right register d _CrR and the Cr left register d _CrL are secured. For the Cb signal, a Cb right register d _CbR and a Cb left register d _CbL are secured on the local memory 15 as an area for storing the leftmost pixel value and the rightmost pixel value of each interpolation pixel.

In step ST112, the 4: 2: 2 format chroma signal is stored in the chroma input register d _Ci secured in the local memory 15.

In step ST113, the values stored in the chroma input registers d _Ci of the four element processors 10 on the left side in all the element processors 10 are calculated as follows.
It is stored in the Cr left register d _{CrL of} its own element processor.

In the next step ST114, in all the element processors 10, the value of the Cr input flag register F _ICr of each of the three element processors 10 on the left is set to "".
In step ST114, _if the value of the Cr input flag register F _ICr of the three element processors 10 adjacent to the left is "1", the process proceeds to step ST114.
If it is not "1" (if it is "0"), it proceeds to step ST116.

In step ST114, the Cr input flag register F _{ICr of the} three element processors 10 on the left side is _set.
ST1 when it is determined that the value of is “1”
At 15, the value stored in the chroma input register d _Ci of the three element processors 10 on the left side is stored in the Cr left register d _CrL of its own element processor 10.

In step ST114, the Cr input flag register F _{ICr of the} three element processors 10 on the left is _used.
Is determined to be "0", and the process proceeds after the process of step ST115. In step ST116, in all the element processors 10, the Cr input flag register F of the element processor 10 two to the left of each is read.
_It is determined whether or not the value of _ICr is “1”. Step ST
At 116, the Cr of the element processor 10 on the two adjacent left
When the value of the input flag register F _ICr is “1”, the process proceeds to step ST117, and when the value is not “1” (“0”).
) At step ST118.

In step ST116, the Cr input flag register F _{ICr of the} two element processors 10 on the left side is _read.
ST1 when it is determined that the value of is “1”
At 17, the value stored in the chroma input register d _Ci of the two element processors 10 on the left side is stored in the Cr left register d _CrL of its own element processor 10.

In step ST116, the Cr input flag register F _{ICr of the} two element processors 10 on the left side is _set.
Is determined to be "0", and the process proceeds after the processing of step ST117. In step ST118, in all the element processors 10, the Cr input flag register F of each of the element processors 10 adjacent to the left one by one.
_It is determined whether or not the value of _ICr is “1”. Step ST
At 118, the Cr of the element processor 10 on the next left
When the value of the input flag register F _ICr is “1”, the process proceeds to step ST119, and when the value is not “1” (“0”).
) Directly proceeds to the next process shown in FIG.

In step _{ST118, the} Cr input flag register F _ICr of the element processor 10 one _{immediately to the left is used.}
ST1 when it is determined that the value of is “1”
In step 19, the value stored in the chroma input register d _Ci of the element processor 10 on the _immediately left _side is stored in the Cr left register d _CrL of its own element processor 10.

In the above step _{ST118, the} Cr input flag register F _ICr of the element processor 10 one _{immediately to the left is used.}
Is determined to be "0", and in step ST121 of the flowchart of FIG. 15, which proceeds after the processing of step ST119, all the element processors 10 have the Cr of their own element processors 10.
It is determined whether the value of the input flag register F _ICr is “1”. In step ST121, the value of the Cr input flag register F _ICr of its own element processor 10 is set to “
If it is "1", the process proceeds to step ST122, and "1"
If not (when it is "0"), step ST1 is performed as it is.
Proceed to step 23.

Step ST122 when it is determined in step ST121 that the value of the Cr input flag register F _ICr of its own element processor 10 is "1".
Then, the value stored in the chroma input register d _Ci of the element processor 10 is stored in the Cr left register d _CrL of the element processor 10.

When it is determined in step ST122 that the value of the Cr input flag register F _ICr of its own element processor 10 is "0" and after the processing in step ST122, the process proceeds to step ST123.
In all the element processors 10, the values stored in the chroma input registers d _Ci of the four element processors 10 on the _right are stored in the Cr write register d _CrR of the own element processor.

In the next step ST124, in all the element processors 10, the value of the Cr input flag register F _ICr of each of the three element processors 10 on the _right is set to "".
In step ST124, when the value of the Cr input flag register F _ICr of the three element processors 10 on the _right side is "1", step ST124 is performed.
The process proceeds to 125, and when it is not “1” (when it is “0”), the process directly proceeds to step ST126.

In step ST124, the Cr input flag register F _{ICr of the} three element processors 10 on the _{right is used.}
ST1 when it is determined that the value of is “1”
At 25, the value stored in the chroma input register d _Ci of the three element processors 10 on the right _side is stored in the Cr write register d _CrR of its own element processor 10.

In step ST124, the Cr input flag register F _{ICr of the} three element processors 10 on the _{right is used.}
Is determined to be "0", and the process proceeds after the processing of step ST125. In step ST126, the Cr input flag register F of each of the two adjacent right-hand element processors 10
_It is determined whether or not the value of _ICr is “1”. Step ST
At 126, the Cr of the element processor 10 on the two right neighbors
When the value of the input flag register F _ICr is “1”, the process proceeds to step ST127, and when the value is not “1” (“0”).
) Directly proceeds to step ST128.

In step ST126, the Cr input flag register F _{ICr of the} two element processors 10 on the _{right is used.}
ST1 when it is determined that the value of is “1”
At 27, the value stored in the chroma input register d _Ci of the two element processors 10 on the right _side is stored in the Cr write register d _CrR of its own element processor 10.

In step ST 126, the Cr input flag register F _{ICr of the} two element processors 10 on the _{right is used.}
Is determined to be "0", and the process proceeds after the processing of step ST127. In step ST128, in all the element processors 10, the Cr input flag registers F of the element processors 10 one by one on the right are respectively.
_It is determined whether or not the value of _ICr is “1”. Step ST
128, the Cr of the element processor 10 immediately to the right
When the value of the input flag register F _ICr is “1”, the process proceeds to step ST129, and when the value is not “1” (“0”).
) Directly proceeds to the next process shown in FIG.

In step ST128, the Cr input flag register F _ICr of the element processor 10 immediately to the right of one is _read.
ST1 when it is determined that the value of is “1”
At 29, the value stored in the chroma input register d _Ci of the element processor 10 on the _{immediately right side} is stored in the Cr write register d _CrR of its own element processor 10.

In step ST128, the Cr input flag register F _ICr of the element processor 10 _{immediately to the right is read.}
Is determined to be "0", and in step ST131 of the flowchart in FIG. 16, the process proceeds after the process of step ST129.
It is determined whether the value of the input flag register F _ICr is “1”. In the step ST131, the value of the Cr input flag register F _ICr of the own element processor 10 is changed to “
If it is "1", the process proceeds to step ST132, and "1"
If not (when it is "0"), step ST1 is performed as it is.
It proceeds to the process of 33.

Step ST132 when it is determined in step ST131 that the value of the Cr input flag register F _ICr of the element processor 10 is "1".
Then, the value stored in the chroma input register d _Ci of the element processor 10 is stored in the Cr write register d _CrR of the element processor 10.

In step ST132, when it is determined that the value of the Cr input flag register F _ICr of the element processor 10 is "0", and after step ST132, the process proceeds to step ST133.
In all the element processors 10, the Cr write register d _CrR for storing Cr left register d _CrL and top right pixel values for storing the leftmost neighboring pixel value of the interpolation data for the Cr signal, determined by calculation of the luminance signal Interpolation by linear addition is performed according to the obtained phase information.

In the next step ST134, processing for the case of the Cb signal is performed. That is, also for the Cb signal, the steps ST112 in FIG.
Replace the Cr write register d _CrR in 143 Cb write register d _CbR, Cr left register d
_{The same} processing as described above is performed by replacing _CrL with the Cb left register d _CbL and _replacing the Cr input flag register F _ICr with the Cb input flag register F _ICb , and obtains interpolation data of the Cb signal by linear addition interpolation.

In the next step ST135, in all element processors 10, the Cr output flag register F
It is determined whether or not the value of _OCr is “1”, and
When the value of the output flag register F _OCr is “1”, the process proceeds to step ST137, and when it is not “1” (when it is “0”), the process proceeds to step ST136.

[0231] The value of the Cr output flag register F _OCr outputs the interpolated data for Cr signals obtained in step ST137 In step ST133 proceeds when it is "1", conversely the Cr output flag register F _OCr In step ST136 to which the process proceeds when the value is "0", interpolation data for the Cb signal obtained in step ST134 is output, and interpolation data for the Cr signal and interpolation data for the Cb signal are selected for each pixel. Then, it is stored in a 4: 2: 2 format output register for Cr and Cb signals provided on the local memory 15.

Next, at the time of the above-described conversion of the number of enlarged pixels, the pixel data is discretely stored in the input register 11 at the time of inputting pixel data, and is directly output from the output register 13 at the time of output. In the conversion, when pixel data is input, the data is stored in the input register 11.
Is output straight from the output register 13 at the time of output. The interpolation processing in the reduced pixel number conversion is the same as that in the enlarged pixel number conversion, and therefore the description is omitted, and the preprocessing part of the interpolation calculation will be described here.

Also in the case of this reduced pixel number conversion, in the all element processor 10, first, the Cr input flag register F _ICr , the Cb input flag register F _ICb and the Cr output flag register F _OCr are stored in the local memory 15 in advance. Secure. Also at the time of the reduced pixel number conversion, to secure the output skip flag register F _OS for storing pixel skip information stored in the output skip register 14 to the local memory 15. Each of these flag registers is a 1-bit register.

The input Cr flag register F _ICr
Similarly, the input Cb flag register F _ICb stores the data input to its own element processor 10 as a Cr signal,
This is a register for storing a flag indicating which of the Cb signals it corresponds to. For example, if certain data is Cr, “1” is set and stored in the flag register F _ICr ,
If so, "1" is set and stored in the flag register F _ICb . In the case of the reduced pixel number conversion, the Cr input flag register F _ICr and the Cb input flag register F _ICb store a value in which “1” and “0” are alternately repeated for each pixel. The pixels corresponding to the register F _ICr and the Cb input flag register F _ICb are inverted. Also, the Cr output flag register F _OCr
In the same manner as described above, corresponding to the pixel to output Cr
A value in which “1” and “0” are alternately repeated is stored.
When “1” is stored in the output flag register F _OCr , Cr is output, and when “0” is stored, Cb is output.

When the process of converting the number of reduced pixels is performed by SIMD control, step ST in the flowchart of FIG.
The procedure for calculating the information stored in the flag register at 71 is as shown in the flowchart of FIG. 17 below.

In FIG. 17, first, at step ST1
01, the output skip flag register F _OS for one bit and the Cr input flag register F _ICr and C
The b input flag register F _ICb and the Cr output flag register F _OCr are secured.

In the next step ST102, the output skip flag register F _OS of the local memory 15 in each of the element processors 10 stores the pixel skip information (output skip register) at the time of the conversion of the reduced pixel number obtained in the processing of FIG. 14 is copied. Note that, as described above, this pixel skip information indicates that "1" is skipped and "0" is not skipped.

[0238] Next, in step ST 103, performs output skip flag register F _OS is the value stored in the "1" determine whether or not each in all element processors 10, when "1", the process proceeds to step ST 104, "
If it is not "1" (when it is "0"), step ST10
Go to 5.

In step ST104, to which the process proceeds when the value stored in the output skip flag register F _OS is determined to be “1” in step ST103, all of the element processors 10
One immediate left Cr output flag register F _OCr value stored in the element processors 10 of 0 is stored in the Cr output flag register F _OCr of its own element processor 10.

[0240] On the other hand, the value stored in the output skip flag register F _OS in step ST103 is "0"
In step ST105, the process proceeds when all the element processors 10 determine the inverted value of the value stored in the Cr output flag register F _OCr of the element processor 10 one to the left of the own element processor 10. , Stored in the Cr output flag register F _OCr of its own element processor 10.

These steps ST104 and S104
After T105, the process proceeds to Step ST106. In step ST106, it is determined whether or not the above-described processing has been completed for all pixels of one line (at least more than the number of all element processors 10), and when it is determined that the processing has not been completed, the process returns to step ST103. The above processing is repeated, and when it is determined that the processing has been completed, the processing proceeds to the next processing, that is, the processing of the flowcharts in FIGS. However, in the flowcharts of FIGS. 14 to 16 at this time, the Cr obtained by the process of FIG.
Input flag register F _ICr and Cb input flag register F
_{The same} processing as described above is performed using the values of the _ICb and Cr output flag registers F _OCr , and the reduced pixel number conversion processing is performed in 4:
A chroma signal output of 2: 2 format is obtained.

In the case of this reduced pixel number conversion process,
Since the leftmost element processor 10 does not have the leftmost element processor, the value of each flag register is not determined. Therefore, the leftmost element processor 1
In the case of 0, "0" is always stored in each flag register.

In addition to the conversion of the number of enlarged pixels and the conversion of the number of reduced pixels in the 4: 2: 2 format by the method described above, the chroma signal of the 4: 2: 2 format is temporarily converted to the 4: 4: 4 format. It is also possible to carry out the conversion of the number of enlarged pixels or the number of reduced pixels.

From the 4: 2: 2 format to 4: 4:
The flow of format conversion into four formats is, for example, a flowchart as shown in FIG.

In FIG. 18, in step ST73, the 4: 2: 2 format chroma signal is converted to 4: 4: 4 format, and in the next step ST74, the 4: 4: 4 format chroma signal is converted as described above. Then, the number of enlarged pixels and the number of reduced pixels are converted.

Here, as an example of the format conversion from the 4: 2: 2 format to the 4: 4: 4 format in step ST73, a method as shown in FIG. 19 can be considered. That is, in FIG. 19, the Cr discrimination flag and the Cb discrimination flag are used, and the Cb discrimination flag and 4:
Cr signal after logical AND operation with 2: 2 chroma signal and Cr signal
A Cb signal obtained by performing a logical product operation of the determination flag and the 4: 2: 2 chroma signal is obtained.
b signal to 4: 4: 4 format Cr signal and Cb
The signal is obtained by calculation.

When the format conversion as shown in FIG. 19 is realized in the SIMD-controlled linear array type multi-parallel processor 1, the procedure is as shown in the flowchart of FIG.

In FIG. 20, in step ST141, the Cr determination flag for determining the 4: 2: 2 format Cr signal and the Cb determination flag for determining the Cb signal are prepared in the local memory 15. These C
The r determination flag and the Cb determination flag are generated inside the linear array type multi-parallel processor 1 and are stored in the local memory 15.
It may be prepared above, or it may be generated by the same numbering method as described in the generation of the Cr and Cb flags described above.

In the next step ST142, these Cr
The logical product (AN) of the determination flag and the Cb determination flag with the 4: 2: 2 format chroma signal in FIG.
D) Perform the operation.

In step ST143, a Cr signal obtained by the logical product operation and a signal in which 0 alternately repeats, and C
A signal in which the b signal and 0 are alternately repeated is stored in the local memory 1
5. Save on top.

In the next step ST144, the signals obtained in steps ST142 and ST143 are added to 1 / 2-, 1-1 / 2 3-tap FIR
Apply filtering. Although this is simply average interpolation, there is no problem with a chroma signal of 4: 2: 2 format for a luminance signal because the frequency band is originally narrow.

The thus obtained 4: 4: 4 format signal is output in step ST145.

Next, the conversion of the number of pixels of the chroma signal of the 4: 1: 1 format will be described.

At the time of converting the number of pixels of the chroma signal of the 4: 1: 1 format, as shown in the flowchart of FIG. 21, the linear array type multi-parallel processor 1 in the linear array type multi-parallel processor 1 in step ST75. The chroma signal is once converted into a 4: 2: 2 format chroma signal, and in the next step ST76, the above-described step S76 is performed.
The same pixel number conversion processing as described above is performed on the 4: 2: 2 format chroma signal obtained in T75.

The flow of the conversion process from the 4: 1: 1 format to the 4: 2: 2 format in step ST75 of FIG. 21 is as shown in the flowcharts of FIGS. The contents of the local memory 15 in the processing shown in FIGS. 22 to 24 are as shown in FIGS. 25 and 26. Although FIGS. 25 and 26 should be represented as one sheet in which FIG. 26 follows FIG. 25, they are represented as two figures due to space limitations. Hereinafter, the processing of FIGS. 22 to 24 will be described with reference to FIGS. 25 and 26.

First, in step ST151 shown in FIG. 22, a 1-bit discrimination flag for indicating the position of the most significant bit (MSB) of the 4: 1: 1 format chroma signal in the local memory 15 in each of the element processors 10. _Is secured in a discrimination flag register d _flg for storing. This discrimination flag is a four-cycle periodic signal shown as a discrimination flag signal in FIG. 25, and may be generated and input outside the linear array type multi-parallel processor 1, for example, or may be input in the numbering process. 1 may be generated internally. If you generate the determination flag in the linear array type multi-parallel processor 1 internal numbering process, and the determination flag register d _{fl g} communicate between the respective element processors 10 in the internal the processor 1,
Move left and right to match the MSB position of the 4: 1: 1 format chroma signal. In addition, the step ST15
In step 1, a 3-bit register (hereinafter referred to as a working register d _tmp ) is also secured on the local memory 15 as a working address space.

Next, in step S152, in all the element processors 10, the work register d on the local memory 15 of the one next to the left one
a value obtained by adding 1 to the value of _tmp, stored in the working register d _tmp self element processors.

In the next step ST153, it is determined whether or not the above processing has been completed for all pixels of one line (at least more than the number of all element processors 10). ST1
Returning to step 52, the above processing is repeated, and when it is determined that the processing has been completed, the process proceeds to step ST154.

In the next step ST154, as the value of the determination flag, a NOR operation is performed on each of the lower two bits of the 3-bit work register d _tmp , and the obtained value is used as the determination flag, The determination flag register d _flg secured in the memory 15 is stored. More specifically, the process of determining the determination flag in step ST154 will be described in more detail. It is determined whether the value of the lower 2 bits of the 3-bit work register d _tmp is “00” and the lower bit is determined. When the value of the two bits is "00", the determination flag is set to "1" and the lower two bits are set.
When the bit value is not “00”, the determination flag is set to “
0 ". However, since the leftmost element processor 10 does not have the leftmost element processor, the value of the discrimination flag is not determined. Therefore, in the case of the leftmost element processor 10, the discrimination flag is set. always"
0 "is given.

In the next step ST155, in all the element processors 10, the 8-bit 4: 2: 2 format chroma register chroma register d _Cout and the 8-bit working register WO ₁ are stored in the local memory 15 respectively. , to ensure the WO _2.

In the next step ST156, all the element processors 10 store the input Cr signal and the input Cb signal in the 4: 1: 1 format in the local memory 15 each of 2 bits.

That is, in step ST157, in all the element processors 10, the above-mentioned 4: stored in the local memory 15 of the three element processors 10 on the right side respectively:
The 2-bit input Cr signal in the 1: 1 format is stored in the 8-bit work register WO of the own element processor 10.
Stored in ₁ of the zeroth bit (shown as WO ₁ in FIG. 25) and the first bit (shown as FIG. 25 in WO ₁ +1).

In the next step ST158, similarly, in all the element processors 10, two bits of the input Cr signal of the 4: 1: 1 format stored in the local memory 15 of each of the two element processors 10 on the right are used. the second bit of the 8-bit working register WO ₁ of the own element processor 10 (FIG. 25 shows a WO ₁ +2)
And the third bit (indicated as WO ₁ +3 in FIG. 25). The process of step ST158 proceeds to step ST161 of the flowchart in FIG.

In step ST161 of FIG. 23, similarly, in all the element processors 10, 2 bits of the input Cr signal of the 4: 1: 1 format stored in the local memory 15 of one element processor 10 on the right next to each other. Is stored in the fourth bit (indicated as WO ₁ +4 in FIG. 25) and the fifth bit (indicated as WO ₁ +5 in FIG. 25) of the 8-bit working register WO ₁ of the element processor 10.

In the next step ST162, all the element processors 10 input the 2 bits of the input Cr signal in the 4: 1: 1 format stored in the local memory 15 of their own element processor 10 and
The sixth bit of the 8-bit working register WO ₁ (shown as WO ₁ +6 in FIG. 25) and the seventh bit (Fig. 25
In this case, it is stored as WO ₁ +7).

With the processing up to this point, the local memory 1
The working register WO ₁ in 5 will be the input Cr signal value as shown in (a) of FIG. 25 are stored.

In the following, similarly for work register WO ₂ , in step ST 163, all element processors 10
The two bits of the input Cb signal in the 4: 1: 1 format stored in the local memory 15 of each of the three element processors 10 on the right side are used to store the two bits of the 8-bit work register WO ₂ of the element processor 10 of its own. Stored in 0 bit and 1st bit.

In step ST164, in all the element processors 10, two element processors 1 adjacent to the right
0 of the input Cb signal in the 4: 1: 1 format stored in the local memory 15 of the 0th bit, and the second bit of the 8-bit work register WO ₂ of the element processor 10 of its own.
Stored in bit and third bit.

In step ST165, in all the element processors 10, each of the two
0 of the input Cb signal of the 4: 1: 1 format stored in the local memory 15 of the 4th bit of the 8-bit work register WO ₂ of the element processor 10 of its own.
Stored in bit and fifth bit.

In step ST166, in all the element processors 10, the 2 bits of the input Cb signal of the 4: 1: 1 format stored in the local memory 15 of the own element processor 10 are converted into the 8 bits of the 8 6th and 7th bits of work register WO ₂
Store in bits.

[0271] Next, in step ST167, in all the element processors 10, and the respective bits of the 8 bits of the stored working register WO ₁ as described above,
Wherein between the decision flag register d _flg stored in the determination flag bits, performs conjunction (AND) operation returns the resulting value to the working register WO _1, respectively.

[0272] This process results in the working register WO ₁ for example in the local memory 15 which is a value as shown in (b) of FIG. 25 are stored.

[0273] follows, in step ST169, similarly, stores in all the element processors 10, and the respective bits of the 8-bit working register WO ₂ stored as described above, the decision flag register d _flg is between determination flag bit was performs conjunction (aND) operation returns the resulting value to the working register WO _2, respectively.

[0274] Then, in step ST171 of the flowchart of FIG. 24, in all the element processors 10 for 8 bits of the working register WO _1, 1/2,
FIR filtering processing of 0, 1, 0, 1/2 taps is performed.

By the processing so far, the local memory 1
5 in the example in working register WO ₁ Figure 25 (c)
Will be stored.

[0276] Similarly, in step ST172, in all the element processors 10 for 8 bits of the working register WO _2, performs FIR filtering process 1 / 2,0,1,0,1 / 2 taps .

[0277] In the next step ST173, the value of the working register WO _1, the 4: stored in 2 format chroma register d _Cout of: 2.

Finally, in all element processors 10,
A logical OR (OR) operation is performed between the value of the working register WO ₂ of the one next to the element processor and the value of the chroma register d _Cout of the own element processor 10, and the obtained value is assigned to the own element processor. The chroma register d of the processor
_Return to _Cout .

By the processing so far, the local memory 1
4: 2: 2 format chroma register d _{Cout in 5}
Stores a value as shown in FIG. Also, in this chroma register d _Cout , the eight bits are represented by d _Cout , the first bit is represented by d _Cout +1 and the second bit is similarly to the case of the work register WO ₁ of FIG. _Is represented as d _Cout +2, and similarly, the seventh bit is represented as d _Cout +7.

Thereafter, the flow advances to the process of step ST76 in FIG.

Next, the configuration of the FIR filter in steps ST171 and ST172 in FIG. 24 can be the one as shown in FIG.

In FIG. 27, the chroma data is supplied to the input terminal 50 and is sequentially transmitted to the one-sample delay units 51 to 54 connected in series. These delay units 51 to 5
Numeral 4 delays the supplied data by one sample. The input data of the input terminal 50 and the output data of the delay units 51 to 54 are sent to the corresponding multipliers 55 to 59, respectively.

Each of the multipliers 55 to 59 has 1
/ 2, 0, 1, 0, 1/2 multiplication coefficient (filter coefficient)
Is set. Therefore, in each of the multipliers 55 to 59, the multiplication coefficient is multiplied by the input data to the input terminal 60 and each output data of each of the delay units 51 to 54.
The multiplication results of the multipliers 55 to 59 are added by the adder 60 and taken out from the output terminal 61 as an FIR filter output.

The FIR filter shown in FIG. 27 can be easily realized by performing proximity communication between the element processors 10.

As described above, if the 4: 1: 1 format chroma signal is converted into the 4: 2: 2 format chroma signal, then the pixel number conversion algorithm in the 4: 2: 2 format described above is applied. Alternatively, if the 4: 2: 2 format is further converted to the 4: 4: 4 format and the pixel number conversion algorithm in the 4: 4: 4 format is used, the 4: 1: 1 format can be used. The number of pixels can be converted.

In the above description, the embodiments of the conversion of the number of enlarged pixels and the conversion of the number of reduced pixels have been described. However, in these techniques, the input rate and the output rate of the pixel data are controlled independently. Accordingly, the present invention can be applied to the sampling frequency conversion processing as it is.

Next, the scanning line number conversion processing will be described.

In the scanning line number conversion processing according to the embodiment of the present invention, real-time scanning line number conversion, which is one of the features of the present invention, is also possible.

If the horizontal sample points of the video signal are viewed in the vertical direction and each pixel is replaced with a line, the number of scanning lines is converted, and the same concept as the conventional pixel number conversion can be applied. In this case, the input / output skip function may be adjusted by an external field FIFO memory or the like, and the control signal can be obtained simultaneously with the calculation of the line attribute information based on the line attribute information.

The arithmetic processing itself does not need to distinguish between a luminance signal and a chroma signal, and can be performed by the same processing.

In the pixel number conversion processing, pixels are performed in units of pixels, but if this is replaced with line units, the scanning line number conversion processing can be handled in the same manner. That is, the line to be interpolated is calculated from the cubic operation of the four line data near the input line and the line phase information. However, in the pixel number conversion processing, the pixel skip information and the pixel phase information shown in step ST2 of FIG. 3 are performed during a blanking interval or when power is turned on. However, in the scan line number conversion processing, input skip line information, The output skip line information and the line phase information are greatly different from each other in that each line is calculated, and the line phase information has registers for two types of phase information for enlargement and reduction. Thus, by having two types of line phase information, an arbitrary ratio conversion from reduction to enlargement is possible. Further, by controlling an external field memory and a processing program of the DSP itself by the input skip line control signal obtained from the two kinds of phase information and the skip line control signal, a local memory inside the DSP required for interpolation calculation is provided. The amount has been reduced.

FIG. 28 shows an example of a block configuration in the case of performing the pixel number conversion and the scanning line number conversion processing using the DSP. In this case, in the linear array type multi-parallel processor 72 of the DSP, the number of pixels is converted by the configuration (pixel number conversion unit 71) surrounded by the dotted line in the figure, and the scanning line number conversion processing is performed by other configurations. Is performed. Since the DSP is composed of software only, not hardware in the first place, the actual implementation method is different. However, if each of the internal signal processing is divided into blocks, it can be represented as shown in FIG. Since the number conversion unit 71 and the other number of scanning line conversion units can be divided, and the number of pixels conversion has already been described, the configuration and operation of the number of scanning line conversion processing will be described below.

A specific prescription for realizing the conversion of the number of scanning lines will be described. However, also in this case, since the linear array type multi-parallel processor is the same as that used in the pixel number conversion, the description of the configuration of the linear array type multi-parallel processor will be simplified here.

In FIG. 28, as described above, the pixel number converter 71 of the linear array type multi-parallel processor 72 includes an output skip pixel calculator 52 for calculating output skip pixels and an input skip pixel for calculating input skip pixels. It comprises a calculation unit 53, a filter unit 54 for luminance and chroma, and a pixel phase calculation unit 55.

The linear array type multi-parallel processor 7
The scanning line number conversion unit 2 includes a reduction line phase calculation unit 58 and an enlargement line phase calculation unit 62, an output skip line calculation unit 60 and an input skip line calculation unit 63, a line phase register 59, and an output skip line register. 6
1, a signal delay line 56 and a filter unit 57. The reduction line phase calculation unit 58 and the enlargement line phase calculation unit 62, the output skip line calculation unit 60 and the input skip line calculation unit 63, the line phase register 59, and the output skip line register 61 perform the pixel number conversion described above. It corresponds to the configuration for processing,
In these, processing is performed in line units.

A data input terminal 50 receives luminance and chroma signals, and these signals IR are supplied to a linear array type multi-parallel processor 72 via an external field memory 51. The signal IR supplied from the field memory 51 is supplied to the signal delay line 56 of the scanning line number conversion unit. This signal delay line 5
Numeral 6 is a signal for delaying the signal IR by 4H (4 horizontal cycles) and outputting it for each line. These signals for each line are sent to a filter unit 57 similar to the filter unit 54 described above. The output of the filter unit 57 is a pixel number conversion unit 71
Is sent to the external field memory 64 as an output signal OR through the filter unit 54 of FIG. This field memory 6
The luminance and chroma signals from 4 are output from the data output terminal 65 as an output obtained by converting the number of pixels or the number of lines.

The input skip line calculation unit 63
Outputs an input skip line control signal F _ISL as a control signal to be described later to the field memory 51. The output skip line register 61 outputs an output skip line control signal F _OSL as a control signal to the field memory 64 as described later. Is output. A control signal for the filter unit 57 is output from the line phase register 59.

Referring to FIGS. 29, 30, and 31, the overall flow of processing in the scanning line number conversion unit will be described.

Referring to FIG. 29, first, at step ST20
At 0, the conversion ratio N: M of the scanning line number conversion is set. However, N and M are positive positive numbers, and when M ≧ N, conversion of the number of enlarged scanning lines is performed, and when M <N, conversion of the number of reduced scanning lines is performed. The 1: 1 conversion at a conversion ratio of 1: 1 is included in the enlargement conversion.

The next step ST201 is executed for the first line of one frame of the image. Here, the line phase information d _phi used for calculating the input skip line and the line phase information d _phi used for calculating the output skip line are set. Information d
Initialize _pho . However, since there is a processing delay time in the linear array type multi-parallel processor, the line phase information d _pho is 0 to compensate for the delay, and the line phase information d _phi is an offset phase corresponding to the delay time. Do what you have.

[0301] In step ST202, the next line 1
It is determined whether or not it is possible to input pixel data for the line, and this determination is repeated until pixel data for the next line can be input. When the input of the pixel data of the next line is enabled in the step ST202, the input of the pixel data of one line is performed in the next step ST203.

In step ST204, according to an input skip line control signal F _ISL described later, if the input skip line control signal F _ISL is 0, step ST20
As shown in 5, the data for one line input in step ST203 is stored in the 4H delay line 56 on the local memory where the data to be interpolated is stored. On the other hand, if the input skip line control signal _FISL is 1, this line is regarded as unnecessary and is not stored in the 4H deline 56, its data is destroyed, and the process proceeds to step ST206.

This input skip line control signal F
_ISL is meaningful in the case of enlarged scan line conversion,
FIG. 32 shows an input skip line control signal F at the time of enlargement conversion.
The relationship between the _ISL and the data in the field memory 51 is illustrated.

[0304] figure L _in the FIG. 32 shows the line to be skipped, that is, the input skip line control signal F
_{When the ISL} is 1, the output of the field memory 51 is stopped and the data is not _fetched . When the _ISL is 0, the data from the memory is fetched and stored in the 4H delay line 56 necessary for the interpolation operation. Although the polarity of the input skip line control signal _FISL is 1 to skip and 0 to not skip, it is necessary to invert if the locality of the control signal of the field memory is reversed.

The control signal GRL of the 4H delay line 56 in FIG. 28 represents a so-called global rotation, where 1 indicates that each line data is delayed by one line, and 0 indicates that there is no delay. Since this is a line-by-line process, in the DSP, data in the local memory is moved, so that only a few tens of steps of instructions are required.

As a result, four lines of data required for cubic interpolation are obtained on the signal delay line 56. For example, in the case of FIG. 32, the line shown in FIG. 33 is stored in the local memory of the signal delay line 56.

[0307] The output skip line control signal F _OSL are those having a meaning in the reduced scanning line number conversion, the relationship between data output skip line control signal FOSL and the field memory 64 at the time of reducing conversion 34 Illustrated.

In FIG. 34, L _out indicates a skipped line. That is, when the output skip line control signal F _OSL is 1, input data to the field memory 64 is not taken in, and when it is 0, the output signal is not output. OR
Import data from Although the locality of the output skip line control signal F _OSL is 1 and skipped, and 0 is not skipped, if the _locality of the control signal of the field memory is reversed, it must be inverted. FIG. 35 shows the contents of the local memory at this time.

At step ST206, a cubic coefficient is calculated from the output skip line phase information _dpho . That is, the calculation using the equation (1) is performed. Here, there is skip line phase information d _phi other than output skip line phase information d _pho to represent the line phase information, but the input skip line phase information d _phi is not used for the actual interpolation calculation. This is used to determine the input skip line described in. As described above, there are two types of line phase information, d _phi and d _pho , but in an actual interpolation operation, only the output skip line phase information d _pho is used to enable arbitrary ratio conversion from reduction to enlargement.

[0310] In step ST207, the above step S
The line Q _V interpolated by the convolution operation of the cubic coefficient obtained in T206 and the pixel data of the above four neighboring lines is represented by the following equation (18).

Q _V = C ₁ ((M + d _pho ) / M) * d _p2 + C ₂ (d _pho / M) * d _p1 + C ₂ ((Md _pho ) / M) * d _c + C ₁ ((2M-d _oho ) / K) * d _n1 (18) where C ₁ (x) = − | x | ³ +5 | x | ² −8 | x | +4 C ₂ (x) = ^{| x | 3 -2 | x |} 2 +1 output skip line phase information d _pho is stored is output skip line phase information d _pho of the previous line register 60
(A register of the output skip line calculation unit 60), which will be described later. d _p2 , d _p1 , d _c , d
_n1 is obtained by delaying the input lines by 3H, 2H, 1H, and 0H lines, respectively.

FIG. 33 shows the state of each register of the local memory of each component at this time. The output skip line phase information _dpho has a certain value regardless of which pixel is taken in one line.

Steps ST208 and ST20
9. In step ST210, it is determined whether or not the next line is an output skip line. That is, N is added to the value stored in the output skip line phase register _dpho of the previous line, and if the obtained value is greater than twice the value of M, 1 is stored in the 1-bit register _FOSL. Then, the output line is skipped, and in the opposite case, 0 is stored in the register _FOSL , and the output line is set not to be skipped.

Next, step ST211, step ST2
212, in step ST 213, in accordance with the register F _OSL showing the output skip line to calculate the output skip line phase register d _pho the next line. If step ST209, if the calculated register F _OSL 1 in step ST210, the output skip line phase information register d _pho for the next line from the output skip line phase information register d _{p ho} of the current line and minus M, If not, add (NM).

Steps ST214 and ST21
5. In step ST216, it is determined whether or not the next line is an input skip line. That is, N is added to the value stored in the output skip line phase information register _dphi of the previous line, and if the obtained value is equal to or smaller than the value of M, 1 is stored in the 1-bit register _FISL. Then, it is assumed that the input line is skipped, and in the opposite case, 0 is stored in the register _FISL to set so that the input line is not skipped.

Next, steps ST217 and ST2
18, in step ST219, in accordance with the register F _ISL showing the input skip line, calculates an input skip line phase register d _phi of the next line. If step ST 214, if the register F _ISL is 1 calculated in step ST216, the input skip line phase information register d _phi of the next line from the input skip line phase information register d _phi of the current line and minus M, so If not, use the value as it is.

In step ST220, the data after the cubic interpolation operation obtained as described above, the output skip line control signal F _OSL and the input skip line control signal F
Output _ISL .

Up to step ST220 is the calculation for one line, and this is repeated for one frame. That is, it is determined in step ST222 whether the end of one frame has been reached. If so, the process returns to step ST201 in FIG. 29, and if not, the process returns to step ST202.

As described above, according to the embodiment of the present invention, the filter switching interpolation method (cubic filter interpolation method), which is difficult to realize with hardware due to the circuit scale and the complexity of the configuration, is used, The number conversion processing and the scanning line number conversion processing can be realized only by software processing using a linear array type multi-parallel processor DSP controlled by SIMD. It also supports conversion to an arbitrary number of pixels, which is difficult to achieve with a hardwired ASIC or the like, and supports arbitrary chroma formats of 4: 4: 4 format, 4: 2: 2 format, and 4: 1: 1 format. Can be made to correspond. In addition, unlike the conventional hard wired circuit, all formats and bit precision can be dealt with only by changing the software, so that there is no need to add a new circuit externally.

Further, according to the embodiment of the present invention, it is possible to convert the number of pixels and the number of scanning lines to arbitrary sizes in real time.

[0321]

In the present invention, a linear array type multi-parallel processor controlled by SIMD is used, and digital signal processing for conversion of the number of pixels at an arbitrary ratio and conversion of the number of scanning lines can be realized only by software processing. The number and the conversion ratio of the number of scanning lines can be set in real time, and can be set independently of each other. As for the conversion of the number of scanning lines, a control signal of a field memory provided outside is also calculated by a linear array type multi-parallel processor, thereby eliminating the need for a memory control circuit. In the present invention,
For example, not only 4: 4: 4 format but also 4: 2: 2
Format and any chroma format such as the 4: 1: 1 format.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram showing a basic configuration of a linear array type multi-parallel processor.

FIG. 2 is a block circuit diagram showing a schematic configuration of a linear array type multi-parallel processor according to the embodiment of the present invention.

FIG. 3 is a flowchart illustrating an entire flow of an enlarged pixel number conversion process for a luminance signal.

FIG. 4 is a flowchart showing a flow of calculation of pixel skip information and phase information of an input skip register in an enlarged pixel number conversion process for a luminance signal.

FIG. 5 is a flowchart showing a flow of a first half of calculation of four pixels near an input pixel in an enlarged pixel number conversion process for a luminance signal.

FIG. 6 is a flowchart illustrating a flow of the latter half of the calculation of four pixels near an input pixel in an enlarged pixel number conversion process for a luminance signal.

FIG. 7 is a diagram used to describe an operation of converting the number of pixels of an enlarged luminance signal.

FIG. 8 is a flowchart illustrating an overall flow of a reduced pixel number conversion process for a luminance signal.

FIG. 9 is a flowchart illustrating a flow of calculation of pixel skip information and phase information of an output skip register in a reduced pixel number conversion process for a luminance signal.

FIG. 10 is a flowchart illustrating a flow of a first half of calculation of four pixels near an input pixel in a reduced pixel number conversion process for a luminance signal.

FIG. 11 is a diagram used to explain the operation of reducing the number of pixels of a luminance signal.

FIG. 12 is a flowchart illustrating an overall flow of a pixel number conversion process of a 4: 2: 2 format chroma signal.

FIG. 13 is a flowchart showing a flow of calculation of a flag register in an enlarged pixel number conversion process of a 4: 2: 2 format chroma signal.

FIG. 14 is a flowchart showing a flow of a former stage of a linear interpolation process of a chroma signal in an enlargement (reduction) pixel number conversion process of a 4: 2: 2 format chroma signal.

FIG. 15 is a flowchart showing a middle stage flow of chroma signal linear interpolation processing in the expansion (reduction) pixel number conversion processing of a 4: 2: 2 format chroma signal.

FIG. 16 is a flowchart illustrating the flow of the latter stage of the linear interpolation process of the chroma signal in the enlargement (reduction) pixel number conversion process of the 4: 2: 2 format chroma signal.

FIG. 17 is a flowchart illustrating a flow of calculation of a flag register in an enlarged pixel number conversion process of a 4: 2: 2 format chroma signal.

FIG. 18 is a flowchart illustrating an overall flow when converting a 4: 2: 2 format to a 4: 4: 4 format and performing a pixel number conversion process of a chroma signal.

FIG. 19 is a diagram used for specific description of conversion from 4: 2: 2 format to 4: 4: 4 format.

FIG. 20 is a flowchart showing the flow of format conversion from 4: 2: 2 format to 4: 4: 4 format.

FIG. 21 is a flowchart illustrating an overall flow when performing a pixel number conversion process of a 4: 1: 1 format chroma signal.

FIG. 22 is a flowchart showing the first part of the flow of the format conversion from the 4: 1: 1 format to the 4: 2: 2 format.

FIG. 23 is a flowchart showing the middle part of the flow of format conversion from the 4: 1 :: 1 format to the 4: 2: 2 format.

FIG. 24 is a flowchart showing the second half of the flow of format conversion from the 4: 1 :: 1 format to the 4: 2: 2 format.

FIG. 25 is a diagram of the first half used for describing the contents of the local memory when converting the number of pixels in the 4: 1: 1 format.

FIG. 26 is a diagram of the latter half used for describing the contents of the local memory when converting the number of pixels in the 4: 1: 1 format.

FIG. 27 is a circuit diagram showing a configuration of an FIR filter used at the time of format conversion from a 4: 1: 1 format to a 4: 2: 2 format.

FIG. 28 is a diagram illustrating a configuration for performing a pixel number conversion process and a scan line number conversion process at an arbitrary ratio, and a block-divided process inside a linear array type multi-parallel processor.

FIG. 29 is a flowchart showing the flow of the former stage of the scanning line number conversion processing.

FIG. 30 is a flowchart showing a middle flow of a scanning line number conversion process.

FIG. 31 is a flowchart showing the flow of the latter stage of the scanning line number conversion process.

FIG. 32 is a diagram used to describe an operation of converting the number of enlarged lines of a luminance signal.

FIG. 33 is a diagram showing the contents of a local memory in the description of the operation of the conversion of the number of enlarged lines of a luminance signal.

FIG. 34 is a diagram used to describe an operation of reducing the number of lines of a luminance signal.

FIG. 35 is a diagram showing the contents of a local memory in the description of the operation of reducing the number of lines of a luminance signal.

FIG. 36 is a diagram used to explain the principle of 2: 3 enlarged pixel number conversion.

FIG. 37 is a diagram used for describing a cubic function.

FIG. 38 is a diagram used to explain the principle of 3: 2 reduced pixel number conversion.

FIG. 39 is a block circuit diagram showing a hardware configuration of a conventional pixel number conversion device.

FIG. 40 is a diagram used to explain the operation of 2: 3 enlarged pixel number conversion in a pixel number conversion device having a conventional hardware configuration.

FIG. 41 is a diagram used for describing an operation of 3: 2 reduced pixel number conversion in a pixel number conversion device having a conventional hardware configuration.

FIG. 42 is a diagram used to explain the principle of 2: 3 enlarged line number conversion.

FIG. 43 is a diagram used to explain the principle of 3: 2 reduction line number conversion.

FIG. 44 is a block circuit diagram showing a hardware configuration of a conventional scanning line number conversion device.

FIG. 45 is a diagram used to explain the operation of 2: 3 enlarged line number conversion in a scanning line number conversion device having a conventional hardware configuration.

FIG. 46 is a diagram used for describing the operation of 3: 2 reduced line number conversion in a conventional scanning line number conversion device having a hardware configuration.

FIG. 47 is a diagram showing a 4: 4: 4 format structure.

FIG. 48 is a diagram showing a 4: 2: 2 format structure.

FIG. 49 is a diagram showing a 4: 1: 1 format structure.

FIG. 50 is a diagram showing conversion from the 4: 1 :: 1 format to the 4: 2: 2 format.

[Explanation of symbols]

1 linear array type multi-parallel processor, 10 element processor, 11 input register, 12 input skip register, 13 output register, 14 output skip register, 15 local memory, 16 arithmetic processing unit, 50 data input terminal, 51 field memory, 52 reduction Output skip pixel calculation unit for pixel number conversion, 53 Input skip pixel calculation unit for enlargement pixel number conversion, 54 pixel number cubic interpolation operation processing unit, 55
Pixel phase calculator for pixel number conversion, 56 delay lines,
57 cubic interpolation operation processing unit for converting the number of scanning lines,
58, a line phase calculator for reducing the number of scanning lines, 5
9 line phase register, 60 output skip line calculator, 61 output skip line register,
62 line phase calculator for converting the number of enlarged scanning lines 63
Input skip line calculation unit, 64 field memory, 65 data output terminals, 71 pixel number conversion processing unit, 72 linear array type multi-parallel processor

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification symbol FI H04N 9/64 G06F 15/66 355D (72) Inventor Kenichiro Nakamura 6-7-35 Kita Shinagawa, Shinagawa-ku, Tokyo Sony Corporation Inside

Claims (26)

[Claims] 1. A plurality of element processors arranged corresponding to respective pixels in a one-dimensional direction of a digitized two-dimensional image and each of the one-dimensional pixel data sequentially input in a time-series manner; An image signal processing device comprising: a control unit for commonly controlling pixel data, wherein each of the element processors includes a temporary storage unit for temporarily storing pixel data of luminance and color difference, and input pixel data of luminance and color difference. Input pixel data storage means for storing and transferring to the temporary storage means, and pixel attribute information storage means for storing at least pixel attribute information representing the attribute of the pixel of luminance,
Pixel skip information storage means for storing pixel skip information for skipping pixel data of luminance and chrominance; and input pixel data of luminance and chrominance or pixel data of luminance and chrominance of a nearby element processor based on the pixel attribute information. Arithmetic operation means for storing the pixel data obtained by performing the predetermined operation used in the temporary storage means, and output pixel data storage means for storing and outputting the pixel data of the luminance and color difference extracted from the temporary storage means An image signal processing apparatus comprising: 2. In each of the above element processors, 4: 4: 4
2. The image signal processing apparatus according to claim 1, wherein the same processing is performed on pixel data of luminance and color difference in the format. 3. The arithmetic operation means of each of the element processors performs an interpolation operation on pixel data of the luminance in the 4: 2: 2 format using values of four neighboring pixels to obtain pixel data of the color difference. 2. The image signal processing apparatus according to claim 1, wherein a linear interpolation operation using a value of a neighboring pixel is performed. 4. Each of the element processors includes a format conversion unit for converting pixel data having a color difference of 4: 2: 2 format into a 4: 4: 4 format. The image signal processing apparatus according to claim 1, wherein the same processing is performed on pixel data of four formats of luminance and color difference. 5. Each of the element processors includes a format conversion unit for converting pixel data of a color difference in a 4: 1: 1 format into a 4: 2: 2 format. Performing an interpolation operation using the values of the neighboring four pixels on the pixel data of the luminance of the 4: 2: 2 format, and performing a linear interpolation operation using the values of the neighboring pixels on the pixel data of the chrominance. The image signal processing device according to claim 1, wherein: 6. Each of said element processors has a format conversion means for converting pixel data of a color difference of 4: 1: 1 format into 4: 4: 4 format. The image signal processing apparatus according to claim 1, wherein the same processing is performed on pixel data of four formats of luminance and color difference. 7. The input pixel data storage means of each of the element processors stores the input pixel data discretely or continuously based on the pixel skip information stored by the pixel skip information storage means. The image signal processing device according to claim 1. 8. An output pixel data storage means of each of said element processors stores pixel data from said temporary storage means discretely or continuously based on pixel skip information stored by said pixel skip information storage means. 2. The image signal processing device according to claim 1, wherein: 9. The control unit controls the rate of pixel data output from the output pixel data storage unit independently of the rate of pixel data input to the input pixel data storage unit. Item 2. The image signal processing device according to Item 1. 10. The image signal processing apparatus according to claim 1, wherein each of the element processors includes a pixel attribute information generation unit that generates the pixel attribute information. 11. A plurality of element processors arranged corresponding to each pixel in the one-dimensional direction of the digitized two-dimensional image and each pixel data in the one-dimensional direction being sequentially input in time series, and each element processor An image signal processing apparatus comprising: a control unit for commonly controlling the two-dimensional image data at an input unit and / or an output unit of an element processor arranged in a one-dimensional direction. A two-dimensional image data storage unit, wherein the element processor stores scanning line data temporary storage unit for temporarily storing luminance and color difference pixel data for each scanning line, and stores input scanning line data of luminance and color difference. Input scan line data storage means for transferring to the scan line data temporary storage means, and scan line attribute information for storing scan line attribute information representing the attribute of a scan line composed of pixels of at least luminance Information storage means, scan line skip information storage means for storing scan line skip information for skipping the scan line data, and scan line data or scan line data of a nearby element processor based on the scan line attribute information. Vertical arithmetic operation means for storing scan line data obtained by using a predetermined operation in the scan line data temporary storage means, and output for storing and outputting scan line data extracted from the scan line data temporary storage means Scanning line data storage means, and controlling data storage to the two-dimensional image data storage means or data extraction from the two-dimensional image data storage means based on the scanning line skip information, An image signal processing apparatus characterized in that the number is enlarged or reduced. 12. The skip scanning line for controlling data storage in the two-dimensional image data storage means and data retrieval from the two-dimensional image data storage means based on the scanning line attribute information. 12. The image signal processing apparatus according to claim 11, further comprising a skip scanning line arithmetic operation means for determining information. 13. The scanning line skip information storing means stores the scanning line skip information independently for enlargement and reduction of the number of scanning lines, and the scanning line attribute information storing means stores the scanning line attribute information. 12. The image signal processing apparatus according to claim 11, wherein the conversion of the number of scanning lines from reduction to enlargement is performed in real time by independently storing the number of scanning lines and the number of scanning lines for reduction. 14. An element processor, comprising: a pixel data temporary storage unit for storing and temporarily storing pixel data of luminance and chrominance; and a pixel data temporary storage unit for storing input pixel data of luminance and chrominance and storing the pixel data. Input pixel data storing means for transferring, pixel attribute information storing means for storing at least pixel attribute information representing an attribute of a pixel of luminance, input image skip information for skipping input pixel data of luminance and color difference, and luminance and color difference Pixel skip information storage means for respectively storing output pixel skip information for skipping output pixel data, and input pixel data of the luminance and chrominance or pixel data of luminance and chrominance of a nearby element processor based on the pixel attribute information. The pixel data obtained by performing the predetermined calculation used is stored in the pixel data temporary storage means in the horizontal direction. Arithmetic operation means, and output pixel data storage means for storing and outputting pixel data of the luminance and color difference extracted from the pixel data temporary storage means,
The image signal processing apparatus according to claim 11, wherein the number of pixels is also enlarged or reduced. 15. The method according to claim 15, wherein the pixel attribute information, the input pixel skip information, and the output pixel skip information are set for each scanning line time, and the number of pixels is enlarged or reduced in real time. Item 15. The image signal processing device according to Item 14. 16. The image signal processing apparatus according to claim 14, wherein said control means controls the switching of the element processor between conversion of the number of scanning lines and conversion of the number of pixels for each scanning line of the input image. . 17. The method according to claim 17, wherein the pixel attribute information, the pixel skip information, and the scan line skip information are set independently, so that enlargement or reduction is performed independently in the horizontal direction and the vertical direction. The image signal processing device according to claim 14. 18. An output image data rate of a two-dimensional image data storage means arranged at an output part of the element processor, wherein an input image data rate of a two-dimensional image data storage means arranged at an input part of the element processor is determined. 12. The image signal processing apparatus according to claim 11, wherein the control is performed independently. 19. In each of the above element processors, 4: 4:
15. The image signal processing device according to claim 14, wherein the same processing is performed on pixel data of four formats of luminance and color difference. 20. The horizontal arithmetic operation means of each of the element processors performs an interpolation operation on pixel data of the luminance in the 4: 2: 2 format using values of four neighboring pixels to obtain the pixel of the color difference. 15. The image signal processing device according to claim 14, wherein the data is subjected to a linear interpolation operation using a value of a neighboring pixel or a process of directly interpolating a value of a nearest pixel. 21. The vertical arithmetic operation means of each of the element processors performs an interpolation operation on the pixel data of the luminance in the 4: 2: 2 format using values of four neighboring lines to obtain the pixel of the color difference. 15. The image signal processing apparatus according to claim 14, wherein the data is subjected to a linear interpolation operation using a value of a neighboring line or a process of directly interpolating the value of a nearest pixel. 22. Each of said element processors is 4: 2: 2
A format conversion unit is provided for converting the color difference pixel data of the format into the 4: 4: 4 format. Each element processor performs the same processing on the luminance and color difference pixel data of the 4: 4: 4 format. 15. The image signal processing apparatus according to claim 14, wherein the processing is performed. 23. Each of said element processors is 4: 1: 1
A format conversion unit for converting the pixel data of the chrominance of the format into a 4: 2: 2 format, wherein the horizontal arithmetic operation unit of each of the element processors performs processing on the pixel data of the luminance of the 4: 2: 2 format. 15. The method according to claim 14, wherein an interpolation operation is performed using values of four neighboring pixels, and linear interpolation of the neighboring pixels or a process of directly interpolating the value of the nearest neighboring pixel is performed on the color difference pixel data. Image signal processing device. 24. The input pixel data storage means of each of the element processors stores the input pixel data discretely or continuously based on the pixel skip information stored by the pixel skip information storage means. The image signal processing device according to claim 14, wherein 25. The image signal according to claim 14, wherein a rate of an image output from said output pixel data storage means is controlled independently of a rate of pixel data input to said input pixel data storage means. Processing equipment. 26. The apparatus according to claim 14, wherein each of the element processors includes pixel attribute information generating means for generating the pixel attribute information, and scanning line attribute information generating means for generating the scanning line attribute information. The image signal processing device according to any one of the preceding claims.