JPH10191238A - Image processing simulator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image processing simulator which can correspond to various television systems and which plural investigators and users can use while sharing an image memory. SOLUTION: An image input/output unit which can switch the operations of a parallel address system for dividing the image memory 10 into four memory blocks 11-14, simultaneously accessing to four memory blocks and inputting/ outputting respective signal components and a serial address system for sequentially accessing to the respective memory blocks and inputting/outputting them is provided. At the time of using the image processing simulator, either address system can be selected and the memory blocks 11-14 of the image memory are divided into plural small blocks. A management table 6 storing information on the image memories by individual users is provided for a main memory connected to a processor in accordance with the respective small blocks. The management table allocates a memory area, which the user uses, in the small block unit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing simulator for performing an image processing operation on image data read from an image memory, storing the processed image data again in the image memory, and outputting the processed image data to a television monitor or the like. In particular, it relates to an input / output control of the image memory and a sharing system for a plurality of users.

[0002]

2. Description of the Related Art Image compression and decompression, feature extraction, rotation,
An image processing simulator is used to check whether an algorithm for image processing such as enlargement is appropriate or to conduct research. The development of image processing hardware (LSI) takes a long time, and in the case of insufficient performance, it takes much more time to re-create it, so that much time and cost are required.
However, if an image processing simulator is used, the quality of the algorithm can be checked before hardware is actually manufactured, so that development costs and time can be saved.

An image processing simulator has an image memory in which a video signal is converted into digital image data and recorded, and this image data is read out by a processor such as a CPU to perform image processing according to the purpose of use of the video. To an image memory, which is converted to analog and output to a television monitor or the like. Thus, the result of the image processing performed by the processor can be visually confirmed and evaluated.

[0004] Television signal systems are diversifying in line with the technological trends of digitization. Conventionally, NTSC, PAL,
Writing and reading of image information have been performed by changing the input / output control method with respect to the image memory in accordance with television systems such as EDTV and HDTV, and signal systems of R, G, B, Y, Cr and Cb. In recent years, component signals have
The α signal is added to the R, G, and B signals to enhance the convenience of image processing. The α signal is a key signal corresponding to the R, G, and B pixels, and is used for the synthesis processing. When a color difference signal is used, since there are only three signal components of luminance Y, red difference Cr, and blue difference Cb, α, R, G, and B composed of four signal components are used.
In a device used in combination with a signal, the use efficiency of the memory was reduced.

[0005] A method of storing a pixel row of R, G, B signals or Y, Cr, Cb signals in an image memory includes a parallel address system in which pixels of each signal component are separated and stored in parallel. And a serial address system in which pixels are connected and stored. The parallel address method is suitable for simulation such as image compression and decompression, and the serial address method is for image rotation,
Suitable for enlargement, reduction, image generation, etc.

[0006]

Conventionally, writing and reading of image information are performed by changing the input / output control method for the image memory in accordance with the image signal method. Only the recording and reproduction of image data of two television systems could be performed. Therefore, in order to use one image processing simulator in a plurality of television systems, an image memory dedicated to each system is required, and much cost and space are required. In addition, there is a problem that image memories are required for the number of users. SUMMARY OF THE INVENTION An object of the present invention is to provide an image processing simulator that can cope with various television systems and that can be used by a plurality of researchers and users by sharing an image memory.

[0007]

An image processing simulator according to the present invention is designed so that a plurality of users can use it in different formats. The image memory is divided into four memory blocks corresponding to signal components of image data. The parallel address method of simultaneously accessing the four memory blocks one by one for each signal component of the image data and inputting / outputting the pixels of each signal component, and the sequential access to each of the memory blocks one by one for each signal block An image input / output device that can switch between two types of operation of a serial address method for inputting / outputting a component pixel every four pixels is provided, and when using an image processing simulator, one of the address methods can be selected,
Each memory block of the image memory is further divided into a plurality of small blocks, and a main memory connected to the processor is provided with a management table for storing information on the image memory for each user corresponding to each small block. It is characterized in that a memory area used by a user is allocated in small block units by a table.

[0008]

FIG. 1 shows an example of the configuration of the main part of an image processing simulator. The input analog image signal is converted into digital image data by the AD converter 1 and recorded in the image storage device 2. The CPU 3 reads out the image data from the image storage device 2, performs image processing, and records the image data again in the image storage device 2. Although not shown, the image storage device 2 has an image memory and a CPU 3 for writing and reading image data to and from the image memory.
And an image input / output device to be performed together with the device. DA converter 4
Converts the image data after image processing output from the image storage device 2 into an analog signal and outputs the analog signal to an analog output terminal. Reference numeral 5 denotes a main memory connected to the CPU 3. In the illustrated example, digital input terminals and output terminals are provided in addition to analog terminals, and digital image data can be directly input to and output from the image storage device 2.

Video signals include R, G, B signals, Y, Cr,
There is a Cb signal and the like, and each is used according to the purpose. The R, G, and B signals are obtained by directly digitizing the three primary colors, and include the information of the primary colors most, and are used for industrial applications requiring performance and accuracy. Y, Cr, and Cb are divided into a luminance signal and a color difference signal, and have performance that does not cause any problem in the characteristics of human eyes. This is a signal suitable for a transmission system with a small amount of data.
b may be a half information amount.

FIG. 2 shows a pixel row after AD conversion in the case of Y, Cr and Cb signals. In the figure, C ₀ , C ₁ , C
₂ ‥‥ is a sampling clock, and Y ₀ , Y ₁ , Y ₂ ‥‥
Are luminance signals, Cb ₀ , Cb ₁ , Cb ₂ } and Cr ₀ ,
Cr ₁ and Cr ₂で are digital values of the color difference signal. As is clear from this figure, the frequency of the chrominance pixel signals Cr and Cb is half the frequency of the luminance signal Y, and two luminance signals Y can be sampled for each chrominance pixel signal Cr and Cb. Therefore, the input and output of these digital values to and from the image memory are performed by serially / parallel conversion of the luminance signal Y.
As described above, the luminance signal Ye can be divided into even-numbered luminance signals Ye and odd-numbered luminance signals Yo. Note that P ₀ , P ₁ , P ₂ } in FIG. 3 indicate pixel addresses.

Therefore, in the case of Y, Cr, Cb signals, the image storage device 2 stores the image data from the AD converter 1 in the image memory 10 as shown in FIG. Pixels can be fetched in series for each signal component by dividing into 13 and 14, and output to the DA converter 4 is possible. In this case, the two memory blocks 11 and 12 are Y
Allocated for storing signal data, the two memory blocks 11, 12 function as one continuous memory.

FIG. 4B shows R and R to which the α signal is added.
This is the case of G and B signals. As described above, even if a full component signal is received, image information can be captured while maintaining the four divisions. By increasing the address of the image memory from the CPU 3 in the direction of the arrow, it is possible to simultaneously access the addresses of four consecutive pixels for each signal component.

FIGS. 5 and 6 show an example of a parallel pixel array in which signal components of image data are recorded in parallel in an image memory 10 divided into four memory blocks 11, 12, 13, 14. FIG. ing. The address of the image memory from the CPU is increased in the direction of the arrow, and image data of the same address is accessed one by one from each signal component. FIG. 5 shows α,
FIG. 6 shows the case of the Y, Cr, and Cb signals. As described above, the image memory 10 in the case of the parallel pixel array is also divided into four memory blocks 11, 12, 13, and 14 in order to simultaneously access data of each signal component.

FIG. 7 is an explanatory diagram of an image storage device for realizing the access method from the CPU described with reference to FIGS. When a signal representing the type of the video signal is input to the terminal 20, the signal lines of the addresses ^{An + 1} and ^{An + 2} in the case of the α, R, G, B signals and the case of the Y, Cr, Cb signals. Connection is switched. FIG. 7 shows α, R, G, B
The case where switching is performed for a signal is shown. The switching of the signal lines is automatically performed by software processing according to the type of the video signal.

The image storage device includes an image memory 10 and an image input / output device for writing and reading data together with a CPU. Hereinafter, this configuration and operation will be described. The image memory 10 is a two-port memory having an input / output port for an AD converter and a DA converter, and a CPU input / output port. Four memory blocks 1 from the AD converter
Data is directly input to 1, 12, 13, and 14, respectively.
Four memory blocks from image memory 10 to DA converter
Data is directly output from 11, 12, 13, and 14, respectively.

By controlling the address signal line and the pixel data selection signal line by the CPU, the required address method,
Access in a pixel configuration is enabled. When switching to the serial address method, the signal line on the S1 side is connected to the CPU. In this case, A ⁰ alpha components to A ^n, R component, G component, simultaneously selected data for each respective four pixels B components by the address signal lines, the pixel data of the selected signal line-side address A ^{n + 1} , ^{An + 2} , the effective data is extracted.

FIG. 8 is an explanatory diagram of the image storage device when the video signals are Y, Cr, Cb signals. Video signal is Y, C
The signals indicating the r and Cb signals are input to the terminal 20, so that the pixel data selection signal side address A ^{n + 1} ,
The connection of the ^{An + 2} signal line is switched for the Y, Cr, and Cb signals. At this time, as for the data of the Y component of the luminance signal, the even number (Ye) and the odd number (Yo) are stored in the image memory.
It is stored in ten separate memory blocks 11,12.

For each of the R, G, B data and Y, Cr, Cb data, an example of a combination of addresses ^{An + 1} , ^{An + 2} and pixel data taken out at that time is shown in FIG.
Shown in Here, n indicates the weight of the address line, and n = 9 when considering 1024 addresses from P _O to P ₁₀₂₃ .

On the other hand, it is switched to the parallel address method,
If the side S2 of the signal line indicated by a broken line in FIGS. 7 and 8 are connected to the CPU, after taking out the data at address A ^0, A ¹ of the data selection signal line side, A ² to A n ⁺ Address ² is updated. FIG. 10 shows an example of the combination of the addresses A ⁰ and A ¹ at this time and the extracted pixel data for R, G, B data and Y, Cr, Cb data.

Note that α _n , R _n ,
G _n and B _n each represent 8-bit pixel data,
It is assumed that a gate signal is prepared for each bit.
As a result, the number of bits of data when accessing the image memory 10 from the CPU 3 is 32 bits. If the number of bits is 32 bits or an integer multiple thereof, α,
In any of the R, G, and B signals and the Yo, Ye, Cr, and Cb signals, four pixels can be simultaneously written or read by one access.

With the above-described configuration, the parallel address system in which each signal component of image data is simultaneously accessed one by one to four memory blocks to input / output pixels of each signal component, and It is possible to perform two operations of a serial address system in which each of the signal components is input and output every four pixels by sequentially accessing each one. A changeover switch for selecting an addressing method may be provided, and when using this image processing simulator, it is sufficient to switch to one of the addressing methods.

In each of the serial pixel array (FIG. 4) and the parallel pixel array (FIGS. 5 and 6), each of the memory blocks 11, 12, 13, and 14 of the image memory 10 is, for example, as shown in FIG. Many small blocks in units of 1 MW (megaword) 10
a. In FIG. 11, the addresses of A ^{0 to} A ^{n + 2} are 1
An example of a memory block 11 when divided into 024 small blocks 10a is shown. Many small blocks like this
A plurality of users register the use of several consecutive small blocks 10a with respect to 10a to secure a continuous memory area, so that image data of different formats can be stored.

A management table 6 as shown in FIG. 12 is provided in the main memory 5 (FIG. 1) so that the management can be performed even if the format is different for each user. In the management table 6,
Information on the image memory 10 for each user is stored.
The assignment of the user to each small block 10a is performed by the management table 6. As shown in FIG. 12, the management table 6 is composed of, for example, 256 tables 6a that can correspond to a total of 256 users, and each table 6a has a capacity of 256 bytes.

The contents of one table 6a are shown on the right side of FIG. Each table 6a is provided with a user entry flag bit X. When X = 0, it indicates that the table 6a is not used and the user is in an entry enabled state, and when X = 1, it indicates that another user is already in use and cannot enter. mmmmmm
mm is a place where the user name is written, and D _{1 to} D
_Reference numeral ₂₅₄ denotes an area in which management information such as the use start block number of the image memory, the number of used blocks, the image method, the image size, the number of frames, and the sampling frequency is written. By writing the user name in the memory area mmmmmmmm, a plurality of users can use the common image memory 10 without duplication.

The number of small blocks 10a specified by the user in the management table 6 is linked, and the use area of each user in the image memory 10 is formed in each of the memory blocks 11, 12, 13, and 14, as shown in FIG. You. Each user accesses the memory area of the image memory 10 allocated in this manner by a respective signaling method. As a result, the image simulator operates according to the time sharing method, and enables simultaneous use by a plurality of users using different signal methods. The example of FIG.
And user 3 use 100 and 150 small blocks 10a respectively in the NTSC system, and user 2 and user n use 200 and 150 small blocks 10a, respectively.
Is used in the HDTV system.

[0026]

According to the present invention, a plurality of users can simultaneously use the image processing simulator by sharing the data in the image memory and the image memory, even in different signal systems and television systems. Incorporation into a network or the like eliminates the need to prepare an image memory device for each user, and has the effect of saving space.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration example of a main part of an image processing simulator.

FIG. 2 is a diagram showing a pixel column;

FIG. 3 is a diagram showing a pixel column after serial-parallel conversion;

FIG. 4 is an explanatory diagram of a parallel pixel array.

FIG. 5 is an explanatory diagram of a serial pixel array in the case of α, R, G, and B signals.

FIG. 6 is an explanatory diagram of a serial pixel array in the case of Y, Cr, and Cb signals.

FIG. 7 is an explanatory diagram of an input / output operation for an image memory.

FIG. 8 is an explanatory diagram of an input / output operation for an image memory.

FIG. 9 shows a first combination of data.

FIG. 10 is a diagram showing a second combination of data.

FIG. 11 is a configuration diagram of a memory block.

FIG. 12 is a configuration diagram illustrating an example of a management table.

FIG. 13 is an explanatory diagram showing a relationship between a management table and an image memory.

[Explanation of symbols]

 6 Management table 10 Image memory 11 Memory block 12 Memory block 13 Memory block 14 Memory block

Claims (2)

[Claims] An image memory for storing input digital image data, and an image input / output device for writing and reading image data to and from the image memory, wherein the image data read from the image memory is processed by a processor. In an image processing simulator that performs image processing operations and stores the image data again in the image memory and outputs the image data after the image processing, the image memory is divided into four memory blocks corresponding to the signal components of the image memory, and the image data Each signal component is accessed simultaneously to four memory blocks one by one to input / output the pixels of each signal component in parallel addressing. An image input / output unit that can switch between two types of operation of the serial address method that inputs and outputs for each pixel is provided, and image processing simulation When using the data memory, any one of the address methods can be selected, and each memory block of the image memory is further divided into a plurality of small blocks. An image processing simulator, wherein a management table for storing information is provided in correspondence with each small block, and a memory area used by a user is allocated in small block units according to the management table. 2. The image processing simulator according to claim 1, wherein at least a user entry flag bit, a user name, a use start block number of the image memory, a use block number, and an image method are written in a management table.