JPH10190467A - A/d converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform accurate digital demodulation by providing a presettable up-down counter and a PLL circuit for generating the sampling clocks of a demodulator acting at each cycle of PWM(pulse width modulation) input signals as signals for which an original PWM input frequency is multiplied by N. SOLUTION: This A/D converter is provided with a processing circuit for frequency dividing original PWM input signals to M and generating preloading signals to the up-down counter and output latch signals respectively from the rising and falling edges of the PWM input signals. The PWM input signals are inputted to the up-down counter, a preloading function is used and counting is started from an appropriate preset value. Thus, even in the case that the time of one cycle of the original PWM input signals itself fluctuates, the number of signals to be generated to the fluctuating one cycle of the PWM input signals is not changed. Thus, conversion more accurate than before is made possible.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an A / D (analog-digital) for digitally demodulating a PWM input signal.
It concerns a converter.

[0002]

2. Description of the Related Art Conventionally, an A / D converter which detects rising and falling edges of a signal every period of a PWM input signal, counts a sampling clock pulse with a fixed clock by an up / down counter, and performs digital demodulation. It has been known. The PWM input signal has a significant ratio between the period of one cycle itself (T0) and the period of the signal in one cycle (T1).
Is calculated.

By the way, if the period of one cycle of the PWM input signal is counted assuming that the period of one cycle of the PWM input signal does not fluctuate, if the period of one cycle of the PWM input signal itself fluctuates and becomes shorter, The period of the signal in one cycle is counted less than the actual period. On the other hand, if the period of one cycle itself becomes longer, an extra signal is counted.

That is, if there is a change in the period of one cycle of the PWM input signal itself, it cannot be determined whether the change is a jitter (frequency change) or a change in the PWM input signal itself, and accurate digital demodulation cannot be expected. There was a problem.

[0005]

SUMMARY OF THE INVENTION Therefore, the present invention
It is an object of the present invention to provide an AD converter that can expect more accurate digital demodulation than before even if the period of one cycle of the PWM input signal itself changes.

[0006]

In order to solve the above-mentioned problems, the present invention employs the following technical means.

An A / D converter according to the present invention includes a preset up / down counter and a PWM (Pulse Width).
Modulation) A pulse counter type demodulator, which is composed of circuit elements of a signal processing circuit for detecting the rise and fall of the input signal, and operates every one cycle of the PWM input signal, and converts the sampling clock of the demodulator into the original signal. PWM
PLL (P) generated as a signal obtained by multiplying the input frequency by N
hase Lock Loop) circuit.

According to the A / D converter, the PLL circuit generates the sampling clock of the demodulator as a signal obtained by multiplying the original PWM input frequency by N.
Even if the time itself of one cycle of the original PWM input signal fluctuates, the number of signals generated for one fluctuated cycle of the PWM input signal does not change.

Therefore, it is possible to provide an A / D converter that can expect more accurate conversion than before even if the time itself of one cycle of the original PWM input signal varies.

When the original PWM input signal has a characteristic that slightly changes in the vicinity of a certain duty value, it is necessary to subtract a useless output bit as an offset by a subtraction circuit.

Therefore, the original PWM input signal is divided by M,
From the rising and falling edges of the PWM input signal,
Each has a processing circuit for generating a preload signal to the up / down counter and an output latch signal, inputs a PWM input signal to the up / down counter, and starts counting from an appropriate preset value using the preload function. You can also

When the counting is started from an appropriate preset value using the preload function, the same function can be achieved without adding an extra signal processing block such as an accumulator and a subtraction circuit. .

[0013]

Embodiments of the present invention will be described below with reference to the drawings.

As shown in FIG. 1, AD of this embodiment
The converter is composed of circuit elements such as a presettable up / down counter and a signal processing circuit for detecting the rise and fall of a PWM (Pulse Width Modulation) input signal, and a pulse which operates every one cycle of the PWM input signal. It has a counter type demodulator and a PLL (Phase Lock Loop) circuit that generates a sampling clock of the demodulator as a signal obtained by multiplying the original PWM input frequency by N.

Also, the original PWM input signal is divided by M,
It has a processing circuit that generates a preload signal to the up / down counter and an output latch signal from the rising and falling edges of the WM input signal, respectively, and inputs the PWM input signal to the up / down counter and uses the preload function. Thus, counting is started from an appropriate preset value.

Next, the use state of the AD converter of this embodiment will be described. According to this A / D converter, the sampling clock of the demodulator is generated by the PLL circuit as a signal obtained by multiplying the original PWM input frequency by N, so that even if the time itself of one cycle of the original PWM input signal fluctuates. , The number of signals generated for one fluctuated period of the PWM input signal remains unchanged.

Therefore, even if the time itself of one cycle of the original PWM input signal fluctuates, there is an advantage that a more accurate conversion can be expected as compared with the related art.

Further, since the counting is started from an appropriate preset value using the preload function,
There is an advantage that a similar function can be achieved without adding an extra signal processing block such as an accumulator and a subtraction circuit.

The operation of this circuit will be described more specifically with reference to FIGS. FIG. 2 shows an example of the circuit of the AD converter according to this embodiment, in which one period corresponding to 16 cycles of the PWM input signal is counted.

One of the original PWM input signals [A] (shown by A surrounded by a circle in the drawing. The same applies to signals B, C, D, E, and F) is input to the PLL circuit block. .
The PLL circuit block converts the original PWM input signal [A] to 2
A clock signal [B] multiplied by 56 is generated (see also FIG. 3).

The other of the PWM input signal [A] is 74163
, And is divided by 16 into a signal [C] (see also FIG. 4).

The rising edge of one of the signals [C] is detected by the differentiating circuit (signal [D]), and is input to the preload terminal of the accumulator / integrator constituted by the up / down counter 74169.

The other of the signal [C] is used as a sampling signal of the output of the accumulator and is output to the final output stage latch 745.
74 is input to the clock terminal.

Next, the operation of the accumulator will be described in detail. Up / down counter 74 according to signal [D]
In 169, a set value of the input terminal (for example, 2,048) is set, and a count operation starting from this value is started.
This counting operation continues until the next signal [D] is input.

The original PWM input signal [A] is 74169
Is counted up while the input signal [A] is "High", and counts down while the input signal [A] is "Low".

According to this circuit, the original PWM input signal [A] has a clock time length of 256 times, so that one sampling time interval is 256 × 16 =
4,096 clock times. The counter is 2,048
, The value of the final output [F] is the minimum value 0.
To a maximum value of 4,095.

That is, an 8-bit (= 256 steps) output is raised to 12-bit accuracy by using a 16-frequency divider circuit.

[0028]

The present invention is configured as described above and has the following effects.

Even if the time itself of one cycle of the original PWM input signal fluctuates, the number of signals generated for one fluctuated cycle of the PWM input signal does not change, so that more accurate conversion can be expected than in the prior art. A -D converter can be provided.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating an embodiment of an AD converter according to the present invention.

FIG. 2 is a circuit diagram illustrating an example of the AD converter in FIG. 1;

FIG. 3 is a view for explaining the operation of the AD converter in FIG. 2;

FIG. 4 is a view for explaining the operation of the AD converter in FIG. 2;

FIG. 5 is a diagram for explaining the operation of the AD converter in FIG. 2;

[Explanation of symbols]

 A PWM input signal

Claims (2)

[Claims] 1. A pulse counter type demodulator comprising a circuit element including a presettable up / down counter and a signal processing circuit for detecting rising and falling of a PWM input signal, and operating for each period of the PWM input signal. The sampling clock of the demodulator and the demodulator is converted to the original PWM
An A / D converter comprising: a PLL circuit that generates an input frequency multiplied by N. 2. An original PWM input signal is frequency-divided by M,
It has a processing circuit that generates a preload signal to the up / down counter and an output latch signal from the rising and falling edges of the input signal, respectively, and inputs the PWM input signal to the up / down counter and uses the preload function. The A / D converter according to claim 1, wherein counting is started from an appropriate preset value.