JPH10190187A - Structure of mounting optical device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To ensure accurate alignment of a LD chip and enhance connecting strength. SOLUTION: In the structure of mounting an optical device, an LD chip 11 is accurately positioned and mounted on a Si substrate 12. The structure involves a cross-shaped electrode 18 with which the LD chip 11 formed on the top of the Si substrate 12 is brought into contact and which thereby provides electrical connection and accurately positions the LD chip 11 in the direction of height; a quadrangular pyramid which is formed on the top of the Si substrate 12 and has solder 14 filled therein, the upper part of the solder 14 is brought into contact with the electrodes on the Si substrate 12 side, and the Si substrate 12 and the LD chip 11 are thereby electrically connected with each other through the solder 14; a surplus solder letting-out rail 19b which is connected to the quadrangular pyramid and receives surplus solder 14 sticking out of the quadrangular pyramid; and an infrared positioning means which aligns the LD chip 11 with the Si substrate 12 in the forward/backward and left/right directions.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an optical device mounting structure for mounting an optical device on a substrate, for example, an optical transmitter having an electric signal / optical signal conversion function used in an optical data transmission device, and It is possible to accurately mount a transmitting element such as an LD chip and a receiving element such as a PD chip on an Si substrate in an optical transceiver module or the like in which an optical receiver having an optical signal / electrical signal conversion function is integrally or separately formed. The present invention relates to an optical element mounting structure that can be used.

[0002]

[Prior art]

Document name: 1995 IEICE Electronics Society Conference SC-1-12 PP.331-332 Generally, an optical element such as an LD chip is mounted as follows. 2 is a perspective view showing a state where the LD chip is mounted on a Si substrate, FIG. 3 is a sectional view taken along line AA of FIG. 2, FIG. 4 is a plan view showing the Si substrate, and FIG. FIG. 6 and FIG. 6 are schematic views showing recognition marks provided on the Si substrate and the LD chip, respectively.

In FIG. 1, reference numeral 1 denotes an LD chip, and 2 denotes an Si substrate. On the upper surface of the Si substrate 2, a V groove 3 for positioning,
A solder 4 for fixing the LD chip 1 to the Si substrate 2 in an energized state; a Si substrate side recognition mark 5a for positioning when the LD chip 1 is mounted on the upper surface of the Si substrate 2;
An i-substrate-side electrode pattern 6a is provided.

On the lower surface of the LD chip 1, in conjunction with the Si substrate side recognition mark 5 a provided on the Si substrate 2,
LD chip side recognition mark 5 for positioning D chip 1
b and L joined to the Si substrate-side electrode pattern 6a.
D chip side electrode patterns 6b are provided.

The mounting of the LD chip 1 on the Si substrate 2 is performed by a visual method. That is, with respect to the Si substrate side recognition mark 5a, the LD chip side recognition mark 5b is detected by infrared rays, and the position is adjusted. As a result, the LD chip 1 is mounted on the Si substrate 2 in an accurate position, and the Si substrate-side electrode pattern 6a provided on the Si substrate 2 and the LD chip-side electrode pattern 6b provided on the LD chip mounting surface. Are connected by solder 4.

[0006]

However, the mounting structure of the optical element having the above configuration has the following problems.

(1) Si substrate side electrode pattern 6a and L
If the thickness of the solder 4 provided between the D-chip-side electrode pattern 6b is too large, accurate alignment becomes difficult. That is, it is difficult to accurately position the LD chip 1 in the height direction (Y-axis direction in FIG. 2).

(2) If the solder 4 is too thin, the positioning accuracy of the LD chip 1 in the height direction is improved, but the connection strength between the LD chip 1 and the Si substrate 2 is weakened.

[0009]

According to the present invention, there is provided an optical element mounting structure for accurately positioning an optical element on a substrate and mounting the optical element on an upper surface of the substrate. An electrode that is electrically connected to the optical element by contacting the element and performs accurate positioning in the height direction of the optical element, and is provided on the upper surface of the substrate and filled with solder, and The upper portion of the solder is bonded to the electrode on the optical element side, so that the substrate side and the optical element side are electrically connected via the solder, and the solder pool provided continuously to the solder pool An excess solder protruding portion for receiving the protruding excess solder, and infrared positioning means for positioning the optical element in the front-rear and left-right directions with respect to the substrate.

With the above arrangement, the optical element contacts the electrode on the upper surface of the substrate while the position in the front-rear, left-right direction with respect to the substrate is accurately controlled by the infrared positioning means. Thereby, while the substrate and the optical element are electrically connected,
Accurate positioning in the front, rear, left, right, and height directions of the optical element is performed. In this state, a sufficient amount of solder filled in the solder pool is securely adhered to the electrodes on the optical element side, and the electrical connection between them is made, and the optical element is securely connected to the substrate side. Fixed. At this time, the solder may overflow from the solder pool, but the excess solder flows out to the excess solder protruding portion to suppress the influence on other portions.

[0011]

An embodiment of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 is a side sectional view showing a mounting structure of an LD chip according to this embodiment, FIG. 7 is a plan view showing an Si substrate, and FIG. FIG. 9 is a schematic diagram showing a state in which the LD chip is mounted on a Si substrate. In addition,
Also in the present embodiment, an LD chip is used as an optical element and a Si substrate is used as a substrate, as in the above-described conventional technology.

[Structure] Based on FIG. 1, FIG. 7 and FIG.
The mounting structure of the D chip will be described.

In the figure, reference numeral 11 denotes an LD chip, and reference numeral 12 denotes a Si substrate. On the lower surface of the LD chip 11, an LD chip-side recognition mark 15b and an LD chip-side electrode pattern 16b are provided. The LD chip side electrode pattern 16b is L
On the lower surface of the D chip 11, it is provided at each of four locations near four corners corresponding to a solder receiver 19 described later.
The LD chip-side recognition mark 15b is provided at one edge of the lower surface of the LD chip 11 and at an intermediate position between two adjacent LD chip-side electrode patterns 16b. The LD chip-side recognition mark 15b is formed in a cross shape.

On the upper surface of the Si substrate 12, a solder receiver 1 is provided.
9 are formed. The four solder receivers 19 are provided at positions corresponding to the LD chip-side electrode patterns 16b provided at four locations. The solder 14 for flip chip mounting the LD chip 11 is filled in the solder receiver 19.

The solder receiver 19 is formed by engraved square pyramid 1.
9a and an excess solder protruding rail 19b. The inner surfaces of the quadrangular pyramid 19a and the surplus solder protruding rail 19b are metallized to form a Si substrate side electrode panel 16a. Square pyramid 19a
Is to store the solder 14 directly, and the upper portion of the solder 14 is adhered to the LD chip-side electrode pattern 16b on the LD chip 11 side, so that each electrode pattern 1
The solder pools 6a and 16b are electrically connected. The quadrangular pyramid 19a is filled with a sufficient amount of solder 14, and the solder 14 and each electrode pattern 16a, 16
b and the LD chip 11 are bonded over a wide area to
2 can be securely fixed. The surplus solder protruding rail 19b is formed continuously with the quadrangular pyramid 19a, and the surplus solder 1 overflowing and protruding from the quadrangular pyramid 19a.
4 is an excess solder protruding portion for receiving 4.

The upper surface of the Si substrate 12 is
Cross electrodes 18 are formed so as to sew between two solder receivers 19. The cross electrode 18 is used for the LD chip 11
Is an electrode that the lower surface (bottom portion) of the electrode contacts directly (in a contact state). The cross electrode 18 is electrically connected to the LD chip 11 by being in contact with the LD chip 11, and performs accurate positioning of the LD chip 11 in the height direction (Y-axis direction in FIG. 1). Electrodes. That is, by mounting the LD chip 11 on the upper surface of the cross electrode 18 by flip chip mounting in a state where the LD chip 11 is placed in direct contact with the upper surface, positioning of the LD chip 11 in the height direction is performed. I have. Therefore, the height of the cross electrode 18 is accurately formed.

Further, on the upper surface of the Si substrate 12, an LD
In a state where the chip 11 is flip-chip mounted, Si substrate side recognition marks 15a are formed at positions corresponding to the cross-shaped LD chip side recognition marks 15b. This S
The i-substrate-side recognition mark 15a is formed in a square shape with a central portion cut out in a cross shape. The cross-shaped notch of the Si substrate-side recognition mark 15a is aligned with the cross-shaped LD chip-side recognition mark 15b by detection and positioning using infrared rays. The alignment of the Si substrate side recognition mark 15a and the LD chip side recognition mark 15b allows the LD chip 11 to be accurately positioned in the front-rear and left-right directions (XZ-axis direction) and the rotation direction about the Y-axis. . Reference numeral 17 denotes an oxide film formed on the upper surface of the Si substrate 12. Further, below the Si substrate 12, an infrared positioning means (not shown) for positioning the LD chip 11 with respect to the Si substrate 12 is provided. The infrared positioning means detects the relative positions of the Si substrate side recognition mark 15a and the LD chip side recognition mark 15b by infrared rays passing from the lower part to the upper part of the Si substrate 12 and aligns them with each other. , The rotation direction of the LD chip 11 in the front-rear and left-right directions and the rotation direction about the Y axis is accurately positioned.

[Manufacturing Method] Next, a method for mounting an optical element will be described with reference to FIGS. 9A to 9F.

FIG. 9A An oxide film 17 is formed on the upper surface of the Si substrate 12. Specifically, the pyramid 19a of the solder receiver 19 formed later
And the surplus solder is formed in a negative shape excluding the shape corresponding to the protruding rail 19b.

FIG. 9B The upper surface of the Si substrate 12 is subjected to alkali etching.
Using the oxide film 17 as a mask, alkali etching proceeds. Thus, the quadrangular pyramid 19a and the surplus solder protruding rail 19b are formed in the upper surface of the Si substrate 12 in a carved shape.

FIG. 9C A cross electrode 18 is formed on the oxide film 17 serving as a mask. At the same time, metallization is applied to the inside of the quadrangular pyramid 19a and the surplus solder protruding rail 19b to form the Si substrate side electrode pattern 16a. A specific forming method is based on a normal thin film forming technique (photolithography, vapor deposition, or the like). Cross electrode 18 and Si substrate side electrode pattern 16a
The metallized layer configuration is made of Ti-Pt-Au and has a thickness of 1
μm.

FIG. 9 (D) Above Si substrate side electrode pattern 16a (within square pyramid 19a)
Is supplied with solder 14. This solder 14 is made of Au /
It is formed into a ball shape using Sn solder. The ball diameter of each solder 14 supplied into the four quadrangular pyramids 19a (φA,
φB) is set to about 100 to 150 μm. The diameter of the ball does not need to be set strictly. Supply more. Excess solder 14 is the excess solder protrusion rail 1
Release to 9b.

FIG. 9E The collet 21 holds the LD chip 11 and mounts it on the upper surface of the Si substrate 12. At this time, the infrared rays are transmitted from the lower surface of the Si substrate 12 toward the upper surface by the infrared positioning means. With this infrared ray, the Si substrate side recognition mark 15a and the LD chip side recognition mark 15b are detected, and the positioning is adjusted by the collet 21. Thereby, as shown in FIG. 8, they are aligned with each other.

FIG. 9 (F) The LD chip 1 is formed by the infrared positioning means and the collet 21.
1 and the Si substrate 12 are flip-chip mounted in a state where they are aligned with each other. At this time, the solder 14
The adhesive is bonded to the LD chip-side electrode pattern 16b of the D chip 11 and spreads in the quadrangular pyramid 19a of the solder receiver 19 to be bonded to the Si substrate-side electrode pattern 16a. The solder 14 electrically connects the Si substrate-side electrode pattern 16a and the LD chip-side electrode pattern 16b, and adheres the LD chip 11 and the Si substrate 12 over a wide area.
Are firmly connected to each other. The surplus solder 14 overflowing from the square pyramid 19a and flowing into the surplus solder protruding rail 19b suppresses the influence on other parts.

At this time, the LD chip 11 is
1 while being supported by the molten solder 14
, And the lower surface of the LD chip 11 contacts the upper surface of the cross electrode 18. That is, a contact state is established. Thereby, the LD chip 11 moves in the Y-axis direction.
Positioned accurately at a certain height. This LD chip 1
1 and the cross electrode 18 may be bonded by thermocompression bonding because the uppermost layer of the cross electrode 18 is Au.
Au / Sn thin film solder or the like may be formed on the uppermost layer and bonded.

[Effect] As described above, the position of the LD chip 11 in the height direction (Y-axis direction) is determined by the contact between the lower surface of the LD chip 11 and the upper surface of the cross electrode 18, and the thickness of the solder 14 Has no effect, so Y
LD chips can be connected with high precision in the axial direction.

Further, since a sufficient amount of the solder 14 is used for connecting the LD chip 11 and the Si substrate 12, the connection strength (shear strength) can be greatly improved (to 100 g or more).

Further, since the excess solder extruding rail 19b for receiving the excess solder that overflows from the engraved quadrangular pyramid 19a of the solder receiver 19 is provided, it is not necessary to strictly control the amount of solder used. And the efficiency of the mounting work of the optical element is greatly improved.

[Modification] In the above embodiment, the electrode 18 is formed in a cross shape, but may be formed in another shape. That is, since the shape of the electrode varies depending on the type of the LD chip 11,
The height from the Si substrate 12 is accurately formed for each shape of the electrode. Thereby, the same operation and effect as the above embodiment can be obtained.

In the above embodiment, the solder 14 is formed in a ball shape as the method of supplying the solder 14. However, the solder 14 may be supplied by screen printing or the like.

Further, a solder receiver 1 for storing the solder 14
9 is not limited to a quadrangular pyramid and a rail, but may have another shape, as long as it can store a certain amount of the solder 14 and have a portion for allowing the excess solder 14 to escape.

[0033]

As described above, according to the present invention, the following effects can be obtained.

(1) Since an electrode is provided which is electrically connected to the optical element when the optical element is brought into contact with the optical element and which performs accurate positioning in the height direction of the optical element, the optical element is located in front of and behind the substrate. In a state where the position in the left-right direction is accurately controlled by the infrared positioning means, it becomes possible to accurately position the optical element with respect to the substrate in the front-rear, left-right, and height directions by contacting the electrodes.

(2) A sufficient amount of solder is stored in the solder pool, and the excess is received at the excess solder protrusion, so that a sufficient amount of solder can be used for connection between the optical element and the substrate. Thus, the connection strength between the optical element and the substrate can be greatly improved.

(3) Since the excess solder protruding portion for receiving the surplus solder overflowing and overflowing from the solder pool is provided, it is not necessary to strictly control the amount of solder to be used. The efficiency of device mounting work is greatly improved.

[Brief description of the drawings]

FIG. 1 is a side sectional view showing a mounting structure of an LD chip according to the present invention.

FIG. 2 is a perspective view showing a state in which a conventional LD chip is mounted on a Si substrate.

FIG. 3 is a sectional view taken along line AA of FIG. 2;

FIG. 4 is a plan view showing a conventional Si substrate.

FIG. 5 is a bottom view showing a mounting surface of a conventional LD chip.

FIG. 6 is a schematic diagram showing recognition marks provided on a conventional Si substrate and an LD chip, respectively.

FIG. 7 is a plan view showing a Si substrate according to the present invention.

FIG. 8 is a schematic diagram showing a state where the Si substrate side recognition mark and the LD chip side recognition mark according to the present invention are aligned.

FIG. 9 is a process diagram showing a process of mounting an LD chip on a Si substrate.

[Description of References] 11: LD chip, 12: Si substrate, 14: Solder, 1
5a: Recognition mark on Si substrate side, 15b: Recognition mark on LD chip side, 16a: Electrode pattern on Si substrate side, 16b:
LD chip side electrode pattern, 18: cross electrode, 19: solder receiver, 19a: square pyramid, 19b: surplus solder protruding rail.

Claims (1)

[Claims] An optical element mounting structure for accurately positioning and mounting an optical element on a substrate, wherein the optical element is provided on an upper surface of the substrate and is electrically connected to the optical element when the optical element contacts the optical element. And an electrode for accurately positioning the optical device in the height direction, and an upper surface of the substrate, which is filled with solder and the upper portion of the solder is bonded to the electrode on the optical device side. A solder pool in which the substrate side and the optical element side are electrically connected via the solder, a surplus solder protruding portion provided continuously to the solder pool and receiving surplus solder protruding from the solder pool; And an infrared positioning means for positioning the optical element in the front-rear and left-right directions with respect to the optical element.