JPH10190041A - Photodiode - Google Patents

Abstract

PROBLEM TO BE SOLVED: To attain high sensitivity and high withstand voltage by a method wherein a filed dope layer is provided between a guard ring layer and a channel stopper layer, and further a spacing portion is provided between the field doper layer and the guard ring layer. SOLUTION: An n type impurity is heavily doped in a light-receiving area in a surface layer of a p type epitaxial layer 2, and an n<+> type layer 3 is formed as a light-receiving layer. An n type impurity is doped at low concentration in a peripheral part of the light-receiving area in a surface layer of the p type epitaxial layer 2, and an n type guard ring layer 4 connecting with a marginal part of the n<+> type layer 3 is formed. Outside the n type guard ring layer 4 in a surface layer of the p type epitaxial layer 2, a p type field dope layer 5 in which a lightly doped p type impurity is formed at a spacing S relative to the n type guard ring layer 4. Further outside the p type field dope layer 5 in a surface layer of the p type epitaxial layer 2, a p<+> type channel stoper layer 6 in which a p type impurity is heavily doped than the p type field dope layer 5 is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a photodiode used as a light receiving element, and more particularly, to a photodiode having a low concentration between a p-type region serving as an anode and an n-type region serving as a cathode. Alternatively, the present invention relates to a photodiode having a PIN structure in which an i-type photocarrier generation region is interposed.

[0002]

2. Description of the Related Art Avalanche photodiodes (hereinafter "A")
PD ”) has attracted attention as a high-sensitivity light-receiving element because electron-hole pairs generated by incident light can be multiplied by the avalanche effect. An APD having a PIN structure (PIN-APD) can efficiently absorb incident light because the photocarrier generation region is thick, so that higher sensitivity can be realized.

FIG. 2 is a sectional view of a conventional PIN-APD. As shown in the figure, ap ⁻ -type epitaxial layer 2 is grown on a p ⁺ -type substrate 1, and an n ⁺ -type layer 3 is formed in a light-receiving region on the surface of the p ⁺ -type substrate 1. ), The p ⁻ type epitaxial layer 2 is an I region (photocarrier generation region), and the n ⁺ type layer 3 is an N region (cathode region).
Is formed.

An n-type guard ring layer 4 is formed around the n ⁺ -type layer 3 so as to connect the electric field to the P-type layer.
Since the p ⁺ -type channel stopper layer 6 is formed so as to surround the N-junction so as to surround the N-junction, another element (not shown) formed on the same substrate (other APD or Transistor for signal amplification) and APD
Can be separated.

According to this structure, not only can the n ⁺ -type layer 3 and the cathode electrode 8 be connected through the opening formed in the SiO ₂ film 7 on the surface, but also the SiO ₂ film 7
Through the opening formed in the p ⁺ -type channel stopper layer 6
And the anode electrode 9 can be connected. For this reason,
p ⁺ -type substrate directly to 1 (for example the rear surface of the p ⁺ -type substrate 1) without providing the anode electrode, p sandwiched by only the wiring on the surface of the element to the p ⁺ -type substrate 1 and the n ⁺ -type layer 3 ^A depletion layer is formed in the negative type epitaxial layer 2 and can function as a photocarrier generation region.

[0006]

However, in the prior art of the planar structure, if the APD is to be made highly sensitive, the PN junction breakdown voltage between the n-type guard ring layer 4 and the p ⁺ -type channel stopper layer 6 is reduced. Therefore, it is difficult to apply a sufficient bias voltage for avalanche multiplication, and it is not easy to realize high sensitivity.

That is, in order to increase the sensitivity, it is only necessary to increase the absorption of incident light in the photocarrier generation region. For this purpose, the photocarrier generation region is increased, that is, p
^The thickness of the p ^- type epitaxial layer 2 may be increased. For this purpose, the impurity concentration of the p ^- type epitaxial layer 2 must be sufficiently reduced. This is because the reverse bias for depleting the p ⁻ type epitaxial layer 2 from the interface with the n ⁺ type layer 3 to the p ⁺ type substrate 1 is proportional to the impurity concentration of the p ⁻ type epitaxial layer 2. .

Therefore, if the concentration of the p ⁻ -type epitaxial layer 2 is made sufficiently low, the surface layer of the p ⁻ -type epitaxial layer 2 between the n-type guard ring layer 4 and the p ⁺ -type channel stopper layer 6 has an easy polarity. To n-type. This polarity inversion is caused by the surface level of the semiconductor or the electric field from the wiring 10 on the SiO ₂ film 7.
Since a high voltage is applied between the anode and the anode electrode 9, the influence of the electric field from the wiring 10 is greater and the polarity is easily inverted.

When the polarity inversion occurs, a PN junction appears between the n-type inversion portion 11 on the surface of the p ^-- type epitaxial layer 2 and the p ⁺ -type channel stopper layer 6, but the p ⁺ -type channel stopper layer 6 has a high concentration. Therefore, the electric field is concentrated, and the breakdown voltage is reduced here. Therefore, a sufficient reverse bias voltage for avalanche multiplication cannot be applied.

[0010] Eventually, in an APD of the type shown in FIG. 2, that is, a photodiode having a PIN structure such as a PIN-APD having a low-concentration p-type, n-type or i-type layer as a photocarrier generation region, high sensitivity is obtained. And achieving a high breakdown voltage at the same time have a trade-off relationship with each other.

An object of the present invention is to provide a photodiode capable of simultaneously achieving high sensitivity and high withstand voltage.

[0012]

A photodiode according to the present invention comprises a semiconductor substrate doped with a first conductivity type impurity at a high concentration and a semiconductor substrate formed on the semiconductor substrate and doped with a first conductivity type impurity at a low concentration. The epitaxial layer thus formed, a light-receiving layer of the second conductivity type formed in the light-receiving region on the surface of the epitaxial layer and doped with the impurity of the second conductivity type at a high concentration, and an epitaxial layer around the light-receiving layer, Formed deeper than the layer and the inner circumference is connected to the light receiving layer,
A second conductivity type guard ring layer doped with a second conductivity type impurity at a low concentration; and an epitaxial layer surrounding the guard ring layer formed at a distance from the guard ring layer so that the first conductivity type impurity has a high concentration. A channel stopper layer doped with an impurity is formed in the epitaxial layer around the guard ring layer so as to be spaced apart from the guard ring layer and to have an outer periphery connected to the channel stopper layer. A field doped layer doped at a lower concentration than the layer and at a higher concentration than the epitaxial layer, wherein the epitaxial layer sandwiched between the light receiving layer and the semiconductor substrate is a photocarrier generation region.

According to the present invention, the space between the lightly doped guard ring layer of the second conductivity type and the lightly doped field dope layer of the first conductivity type is provided in the space between the guard ring layer and the first conductivity type. Since the type epitaxial layer is interposed, the pn junction breakdown voltage in this portion does not decrease regardless of whether or not the polarity of the epitaxial layer in this interval portion is inverted.

That is, when the polarity is not inverted, a pn junction is formed between the low-doped guard ring layer and the sufficiently lightly-doped space, and when the polarity is inverted, the lightly-doped field-doped layer and the inverted layer are formed. Since a pn junction is formed between them, the electric field concentration at the junction is reduced in any case, and the high breakdown voltage of the photodiode is maintained.

Therefore, the operating voltage of the APD can be set high, and the epitaxial layer can be sufficiently lightly doped to such an extent that the polarity inversion is easily caused by the surface state or the wiring on the surface. The first conductivity type epitaxial layer in the region between the conductivity type semiconductor substrate and the second conductivity type light receiving layer can be sufficiently depleted. Therefore, the photocarrier generation area is enlarged, and the absorption efficiency of incident light is increased. In addition, since the epitaxial layer can be sufficiently low-doped as described above, a high electric field concentrates near the interface of the light-receiving layer of the second conductivity type in contact with the epitaxial layer of the first conductivity type. Avalanche multiplication effect increases.

Therefore, according to the present invention, a photodiode having a PIN structure (for example, PINN-APD) can simultaneously achieve high withstand voltage and high sensitivity.

In the APD according to the present invention, the first conductivity type is p-type, the second conductivity type is n-type, and the APD is connected to the cathode electrode connected to the light receiving layer and the channel stopper layer. And an anode electrode.

With this configuration, of the electron-hole pairs generated in the photocarrier generation region, electrons are transferred between the n-type light-receiving layer and the p-type light-receiving layer.
Induced in the interface direction of the epitaxial layer, the AP
When used as D, electrons are avalanche multiplied by a high electric field, and high detection sensitivity is realized.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a PIN-A according to an embodiment will be described.
The PD will be described in detail. In the drawings, the same elements are denoted by the same reference numerals.

As shown in FIG. 1, a p ⁺ -type substrate 1 made of Si single crystal doped with a p-type impurity such as boron at a high concentration is provided on a p ⁺ -type impurity similarly doped with a p-type impurity at a sufficiently low concentration.
A p ⁻ type epitaxial layer 2 made of a single crystal is formed. Here, the p ⁺ type substrate 1 has a specific resistance of 0.01 to 0.1.
The p ⁻ -type epitaxial layer 2 has an impurity concentration of about 5 × 10 ¹⁴ to 5 × 10 ¹⁵ cm ⁻³ (resistivity of ³ to 20 Ω · cm) and a thickness of about ³ to 30 μm. .

An n-type impurity such as arsenic is heavily doped in the light-receiving region on the surface of the p ^-- type epitaxial layer 2, and an n ⁺ -type layer 3 as a light-receiving layer is formed by, for example, a diffusion method. The impurity concentration of the n ⁺ type layer 3 is 3 × 10 ¹⁸ to 3 × 1
It is about 0 ²¹ cm ⁻³ and the depth is about 0.2 to 1.0 μm.

The periphery of the light receiving region on the surface of the p ⁻ -type epitaxial layer 2 is doped with an n-type impurity at a low concentration.
An n-type guard ring layer 4 connected to the periphery of the ⁺ -type layer 3 is formed. The impurity concentration of the n-type guard ring layer 4 is ^{5 × 10 15 ~ 5 × 10} 1 about ⁸ cm ^-3 at the surface, the depth is about 1.0 to 5.0 [mu] m. As described above, by forming the n-type guard ring layer 4 deep, the radius of curvature of the cross section of the n-type guard ring layer 4 can be increased, and the p ^- type epitaxial layer 2 and p ^- type
Since the n-junction can be a graded junction instead of a step junction, the breakdown voltage in the outer portion of the n-type guard ring layer 4 can be improved.

Outside the n-type guard ring layer 4 on the surface of the p ⁻ -type epitaxial layer 2, the n-type guard ring layers 4 and 1
A p-type field doped layer 5 doped with a p-type impurity such as boron at a low concentration is formed at intervals of about μm or more. The impurity concentration of the p-type field doped layer 5 is about 3 × 10 ¹⁵ to 1 × 10 ¹⁷ cm ^{−3 on the} surface, and the depth is about 0.5 to 2.0 μm. The p-type field doped layer 5 having a higher concentration than the p ⁻ -type epitaxial layer 2 was provided. In particular, the p-type field doped layer 5 was provided with a predetermined interval S between the p ^- type epitaxial layer 2 and the n-type guard ring layer 4. The present embodiment is characterized in that the p ⁻ -type epitaxial layer 2 is sufficiently low-doped and the withstand voltage can be improved.

A p ⁺ -type channel stopper doped with a p-type impurity such as boron at a higher concentration than the p-type field dope layer 5 is further outside the p-type field dope layer 5 on the surface of the p ⁻ -type epitaxial layer 2. Layer 6 is formed. The impurity concentration of the p ⁺ type channel stopper layer 6 is 3 × 1
0 ^{15 to} 3 × 10 ²⁰ cm ^-3 and a depth of 0.2 to
It is about 1.0 μm. When an APD is integrated with a transistor or the like to manufacture an IC chip, the above-described concentration and depth are preferable.

An SiO ₂ film 7 is laminated on the upper surface of the p ⁻ -type epitaxial layer 2 in which the respective regions are formed as described above, and functions as an antireflection film for incident light on the upper surface of the n ⁺ -type layer 3. I do. SiO ₂ film 7 on the periphery of n ⁺ type layer 3
, A contact hole is formed, and the cathode electrode 8 is ohmic-connected to the contact hole. Further, a contact hole is also formed in the SiO ₂ film 7 on the p ⁺ type channel stopper layer 6, and the anode electrode 9 is ohmically connected thereto. The electrodes 8 and 9 are connected to another circuit element (not shown) such as a transistor on the same substrate by a wiring 10 on the SiO ₂ film 7.

Further, a protective film (not shown) such as PSG is formed on the SiO ₂ film 7 and the wiring 10, and a region other than the n ⁺ type layer 3 (light receiving region) is made of aluminum or the like. A light-shielding film (not shown) is formed, and the incident light selectively enters only the light receiving region.

Next, the operation of the PIN-APD shown in FIG. 1 will be described.

First, when a reverse bias voltage is applied to the cathode electrode 8 and the anode electrode 9, the n ⁺ -type layer 3 and the n-type guard ring layer 4 have the same positive potential, and the p ⁺ -type channel stopper layer 6 The p-type field doped layer 5 has the same negative potential and the p ⁺ -type substrate 1 has the same potential as the p ⁺ -type channel stopper layer 6 via the p ^-- type epitaxial layer 2.

Therefore, the p ⁻ -type epitaxial layer 2 sandwiched between the p ⁺ -type substrate 1 and the n ⁺ -type layer 3 and surrounded by the n-type guard ring layer 4 is depleted, and a photocarrier generation region is formed. At the same time, the p ⁻ -type epitaxial layer 2 between the n-type guard ring layer 4 and the p-type field dope layer 5 is also depleted. However, since the incident light does not reach the light-shielding film, it functions as a photocarrier generation region. There is no.

When light enters the p ⁻ -type epitaxial layer 2 from the n ⁺ -type layer 3 through the SiO ₂ film 7, electron-hole pairs are generated, and electrons are transferred to the n ⁺ -type layer 3 by the electric field of the depletion layer. , The holes drift toward the p ⁺ type substrate 1. And
When the electrons reach the interface end of the n ⁺ -type layer 3 in contact with the p ⁻ -type epitaxial layer 2, avalanche multiplication is caused by a high electric field, and the multiplied electrons are converted into signal currents by the cathode electrode 8,
It is output from 10.

Here, if the p ⁻ type epitaxial layer 2 is sufficiently lightly doped, the probability that electrons generated by light incidence are trapped in impurity levels during drift is reduced, and the detection sensitivity is improved. If the p ⁻ -type epitaxial layer 2 is sufficiently lightly doped, the internal electric field due to the applied reverse bias voltage is more concentrated at the interface end of the n ⁺ -type layer 3 with the p ⁻ -type epitaxial layer 2. Therefore, the effect of avalanche multiplication can be further enhanced. In the present embodiment, the impurity concentration of the p ⁻ -type epitaxial layer 2 is set to 5 × 10
Since it is sufficiently low to about ¹⁴ to 5 × 10 ¹⁵ cm ^−3, the improvement of the detection sensitivity and the improvement of the avalanche multiplication efficiency are simultaneously and sufficiently achieved.

On the other hand, the depletion layer caused by the reverse bias voltage is n
The p ^- type epitaxial layer 2 is also generated in the surface layer portion between the p-type guard ring layer 4 and the p-type field dope layer 5.
If the polarity of the interval portion S which is the surface layer of
Centering on the interface between the mold guard ring layer 4 and the space S,
When the polarity is reversed, the depletion layer spreads on both sides around the interface between the p-type field dope layer 5 and the interval S according to the carrier concentration. When the spacing S changes from p ⁻ type to neutral (i-type), the carrier is centered on both interfaces of the n-type guard ring layer 4 and the spacing S and the p-type field doped layer 5 and the spacing S. A depletion layer spreads on both sides according to the concentration.

In any case, the internal electric field due to the reverse bias voltage is centered on the interval S composed of the sufficiently lightly doped p ⁻ -type epitaxial layer 2 and the lightly doped n-type guard ring layer 4 or the p-type Field dope layer 5
And the depletion layer does not reach the highly doped n ⁺ -type layer 3 and p ⁺ -type channel stopper layer 6. For this reason, the electric field concentration can be reduced regardless of the presence or absence of the polarity inversion.
It is possible to increase the withstand voltage of the PIN-APD.

The PIN-APD shown in FIG. 1 is manufactured by the following process. First, p to p ⁺ -type substrate 1 ^-
A type epitaxial layer 2 is grown. Next, the n-type guard ring layer 4, p-type field doped layer 5, n-type through a resist mask by thermal diffusion, ion implantation, or ion implantation (through implantation) with the thin SiO ₂ film 7 formed on the surface. ^{The +} type layer 3 and the p ⁺ type channel stopper 6 are formed in this order. Then, a contact hole is formed in the SiO ₂ film 7, and a cathode electrode 8 and an anode electrode 9 are formed.

The present invention can be variously modified without being limited to the above embodiment.

For example, the semiconductor substrate 1 may be of the n ⁺ type, and the conductivity types of all elements such as the light receiving layer 3 and the field dope layer 5 may be reversed. However, if the conductivity type of the embodiment is used, avalanche multiplication of electrons of the photo-generated electron-hole pairs is more preferable for high-sensitivity detection.

Further, a normal PIN photodiode having no avalanche multiplication function may be used. However, AP
Since the reverse bias voltage applied to D is higher than that of a normal PIN photodiode, the effect of increasing the breakdown voltage according to the present invention is A
PD is better.

As a technique for preventing a leak current due to inversion of the surface in an APD, Japanese Patent Laid-Open No. 58-1158 discloses a technique.
No. 73 is known, but relates to a photodiode having a PN structure, and its basic structure is different from that of the present invention. Further, in order to prevent the surface from being inverted from n ⁻ type to p ⁻ type, the surface is highly doped from n ⁻ type to n type. This is different from the present invention which is left as it is. For this reason, in the technique of the above publication, the electric field is concentrated on the interface of the pn junction, and the breakdown voltage is reduced.

[0039]

According to the photodiode of the present invention, a field dope layer in contact with the channel stopper layer is provided between the guard ring layer and the channel stopper layer, and a certain interval is provided between the field dope layer and the guard ring layer. Because of the provision, the concentration of the electric field can be reduced regardless of whether the polarity of the interval portion is inverted, and the withstand voltage can be increased.

For this reason, without considering the polarity inversion,
Since the impurity concentration of the epitaxial layer can be designed, a PIN structure in which an I layer sandwiched between a P layer and an N layer has an epitaxial layer functioning as a photocarrier generation region having the highest sensitivity and the highest light absorption efficiency depending on the application. A photodiode can be realized.

In particular, a PIN-APD having a p ⁺ type substrate
In this case, there is an effect that high withstand voltage and high sensitivity can be simultaneously achieved.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a PIN-APD according to an embodiment.

FIG. 2 is a sectional view of a conventional PIN-APD.

[Explanation of symbols]

1 ... p ⁺ type substrate, 2 ... p ^- type epitaxial layer, 3 ... n ⁺
Type layer, 4 ... n-type guard ring layer, 5 ... p-type field dope layer, 6 ... p ⁺ type channel stopper layer, 7 ... SiO
₂ film, 8 ... cathode electrode, 9 ... anode electrode, 10 ... wiring, 11 ... n-type inversion part, S ... interval part.

Claims (2)

[Claims] A semiconductor substrate doped with a first conductivity type impurity at a high concentration; an epitaxial layer formed on the semiconductor substrate and doped at a low concentration with the first conductivity type impurity; A second-conductivity-type light-receiving layer formed in the surface light-receiving region and doped with a second-conductivity-type impurity at a high concentration; and the epitaxial layer around the light-receiving layer, the inner periphery of which is deeper than the light-receiving layer. A second-conductivity-type guard ring layer formed so as to be connected to the light-receiving layer and doped with the second-conductivity-type impurity at a low concentration; and the guard ring layer on the epitaxial layer around the guard ring layer. A channel stopper layer formed so as to be spaced apart from the first conductivity type impurity at a high concentration, and the epitaxial ring around the guard ring layer and the guard ring layer. A field-doped layer formed so that the outer periphery is connected to the channel stopper layer and the impurity of the first conductivity type is doped at a lower concentration than the channel stopper layer and at a higher concentration than the epitaxial layer. And wherein the epitaxial layer sandwiched between the light receiving layer and the semiconductor substrate is a photocarrier generation region. 2. The method according to claim 1, wherein the first conductivity type is p-type, the second conductivity type is n-type, and a cathode electrode connected to the light receiving layer and an anode electrode connected to the channel stopper layer. The photodiode according to claim 1, further comprising: