JPH10187437A - Device and method for allocating bits to instruction code - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce power consumption when operating an application on a real LSI in the bit allocation for the instruction code of processor. SOLUTION: Since a bit allocating part 11 performs bit allocation so as to minimize a total sum concerning the combination of all double instruction codes in the product of instruction code transition frequency provided by an instruction analytic part 10 and the number of changed bits between two instruction codes, a bit change caused by the change of instruction code is suppressed so that power consumption is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and an apparatus for reducing the power consumption at the time of executing an instruction in bit allocation of an instruction code of a microprocessor.

[0002]

2. Description of the Related Art Hitherto, in order to reduce the decoder area of a processor, bit allocation of instruction codes of a processor has been performed with the smallest possible number of bits and the number of stages.

[0003]

However, in the bit allocation of the instruction code according to the above-described conventional method, as the number of instruction bits used increases due to the complexity of the instruction set, the instruction code for executing the application program is increased. However, there is a problem that power consumption resulting from a bit change due to a change in the power consumption increases.

[0004] In view of the above problems, an object of the present invention is to reduce power consumption during execution of an application program by performing bit allocation in consideration of a bit change due to a change in an instruction code.

[0005]

In order to achieve the above object, the present invention is characterized in that bit assignment of an instruction code is performed so that a bit change due to a change in the instruction code when executing an application program is reduced. And

[0006]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a diagram showing a configuration of a bit allocation device according to this embodiment. As shown in FIG. 1, the bit allocation device according to this embodiment includes an input device 1, a display 2, a storage device 3, an editor unit 4, and a processing unit 5. The processing unit 5 further includes an instruction analysis unit 10 and a bit allocation unit. Part 1
And 1.

[0008] The input device 1 is composed of a keyboard or a mouse. The storage device 3 is a hard disk or R
It is composed of an AM or the like, and can store data handled by the editor unit 4 or the processing unit 5.

The editor unit 4 creates and edits data to be input to the processing unit 5 by an operation from the input device 1. More specifically, the type of the application program and the instruction set described in mnemonics, and the bit width (hereinafter, referred to as a designated number of bits) allocated to the instruction set are described.

The editing work in the editor unit 4 can be performed while confirming the contents on the display 2. The editing result in the editor unit 4 is stored in the storage device 3 and read out from the processing unit 5 for use.

Next, the flow of processing in the bit allocation device of the present embodiment will be described with reference to the flowchart of FIG.

First, in the data input process S1, the editor unit 4 inputs an application program, the type of instruction set, and the designated number of bits. The input operation is performed via the input device 1, and the operation is performed while confirming the input contents on the display 2.

A part of the application program input in this embodiment is shown in (Table 1). As shown in Table 2, the types of instruction sets are AND, OR, NO
T, MOV, and BRN are input. Also, “3” is described as the designated number of bits.

[0014]

[Table 1]

[0015]

[Table 2]

The data input here is stored in the storage device 3. Next, in the error check processing S2, the application program described in the data input processing S1 is read from the storage device 3, and an error in the description is detected by the instruction analysis unit.

In step S3, an error check process S
As a result of the error detection in step 2, it is determined whether or not there is an error. If there is no error, the process proceeds to the instruction code transition frequency measurement process S4, and if there is an error, the data correction process S4
Move to 6.

In the data correction process S6, the editor unit 4 corrects an error in input data using the input device 1 and the display 2, and then proceeds to the error check process S2 again.

Here, it is assumed that no description error has been found, and the process proceeds to the instruction code transition frequency measurement processing S4.

In the instruction code transition frequency measurement processing S4, the application program is analyzed based on the type of instruction set input in the data input processing S1. Specifically, the execution frequency (hereinafter, referred to as an instruction code transition frequency) of a combination of two instruction codes that are continuously executed when the application program is executed is measured.

In the present embodiment, it is assumed that the measurement results as shown in (Table 3) have been obtained. In Table 3, the left column shows a combination of two instruction codes, and the right column shows the instruction code transition frequency of the two instruction codes. However, when the same instruction is executed successively, the bit change is 0, so that the description is omitted.

[0022]

[Table 3]

Next, in the bit allocation process S5, the bit allocation section 11 performs bit allocation for the instruction code. At this time, the instruction code transition frequency and 2
Bit assignment of the instruction code is performed with the specified number of bits specified in the input processing S1 so that the sum of the product of the number of changed bits between the instruction codes and the combination of all the two instruction codes is minimized.

In this embodiment, it is assumed that a bit allocation result as shown in (Table 4) has been obtained.

[0025]

[Table 4]

Here, AND and OR are respectively (0
00) and (001) are assigned, and the bit change between them is 1 bit. Referring to the combination of two instruction codes of AND and OR (Table 5), the instruction code transition frequency is 5. Therefore, AND and O
“5” is obtained as the product value of the number of change bits and the instruction code transition frequency for the combination of R.

The results obtained for all combinations of two instruction codes are shown in Table 5 below.

[0028]

[Table 5]

From Table 5, it can be seen that the sum of the product of the number of change bits and the instruction code transition frequency for all combinations of two instruction codes is "29".

As described above, according to the present embodiment, the bit change due to the change of the instruction code can be suppressed to the minimum in the entire application program, so that the increase in power consumption due to the bit change can be suppressed to the minimum. It becomes possible.

(Embodiment 2) In Embodiment 1, the sum of the product of the number of change bits and the instruction code transition frequency is obtained for all the bit allocation patterns, and the sum of the product of the instruction code with the smallest bit change is obtained from the sum. Bit allocation is adopted.

However, even if the bit allocation does not always minimize the bit change, other bit allocation methods can be adopted as long as the required power consumption condition is satisfied.

In the present embodiment, another bit allocation method for speeding up processing will be described.

The processing prior to the instruction code transition frequency measurement processing S4 is the same as that of the first embodiment, and therefore the description is omitted.

In the bit allocating process S1 in the bit allocating section 11, the bit allocation of the instruction code is performed in order from the combination of the two instruction codes having the large instruction code transition frequency so as to reduce the number of changed bits.

The relationship between the combination of two instruction codes and the instruction code transition frequency is the same as in the first embodiment (Table 3).

First, referring to (Table 3), the combination of two instruction codes having the maximum instruction code transition frequency is AN
It is a combination of D and OR, and it is understood that the value is “5”. Therefore, (000) is assigned to AND, and (001) is assigned to OR so that the bit change is minimized.

Next, since the instruction code transition frequency of the combination of NOT and MOV is "4", (01
(0), (110) is assigned to MOV so that the bit change from NOT becomes 1.

Next, the instruction code transition frequency is the largest
This is “3” for the combination of AND and MOV, and AND and BRN. Since bit allocation has already been completed for AND and MOV, allocation of BRN will be considered. The BRN is set so that the bit change with AND becomes 1 (100).
Assign

The results of the above allocation are shown in (Table 6).

[0041]

[Table 6]

When the sum of the product of the instruction code transition frequency and the number of change bits is obtained based on the allocation result of (Table 6), it becomes "32" as shown in (Table 7).

[0043]

[Table 7]

In this embodiment, although slightly inferior to the optimal allocation result "29" in the first embodiment, an increase in power consumption due to a bit change can be suppressed.

Furthermore, since only processing for one allocation pattern is required, there is a remarkable effect that near-optimal bit allocation can be performed at high speed.

In the above embodiments, the designated number of bits is input in the data input process S1, but the designated number of bits can be automatically set.

In this case, the smallest integer larger than the logarithm of the number of used instructions whose base is 2 is used as the designated number of bits. For example, when the number of used instructions is 5, the logarithm of 5 with 2 as a base is about 2.32, and therefore 3 which is the smallest integer larger than this is set as the designated number of bits.

[0048]

As described above, according to the present invention, instructions having a high instruction transition frequency in an application program are assigned to each instruction bit so that a bit change is reduced, thereby realizing an actual LSI. In the case where the application is operated, the bit change due to the change of the instruction code can be reduced, so that the power consumption can be suppressed low.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a bit allocation device according to an embodiment of the present invention.

FIG. 2 is a flowchart showing a processing flow in the embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 1 input device 2 display 3 storage device 4 editor 5 processing unit 10 instruction analysis unit 11 bit allocation unit

Claims (5)

[Claims] 1. An apparatus for performing bit allocation of instruction codes of a microprocessor, comprising: an instruction analyzer for measuring an execution frequency (hereinafter, referred to as an instruction code transition frequency) of a combination of two instruction codes that are continuously executed; And a bit allocating unit for allocating the bit of the instruction code based on the number of change bits between the two instruction codes and the instruction code transition frequency measured by the instruction analyzing unit. apparatus. 2. A bit allocating unit, wherein the sum of products of the number of changed bits between two instruction codes and the frequency of instruction code transitions for all combinations of two instruction codes is set to a minimum value or a value smaller than a predetermined value. 2. The instruction code bit allocating device according to claim 1, wherein the instruction code is allocated with a designated number of bits. 3. The method according to claim 2, wherein instead of designating the number of bits, the instruction code is allocated with the number of bits corresponding to the smallest integer greater than the logarithm of the number of instructions used with base 2. Instruction code bit assignment device. 4. The bit allocating unit performs bit allocation of an instruction code such that the number of changed bits between the two instruction codes decreases in order from the combination of the two instruction codes having the highest instruction code transition frequency. 2. A bit allocating apparatus for an instruction code according to claim 1, wherein: 5. A method for allocating bits of an instruction code of a microprocessor, comprising: a process of measuring an execution frequency (hereinafter, referred to as an instruction code transition frequency) of a combination of two instruction codes executed continuously. Bit allocation of instruction codes is performed so that the total sum of the product of the number of change bits between the two instruction codes and the instruction code transition frequency for all combinations of the two instruction codes is smaller than a minimum or a predetermined value. A bit allocation method for an instruction code including a bit allocation process.