JPH10185989A - Semiconductor part-mounting board - Google Patents
Semiconductor part-mounting boardInfo
- Publication number
- JPH10185989A JPH10185989A JP8356339A JP35633996A JPH10185989A JP H10185989 A JPH10185989 A JP H10185989A JP 8356339 A JP8356339 A JP 8356339A JP 35633996 A JP35633996 A JP 35633996A JP H10185989 A JPH10185989 A JP H10185989A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor component
- board
- mounting board
- vertical connector
- component mounting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Testing Of Individual Semiconductor Devices (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、半導体部品の温度環境
試験及び機能試験が行われる恒温槽装置で、その恒温室
内に挿入されて使用される半導体部品搭載ボードの改良
に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thermostatic chamber apparatus for performing a temperature environment test and a function test of a semiconductor component, and relates to an improvement of a semiconductor component mounting board used by being inserted into the thermostatic chamber.
【0002】[0002]
【従来の技術】CPUやメモリなどの半導体部品の環境
試験として、恒温槽装置を用いるバーンイン等が行われ
ている。即ち、ヒータによって昇温された空気がファン
により供給され所定の温度に維持された恒温室に、ソケ
ットなどを介して半導体部品の搭載された半導体部品搭
載ボードが装填され、該室内で繰り返される昇温・降温
操作に対して、電力の供給された半導体部品がスティミ
ュラス信号に対しどのような状態変化を示すかを調べる
温度環境試験及び機能試験が行われる。2. Description of the Related Art As an environmental test of semiconductor components such as a CPU and a memory, burn-in using a thermostat device or the like is performed. That is, a semiconductor component mounting board on which semiconductor components are mounted is loaded via a socket or the like into a constant temperature chamber in which air heated by a heater is supplied by a fan and maintained at a predetermined temperature, and is repeatedly heated in the chamber. For the temperature / temperature lowering operation, a temperature environment test and a function test are performed to check how the semiconductor component supplied with power shows a change in state with respect to the stimulus signal.
【0003】その際、前記恒温室側に設けられた試験機
器用ソケット部と前記恒温室に装填される半導体部品搭
載ボードのボード側プラグ部とからなるコネクタを結合
し、それにより、前記半導体部品搭載ボードに搭載され
た半導体部品を、装置側に内蔵される前記試験機器に接
続して、上記の試験が行われている。At this time, a connector consisting of a socket for test equipment provided on the constant temperature chamber side and a board side plug of a semiconductor component mounting board to be loaded in the constant temperature chamber is connected, whereby the semiconductor component is connected. The above test is performed by connecting a semiconductor component mounted on a mounting board to the test equipment built in the apparatus side.
【0004】[0004]
【発明が解決しようとする課題】この試験装置の歩留ま
りを上げるため、一度の試験に該恒温室内に入れること
のできる半導体部品数はできるだけ多い方が良い。しか
し近年CPUなどの半導体部品はサイズは小さくなりな
がらも多ピン化(BGAでは600ピン以上のものもあ
る)が進み、この多ピン化の影響で、半導体部品の保護
目的で各ピンに接続される保護抵抗の半導体部品搭載ボ
ード上に占める設置面積の割合が増大してしまい、恒温
室内に装填できる半導体部品数をそれほど増やすことが
できない。In order to increase the yield of the test apparatus, it is preferable that the number of semiconductor components that can be put into the constant temperature chamber in one test is as large as possible. However, in recent years, semiconductor components such as CPUs have been reduced in size but have increased the number of pins (some BGAs have more than 600 pins). Due to the increase in the number of pins, semiconductor components are connected to each pin for the purpose of protecting the semiconductor components. The proportion of the installation area of the protection resistor occupying on the semiconductor component mounting board increases, and the number of semiconductor components that can be loaded in the constant temperature chamber cannot be increased so much.
【0005】またCSP(Chip Scale Package)で
は、そのピンピッチが0.8mm以下になり、このよう
な微細化した半導体部品を搭載する半導体部品搭載ボー
ドを製作するためには、どうしてもプリント基板を多層
化する必要がある。しかし、半導体部品搭載ボードは、
前述のように、接続用のコネクタを使用するため該ボー
ドの板厚を1.6mm程度に制限せざるを得ないが、現
状のプリント基板生産技術では熱サイクルを加えること
による信頼性を配慮すると、上記板厚では10層程度が
限度であり、そのため実装数を増やそうとしてもかなり
制約を受けることになる。また多層化する際に必要とな
るスルーホール等の孔位置などのずれは、上記熱サイク
ルを経た場合に大きなサイズのボード程顕著になるた
め、半導体部品搭載ボードのサイズ拡張による半導体部
品の搭載数を増やすことには限界がある。In a CSP (Chip Scale Package), the pin pitch is reduced to 0.8 mm or less. In order to manufacture a semiconductor component mounting board on which such miniaturized semiconductor components are mounted, it is inevitable to use a multilayer printed circuit board. There is a need to. However, semiconductor component mounting boards
As described above, the thickness of the board must be limited to about 1.6 mm in order to use the connector for connection. However, in the current printed circuit board production technology, considering the reliability by adding a heat cycle, However, the above-mentioned plate thickness is limited to about 10 layers, so that even if an attempt is made to increase the number of mountings, there is considerable restriction. In addition, since the displacement of the hole position such as a through hole, etc., required when forming a multilayer, becomes more remarkable for a board of a larger size after the above thermal cycle, the number of semiconductor components mounted due to the expansion of the size of the semiconductor component mounting board is increased. There is a limit to increasing.
【0006】本発明は従来技術の以上のような問題に鑑
み創案されたもので、ボード上に搭載できる半導体部品
の実装数を大幅に増加できる半導体部品搭載ボードを提
供し、恒温槽装置一装置当たり単位時間でのバーイン検
査の能率を向上せんとするものである。The present invention has been made in view of the above problems of the prior art, and provides a semiconductor component mounting board capable of greatly increasing the number of semiconductor components mounted on the board. It is intended to improve the efficiency of burn-in inspection per unit time.
【0007】[0007]
【課題を解決するための手段】そのため本発明に係る半
導体部品搭載ボードは、半導体部品を搭載可能な子基板
を有し、保護抵抗を内蔵した縦型コネクタを介して該子
基板と接続できるようにしたことを基本的特徴としてい
る。Therefore, a semiconductor component mounting board according to the present invention has a child substrate on which a semiconductor component can be mounted, and can be connected to the child substrate via a vertical connector having a built-in protection resistor. The basic feature is that
【0008】[0008]
【作用】上記構成では、保護抵抗を内蔵した縦型コネク
タの使用による立体化のために、該抵抗の占めるスペー
スが縮小し、より多くの半導体部品を搭載できることに
なる。また子基板上に半導体部品を搭載するため、子基
板のサイズを小さくすれば、熱サイクルの影響によるス
ルーホールなどの位置ずれの心配もなく、しかも一枚の
半導体部品搭載ボード上に実装できる半導体部品数も増
化させることができる。In the above-mentioned structure, the space occupied by the resistor is reduced because of the use of a vertical connector having a built-in protection resistor, so that more semiconductor components can be mounted. Also, since the semiconductor components are mounted on the sub-board, if the size of the sub-board is reduced, there is no need to worry about misalignment such as through holes due to the effects of thermal cycling, and a semiconductor that can be mounted on a single semiconductor component mounting board The number of parts can also be increased.
【0009】[0009]
【発明の実施の形態】以下本発明の実施の形態を説明す
る。図1乃至図4は、本発明の構成の一実施形態を示し
ている。図中1は半導体部品搭載ボード、2は子基板、
3は保護抵抗4を内蔵した縦型コネクタ、5は電源供給
用縦型コネクタを各示している。Embodiments of the present invention will be described below. 1 to 4 show an embodiment of the configuration of the present invention. In the figure, 1 is a semiconductor component mounting board, 2 is a child board,
Reference numeral 3 denotes a vertical connector having a built-in protection resistor 4, and reference numeral 5 denotes a power supply vertical connector.
【0010】前記半導体部品搭載ボード1は、恒温室に
備えられた試験機器用のソケット部に結合するプラグ部
1aを有すると共に、後述する各子基板2への電源供給
を行い、またスティミュラス信号を送ったり、半導体部
品からの出力信号を受けるための配線回路を、その表面
に形成したプリント配線基板で構成されている。そして
該配線回路と子基板2上のこれらの配線回路との接続対
応位置に、夫々後述するコネクタ3及び5の導通端子3
a、3b及び5a、5bが接触し且つ電気的に接続でき
るように、スルーホール(図示なし)が形成されてい
る。The semiconductor component mounting board 1 has a plug 1a which is connected to a socket for test equipment provided in a constant temperature chamber, supplies power to each of the daughter boards 2 described later, and outputs a stimulus signal. A wiring circuit for sending or receiving an output signal from a semiconductor component is constituted by a printed wiring board formed on the surface thereof. The conductive terminals 3 of the connectors 3 and 5, which will be described later, are respectively provided at positions corresponding to the connection between the wiring circuit and these wiring circuits on the daughter board 2.
Through holes (not shown) are formed so that a, 3b and 5a, 5b can contact and be electrically connected.
【0011】前記子基板2は、図2及び図3に示すよう
に、その中央上面に半導体部品搭載用のソケット2aを
有すると共に、その周囲に、前記半導体部品搭載ボード
1の各スルーホールに対応する位置に、同様にコネクタ
3及び5の導通端子3a、3b及び5a、5bが接触し
且つ電気的に接続できるように、電源供給用、スティミ
ュラス信号送信用及び半導体部品出力信号受信用のスル
ーホール2b及び2cが設けられている。そして前記ソ
ケット2aの各端子とこれらに対応するスルーホール2
b及び2cとが、夫々配線回路によって電気的に接続さ
れている。As shown in FIGS. 2 and 3, the daughter board 2 has a socket 2a for mounting a semiconductor component on the center upper surface thereof, and a socket corresponding to each through hole of the semiconductor component mounting board 1 around the socket 2a. And through holes for power supply, stimulus signal transmission, and semiconductor component output signal reception so that the conductive terminals 3a, 3b and 5a, 5b of the connectors 3 and 5 are also in contact with each other and can be electrically connected. 2b and 2c are provided. Each terminal of the socket 2a and the corresponding through hole 2
b and 2c are electrically connected to each other by a wiring circuit.
【0012】前記コネクタ3は、図4に示されるよう
に、保護抵抗4が複数並列した状態で内蔵されており、
更に該抵抗4の端子が夫々延出して、コネクタの導通端
子3a及び3bが形成されている。なお、本構成におい
て、前記電源供給用縦型コネクタ5も両方の端子が夫々
延出して、縦型構成となっている。As shown in FIG. 4, the connector 3 has a plurality of protective resistors 4 built therein in parallel.
Further, the terminals of the resistor 4 extend to form conductive terminals 3a and 3b of the connector. In this configuration, the power supply vertical connector 5 also has a vertical configuration with both terminals extending respectively.
【0013】上記半導体部品搭載ボード1に子基板2を
搭載する場合は、図3に示されるように、コネクタ3及
び5の夫々の端子を、半導体部品搭載ボード1と子基板
2の対応する各スルーホールにはめ入れることで行われ
る。このように搭載することで、保護抵抗4を内蔵した
縦型コネクタ3の使用による立体化のために、該抵抗4
の占めるスペースが縮小し、より多くの半導体部品を搭
載できることになった。図1は半導体部品搭載ボード1
上への子基板2の搭載状態を示している。この例では一
枚の半導体部品搭載ボード1上に20枚の子基板2が搭
載できることになった(従って半導体部品は計20個搭
載可能)。これに対し、従来構造の半導体部品搭載ボー
ドでは、同じサイズの場合、半導体部品は15個しか搭
載できない。When the child board 2 is mounted on the semiconductor component mounting board 1, as shown in FIG. 3, the terminals of the connectors 3 and 5 are connected to the respective terminals of the semiconductor component mounting board 1 and the child board 2. This is done by fitting it into a through hole. By mounting in this way, the use of the vertical connector 3 having the built-in protection resistor 4 makes the resistor 4
The space occupied by the device has been reduced, and more semiconductor components can be mounted. FIG. 1 shows a semiconductor component mounting board 1
The mounting state of the child board 2 on the top is shown. In this example, 20 sub-boards 2 can be mounted on one semiconductor component mounting board 1 (accordingly, a total of 20 semiconductor components can be mounted). On the other hand, in a semiconductor component mounting board having a conventional structure, only 15 semiconductor components can be mounted in the same size.
【0014】図5乃至図7は、CSP型の半導体部品を
搭載する半導体部品搭載ボード1の構成を示している。
上記構成と基本的な構成は同じであるので、同じ構成に
は同一の番号を付している。図6に示すように、半導体
部品搭載ボード1上にスペーサ6を介して子基板2が搭
載されているが、更に保護抵抗を内蔵した縦型コネクタ
3を介して、半導体部品搭載ボード1と子基板2とが電
気的に接続されている。この例では、196ピンのCS
Pであるが、リードのピッチが0.8mmとなっている
ため、半導体部品搭載ボード1を製作する場合パターン
幅100μmでも、150μmのギャップしかとれな
い。そのため現在のプリント基板製造技術では、サイズ
の小さいものしか作り得ない。しかし本例のように、子
基板2搭載式にしたことと、抵抗内蔵式縦型コネクタ3
を使用したことに伴って、図7に示すように、54個の
搭載が可能になった。FIGS. 5 to 7 show the structure of a semiconductor component mounting board 1 on which CSP type semiconductor components are mounted.
Since the basic configuration is the same as the above configuration, the same configuration is denoted by the same reference numeral. As shown in FIG. 6, a child board 2 is mounted on a semiconductor component mounting board 1 via a spacer 6, and further connected to the semiconductor component mounting board 1 via a vertical connector 3 having a built-in protection resistor. The substrate 2 is electrically connected. In this example, 196-pin CS
Although the pitch is P, since the lead pitch is 0.8 mm, a gap of only 150 μm can be obtained even when the pattern width is 100 μm when the semiconductor component mounting board 1 is manufactured. Therefore, with the current printed circuit board manufacturing technology, only small-sized products can be manufactured. However, as shown in this example, the child board 2 mounted type and the built-in resistor type vertical connector 3
As shown in FIG. 7, with the use of, 54 can be mounted.
【0015】[0015]
【発明の効果】以上詳述した本発明の構成によれば、保
護抵抗を内蔵した縦型コネクタの使用による立体化のた
めに、該抵抗の占めるスペースが縮小し、より多くの半
導体部品を搭載できることになる。また子基板上に半導
体部品を搭載するため、子基板のサイズを小さくすれ
ば、熱サイクルの影響によるスルーホールなどの位置ず
れの心配もなく、しかも一枚の半導体部品搭載ボード上
に実装できる半導体部品数も増化させることができる。
そのため、恒温槽装置一装置当たり単位時間でのバーイ
ン検査の能率が大幅に向上できることになる。According to the structure of the present invention described in detail above, the space occupied by the resistor is reduced and the number of semiconductor components mounted is increased due to the use of a vertical connector having a built-in protection resistor. You can do it. Also, since the semiconductor components are mounted on the sub-board, if the size of the sub-board is reduced, there is no need to worry about misalignment such as through holes due to the effects of thermal cycling, and a semiconductor that can be mounted on a single semiconductor component mounting board The number of parts can also be increased.
Therefore, the efficiency of burn-in inspection per unit time per thermostat apparatus can be greatly improved.
【図1】本発明の構成の一実施形態に係る半導体部品搭
載ボードを示す平面図である。FIG. 1 is a plan view showing a semiconductor component mounting board according to an embodiment of the present invention.
【図2】上記構成に使用される子基板の構成を示す平面
図である。FIG. 2 is a plan view showing a configuration of a daughter board used in the above configuration.
【図3】該子基板にコネクタが接続された状態を示す側
面図である。FIG. 3 is a side view showing a state where a connector is connected to the daughter board.
【図4】保護抵抗内蔵式縦型コネクタの構成を示す説明
図である。FIG. 4 is an explanatory diagram showing a configuration of a vertical connector with a built-in protection resistor.
【図5】本発明の構成の他の実施形態に係る子基板の構
成を示す平面図である。FIG. 5 is a plan view showing a configuration of a child board according to another embodiment of the configuration of the present invention.
【図6】そのA−A線断面を示す断面図である。FIG. 6 is a sectional view showing a section taken along line AA.
【図7】上記実施形態における半導体部品搭載ボードを
示す平面図である。FIG. 7 is a plan view showing a semiconductor component mounting board in the embodiment.
1 半導体部品搭載ボード 2 子基板 2a ソケット 2a、2b スルーホール 3 縦型コネクタ 3a、3b、5a、5b 端子 4 保護抵抗 5 電源供給用縦型コネクタ 6 スペーサ DESCRIPTION OF SYMBOLS 1 Semiconductor component mounting board 2 Substrate 2a Socket 2a, 2b Through hole 3 Vertical connector 3a, 3b, 5a, 5b Terminal 4 Protection resistor 5 Power supply vertical connector 6 Spacer
Claims (1)
を行う恒温槽装置の恒温室内に、半導体部品を搭載して
挿入し、試験機器にコネクタを介して電気的に結合する
半導体部品搭載ボードにおいて、半導体部品を搭載可能
な子基板を有し、保護抵抗を内蔵した縦型コネクタを介
して該子基板と接続できるようにしたことを特徴とする
半導体部品搭載ボード。A semiconductor component mounting board that mounts and inserts semiconductor components into a thermostatic chamber of a thermostat device for performing a temperature environment test and a function test of a semiconductor component and electrically couples the test component with a test device via a connector. A semiconductor component mounting board having a child substrate on which a semiconductor component can be mounted, and being connectable to the child substrate via a vertical connector having a built-in protection resistor.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8356339A JPH10185989A (en) | 1996-12-26 | 1996-12-26 | Semiconductor part-mounting board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8356339A JPH10185989A (en) | 1996-12-26 | 1996-12-26 | Semiconductor part-mounting board |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH10185989A true JPH10185989A (en) | 1998-07-14 |
Family
ID=18448541
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8356339A Pending JPH10185989A (en) | 1996-12-26 | 1996-12-26 | Semiconductor part-mounting board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH10185989A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6392530B2 (en) | 2000-06-09 | 2002-05-21 | Yamaichi Electronics Co., Ltd. | Resistor array board |
-
1996
- 1996-12-26 JP JP8356339A patent/JPH10185989A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6392530B2 (en) | 2000-06-09 | 2002-05-21 | Yamaichi Electronics Co., Ltd. | Resistor array board |
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Legal Events
Date | Code | Title | Description |
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A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20030930 |