JPH10178173A - Method and device for simulating semiconductor device and its recording medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simulate reverse short channel effect easily and at a high speed. SOLUTION: When a first conductivity type impurity is introduced to a semiconductor substrate, a data of rearrangement distribution showing polarization at the time an already-introduced second conductivity type impurity is rearranged is generated (ST11), and the generated data of rearrangement distribution is added to a data of impurity distribution to be inputted so as to synthesize a new data thereof (ST12), and then a specified physical equation or characteristic equation is solved by using the new data, so as to calculate a desired characteristic (ST9). In addition, the data of rearrangement distribution is updated according to the gate length (ST14). Through such a simplified procedure such as addition of the data thereof, rearrangement of impurity due to point failure can be reflected to device simulation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for simulating a semiconductor device, and more particularly to a device simulation of electric characteristics or physical quantities in a field effect transistor or the like, for example, a gate length dependence of a gate threshold voltage. Further, the present invention relates to a simulation device for a semiconductor device that can suitably execute the simulation method, and a recording medium storing a program of the simulation method.

[0002]

2. Description of the Related Art With the recent trend toward higher integration and miniaturization of semiconductor devices, insulated gate field effect transistors such as MOS
FET (Mental Oxide Semiconductor Field Effect Tra
nsistor) gate length has been reduced. MOSFE
When the gate length is shortened at T, generally, the gate threshold voltage tends to suddenly decrease from a certain gate length. This decrease is called roll-off, and has been known for a relatively long time as a typical phenomenon of the short channel effect.

However, if the gate length of the MOSFET is further reduced due to further miniaturization of the semiconductor device, the gate threshold voltage once increases with the shortened gate length, and then rapidly decreases in accordance with the short channel effect. Phenomenon is seen. The increase in the gate threshold voltage immediately before the gate threshold voltage decreases due to the short channel effect is called roll-up or reverse short channel effect.

FIG. 11 is a graph schematically showing a relationship between a gate length and a gate threshold voltage when a short channel effect and an inverse short channel effect appear. In this graph, the solid line shows the case where the inverse short channel effect appears, and the broken line shows the case where it does not appear. In both the case of the solid line and the case of the broken line,
As the gate length of T decreases, the gate threshold voltage tends to decrease as a whole. This decrease is due to the generally known short channel effect. More specifically, the broken line follows a simple decreasing trend, while the solid line shows that the gate threshold voltage once rises as the gate length is shortened and then drops sharply. This rise immediately before the sharp drop is due to the inverse short channel effect.

[0005] MOSFE that requires a reduction in gate length
At T, if such an inverse short channel effect occurs,
This causes a variation in the gate threshold voltage, making it difficult to uniformly control the electrical characteristics of the transistor within the device or between the devices. As a result, it is necessary to secure a large noise margin or the like, which is a factor inhibiting high integration. Therefore, there is an increasing demand for a simulation technique for effectively predicting the inverse short channel effect and the short channel effect.

[0006] The short channel effect is caused by the ordinary fine gate MO.
In SFETs, this is a phenomenon that appears almost always to some extent. However, the reverse short channel effect does not always appear in all cases, and the degree of occurrence varies greatly depending on the transistor structure, manufacturing conditions, and the like. It is not clear at what time this will happen. There have been many reports on this, and it is mainly observed in the surface channel type having a current path near the surface of the semiconductor substrate. Therefore, the reverse short channel effect is because the potential distribution of the current path does not change uniformly with the gate length. It is common to recognize that this phenomenon occurs. There are reports that the potential distribution changes depending on the gate length due to the shape effect of fine gate bird's beak at the gate edge. However, according to recent reports, point defects generated during ion implantation or the like cause rearrangement of introduced impurities in the vicinity of the source or drain region of the channel formation region, resulting in an uneven distribution of impurities in the channel formation region below the gate electrode. Has become the mainstream in recent years. This concept is based on a diffusion model of a point defect-impurity pair, in which diffusion proceeds by a pair of a point defect (for example, a hole or interruption defect) and an impurity.

FIGS. 12 and 13 show an N-channel MOS.
FIG. 9 is a schematic diagram for explaining, using a FET as an example, the rearrangement of impurities at the end of a P-type channel formation region, paying attention to a portion where the P-type impurity concentration is higher than the surroundings. FIG. 12 shows a case of a normal surface channel type in which a source or drain region is arranged below both ends of a gate, and FIG. 13 shows a case of a surface channel type in which a low concentration LDD (Lightly Doped Drain) region is arranged on the gate center side. Is the case. Since the rearrangement of impurities is symmetric on the source side and the drain side, only the source side is shown in these drawings, and the following description will be made on the source side. It is expected that a portion having a low impurity concentration will be formed around the portion due to the rearrangement, but is not illustrated for simplicity. 12 and 13, reference numeral 100 denotes a semiconductor substrate, 101 denotes a source region into which an N-type impurity is introduced at a high concentration, 102 denotes a channel formation region, 103 denotes a gate insulating film, 104 denotes a gate electrode, Reference numeral 105 denotes an LDD region into which an N-type impurity is introduced at a relatively low concentration, 106 denotes a sidewall spacer, S denotes a source electrode terminal, and G denotes a gate electrode terminal. In the impurity concentration distribution of each figure, reference numeral 107 denotes an N-type impurity concentration distribution of the source region 101 (and the LDD region 105);
Indicates a P-type impurity concentration distribution of the channel formation region 102.

Normally, impurities are introduced into the source region 101 (and the LDD region 105) by an ion implantation method.
0 is introduced. These point defects diffuse around the impurity region in a heating step such as activation annealing of these impurity regions or film formation when forming the sidewall spacers 106. In the diffusion model based on the point defect-impurity pair, diffusion of the point defect causes impurity diffusion. As a result, the P-type impurity concentration 108 initially having a flat distribution as shown by a broken line in FIGS. 12 and 13 is changed from the channel forming region 102 near the point defect diffusion to the source region as shown by a solid line, for example. 101
It is generally thought that it becomes higher toward the side. This high concentration is due to the fact that a P-type impurity having the same type as that of the channel formation region 102 below the gate electrode 104 is deeper than the source region 101 (and the LDD region 105), the gate center side of the channel formation region 102, or the channel formation region 102. This is due to the phenomenon that the diffusion from the region to the shallow channel formation region 102 immediately below the gate electrode 104 occurs. Also, this high concentration,
As a result of diffusion of the N-type impurity near the PN junction into the source region 101 (and the LDD region 105), a phenomenon that the vicinity of the PN junction relatively becomes P-type as compared with the case where there is no rearrangement is also shown. .

When this phenomenon occurs, the P-type impurity concentration distribution in the channel forming region 102 under the gate electrode 104 changes depending on the gate length, and accordingly, the gate electrode 10
4 changes the potential distribution below, so that the state of carriers flowing through the channel forming region 102 also changes. As a result, the gate threshold voltage changes depending on the gate length, and an inverse short channel effect appears. The mechanism described above, that is, the idea that the impurity in the channel formation region is biased by the rearrangement of the impurity due to the diffusion of the point defect, and this causes an inverse short channel effect, is being generally accepted.

Based on the recognition of the inverse short channel effect, in recent years, research and development of a calculation model of the interaction between a point defect and an impurity have been advanced, and the inverse short channel effect described above has been simulated using a point defect model. Has become able to reflect this phenomenon. In addition, there are increasing reports that the measured value of the inverse short channel effect and the simulation result match well. Examples of such reports include, for example, the following. HIHanafi, et al. "A Model for Anomalous Short-Ch
annel Behavier in Submicron MOSFET's "IEEE EDL-14,
pp.575, 1993. (Reference 1) CSRafferty, et al. "Explanation of Reverse Short
Channel Effect by Defect Gradients "IEDM93, pp.3
11, 1993. (Reference 2) T. Kunikiyo, et al. "Reverse Short-Channel Effect
Due to Lateral Diffusion of Point-Defect Induced b
y Source / Drain Ion Implantation "IEEE CAD-13, pp.
507, 1994. (Reference 3)

[0011]

As described at the outset,
By using the conventional classical simulation method that does not consider the point defect, it is not possible to perform a highly accurate simulation by taking into account the inverse short channel effect caused by the point defect.

Further, when a simulation method having a point defect model which has been recently developed is used, it is possible to simulate the inverse short channel effect, but the calculation model is complicated and the number of parameters is large. Therefore, there is a problem that the handling becomes difficult and the simulation time becomes very long. For example, in the above document 1, a convex portion and a concave portion having a high concentration by impurity rearrangement are provided at both ends of a channel forming region near a source region or a drain region, respectively. The height, width, shape, etc. are changed, and it is not easy to reflect such a complicated model in numerical calculation. Further, in the above-mentioned Reference 3, the Monte Carlo method is used, and it is difficult to set conditions in such a particle model, and it is inevitable that the simulation time becomes long due to the necessity of performing calculations for each charge. It should be noted that the above document 2 does not show a specific calculation model. Therefore, the simulation method having the conventional point defect model is not yet suitable for provision to a development group, a production line, or the like, and is currently used only in a research range.

The present invention has been made in view of the above-mentioned circumstances, and is based on a conventional classical simulation method which does not consider a point defect. It is another object of the present invention to provide a new method of simulating a semiconductor device capable of performing the inverse short channel effect simulation easily and at high speed. In addition, another object of the present invention is to provide a simulation apparatus suitable for carrying out the simulation method and a recording medium having a built-in simulation program.

[0014]

In order to solve the above-mentioned problems of the prior art and achieve the above object, the present inventor calculates a point defect element by a conventional classical simulation which does not consider a point defect. To effectively incorporate the model without complicating the model, first consider adding a distribution in consideration of impurity rearrangement (in the present invention, referred to as a rearrangement distribution) in an impurity introduction simulation (process simulation) of semiconductor manufacturing. A patent application has already been filed for its contents. The present invention more directly uses various characteristics (for example, a gate threshold voltage V) of a semiconductor device by using impurity distribution data from process simulation or actual measurement.
th, transconductance gm, etc.) and physical quantities (mobility μ,
This is applied to a simulation (device simulation) for calculating potential or electric field strength.
At that time, in terms of channel modulation, it is sufficient to provide a portion where the concentration is increased only in the channel formation region, and it has been concluded that this will have less influence on the source and drain regions and the effective channel length. Was.

That is, the semiconductor simulation method according to the present invention is a method for simulating a semiconductor device for estimating predetermined characteristics of a semiconductor device, wherein the impurity of the first conductivity type is already introduced when introduced into the semiconductor substrate. Relocation distribution data indicating a bias when the second conductivity type impurity is rearranged is generated, and the generated relocation distribution data is added to the impurity distribution data input to the device simulation to generate new impurity distribution data. After synthesis,
A predetermined physical equation or a characteristic equation is solved using the new impurity distribution data to calculate the predetermined characteristic.

Thus, the impurity of the second conductivity type (that is, the same conductivity type as that of the channel forming region) can be obtained at the time of introducing the impurity of the first conductivity type immediately before the device simulation is performed, for example, with respect to the impurity distribution data obtained from the process simulation. It is possible to reflect the rearrangement of the impurity due to the point defect in the device simulation by a simple procedure such as adding the rearrangement distribution data indicating the deviation of the distribution. On the other hand, the method of adding the relocation distribution to the process simulation has an advantage that the semiconductor device manufacturing process such as impurity diffusion can be reflected in the relocation distribution shape, but only the impurity concentration distribution data according to the diffusion calculation model can be obtained. Therefore, the possible distribution shapes are limited. In the present invention, the process of forming the rearrangement distribution data is provided separately from the simulation process, and therefore, there is an advantage that input distribution data for matching a complicated phenomenon such as the inverse short channel effect with the actually measured value is easily obtained. . Further, the relocation distribution data can be easily changed, and the entire simulation time can be reduced.

Preferably, in the synthesis of the impurity distribution data, the relocation distribution data may be added in a form of being spatially separated from the first conductivity type impurity distribution in the input impurity distribution data. This is because if the rearrangement distribution extends to the source and drain regions (or LDD regions), the effective channel length tends to be increased by moving the PN junction position, and the system tends to change in a direction in which the short channel effect is less likely to appear. It is.

Considering that it is generally considered that the rearrangement of impurities is concentrated near the surface of the channel forming region, the rearrangement distribution data is obtained by assuming that the impurity concentration has a maximum value on the surface of the semiconductor substrate. Good. As a method of specifically expressing the process of generating the reverse short channel effect by shortening the gate length, it is preferable to change the degree of spread of the impurity concentration distribution. For example, the value indicating the degree of spread of the distribution is constant from the position indicating the maximum value of the impurity concentration to the center of the gate over an arbitrary value of the gate length, and gradually becomes smaller as the gate length becomes shorter than the arbitrary value. To be smaller. By doing so, the maximum impurity concentration can be kept constant even when the gate length is extremely short and the rearrangement distributions on the source side and the drain side overlap, which is preferable. This is because, when the gate length is shortened and the relocation distribution concentration apparently sharply increases at the stage of transition from a region where the inverse short channel effect looks large to an extremely fine gate region where the short channel effect is dominant, This is because it is empirically recognized that the behavior is far from the actual behavior of the gate threshold voltage.

According to the present invention, there is provided a semiconductor device simulation apparatus for estimating predetermined characteristics of a semiconductor device, comprising: an impurity distribution data of an impurity introduced into a semiconductor substrate; Input means for inputting relocation data indicating a bias when the second conductivity type impurity already introduced is rearranged when the impurity of the type is introduced into the semiconductor substrate; and A distribution setting means for generating the relocation distribution data based on the relocation data; and a new impurity distribution by adding relocation distribution data from the distribution setting means to the impurity distribution data from the input means. A distribution synthesis unit for synthesizing data, and a predetermined physical equation or characteristic using the new impurity distribution data from the distribution synthesis unit. Analyzing means for calculating the predetermined characteristic by solving the equation; and changing the rearrangement distribution data based on the rearrangement data, and the new impurity distribution output from the distribution synthesizing means to the analysis means. Distribution update means for updating data.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a semiconductor device simulation apparatus and a simulation method according to the present invention will be described in detail with reference to the accompanying drawings. Since the recording medium according to the present invention stores a program indicating the procedure of the simulation method of the present invention,
The description here is omitted. Although the present invention can be applied to various device simulations in which the rearrangement of impurities has an effect, here, the present invention will be described by taking as an example the case of estimating the reverse short channel effect in the gate length dependence of the gate threshold voltage of a MOSFET. . Also, an N-type channel MOSFET (NMOSFET) will be described as an example, but a P-type channel MOSFET (PMOSFET) can be similarly applied by reversing all conductivity types.

FIGS. 1 and 2 are schematic cross-sectional views of a surface channel type NMOSFET to be simulated by the present invention. FIG. 1 shows a case where a source or drain region is arranged below both ends of a gate, and FIG. 2 shows a case where an LDD is arranged on the center side of the gate. 1 and 2, reference numeral 1 denotes a semiconductor substrate, 2 and 3 each a source region and a drain region into which an N-type impurity is introduced at a high concentration, 4 a channel formation region, 5 a gate insulating film, 6
Is a gate electrode, 7 is an LDD region into which an N-type impurity is introduced at a relatively low concentration, 8 is a sidewall spacer, S is a source electrode terminal, D is a drain electrode terminal, and G is a gate electrode terminal. In the following description, the case of the LDD structure of FIG. 2 will be described as an example, but the present invention can be applied to the case of FIG.

FIG. 3 is a block diagram showing a schematic configuration of the simulation apparatus of the present invention. The simulation apparatus 10 roughly includes a transistor model,
A preprocessor 11 for processing various data; a main processor 12 for obtaining a solution by taking a predetermined basic equation
And a post processor 13 for converting the result of the main processor 12 into a form conforming to a predetermined output format and outputting the result.
And an input / output device (not shown). Also,
A process simulator 14 is connected to the preprocessor 11 online or offline.

The process simulator 14 according to the present embodiment is an impurity simulator for estimating the distribution of impurities introduced into a semiconductor substrate under predetermined manufacturing conditions in a semiconductor wafer process. The means for estimating the impurity distribution is not limited to the process simulator 14 and may be any means that provides the preprocessor 11 with process parameters such as impurity distribution data by actual measurement or the like.
The preprocessor 11 includes an input unit 15 for inputting various data including impurity data and parameters, and a model / condition setting unit 16 for creating an analysis model from various data and formulating conditions such as boundaries and biases. In the present invention, in addition to the above, a means for adjusting the distribution data according to the phenomenon of the actual device (in this case, the inverse short channel effect), that is, a distribution generating means 17, a distribution synthesizing means 18, and a distribution updating means 19 are newly provided. ing. The functions and operations of these units will be described in the following simulation method.

FIG. 4 is a flowchart showing the overall flow of the simulation method of the present invention. First, impurity distribution data is created by the process simulator 14 of FIG. 3 (or an apparatus for performing actual measurement, etc.). More specifically, the P-type impurity concentration which is introduced into the semiconductor substrate 1 shown in FIG. 2 and determines the concentration of the channel formation region 4 and the LDD region 7 which extends inward from the source region 2 and the drain region 3 and the opposed space therebetween. The relationship between the position and the concentration with respect to the N-type impurity concentration is obtained and output as impurity distribution data.

When the device simulation is started, parameters are input to the input unit 15 of the preprocessor 11 in step ST1. These parameters include the structure parameters of the NMOSFET, process parameters other than the impurity distribution, and the like. Step ST2
In step ST4, the model / condition setting unit 16 performs modeling such as discretization of analysis points and setting of boundary conditions, bias conditions, and the like based on the input parameters in a conventional manner.

On the other hand, simultaneously with the start of the simulation,
The impurity distribution data and the rearrangement data from the process simulator 14 are input to the input unit 15 of the preprocessor 11 (step ST5), and the impurity distribution data is adjusted based on the rearrangement data (step ST5). ST6). This distribution adjustment is for reflecting the impurity rearrangement due to the point defect in the impurity distribution data in consideration of the inverse short channel effect, and will be described later in detail.

In the next steps ST7 to ST9, numerical calculation is performed in the main processor 12 of FIG. 3 by using a method similar to a normal device simulator. That is, basic equations (physical equations) such as Poisson's equation and current continuity equation are standardized (discretized) by, for example, a difference method (step ST7), and initial values are set (step ST8). Is calculated (step ST9). In this numerical calculation, a solution of the characteristic equation is finally obtained by using intermediate variables (for example, mobility and electric field strength) obtained from the basic equation. In the present embodiment, as the characteristic equation, the gate length Lg
Is required as an expression of the gate threshold voltage Vth having the following as a parameter. In addition, an equation for calculating a physical quantity involved in the characteristic equation, for example, a work function or a gate capacitance by using the structural parameters is also required. Thereafter, when the calculation result data is output in a predetermined format by the post-processor 13 (step ST10), the simulation ends.

In the present invention, it is assumed that the reverse short channel effect described in the prior art is caused by a phenomenon of impurity rearrangement due to point defects. FIG. 2
In other words, the source and drain regions 2, 3 or LD
At the time of ion implantation for introducing an N-type impurity for the purpose of forming the D region 7, a point defect is introduced into the semiconductor substrate 1 and diffused into the P-type impurity region (channel formation region 4) already introduced in the thermal process. As a result, P-type impurities cause rearrangement. It is considered that the reverse short channel effect is caused by a kind of channel modulation in which the potential of the channel formation region 4 does not change uniformly due to the rearrangement of the impurities.

Hereinafter, the contents of step ST6 for adjusting the impurity distribution data in consideration of the rearrangement of the impurities will be described in detail. In this distribution adjustment, data representing the distribution after the rearrangement (rearrangement distribution data) is created based on the rearrangement data input in the previous step ST5, and this is converted into the impurity distribution data obtained from the process simulator 14. The addition is performed to synthesize new impurity distribution data.

First, in step ST11, rearrangement distribution data is created. Here, the relocation distribution data created in the present embodiment satisfies the following conditions included in the relocation data. (1) The conductivity type of the impurity constituting the rearrangement distribution is the same as that of the impurity under the gate electrode 6. (2) The rearrangement distribution is adjacent to the PN junction in the channel formation region 4 under the gate electrode 6. And does not overlap with the PN junction,
(3) The relocation distribution should be a smooth distribution, for example, a Gaussian distribution, in the channel plane direction and the substrate depth direction.
The maximum value of the impurity concentration in the rearrangement distribution should be constant regardless of the gate length. (5) The impurity concentration of the rearrangement distribution should have the maximum value on the surface of the semiconductor substrate. (6) The maximum of the rearrangement distribution. The degree of spreading from the density point toward the gate center should be constant when the gate length Lg is equal to or greater than an arbitrary value (hereinafter, referred to as “Lgx”), and gradually decrease as the gate length becomes shorter than Lgx. , (7) The extent of the rearrangement distribution other than (6) above (for example, in the three-dimensional simulator, the outside of the gate, the substrate depth direction and the channel width direction) is constant regardless of the gate length Lg. .

In the next step ST12, the gate length Lg
The impurity distribution data at the time when the inverse short channel effect first appears when is gradually shortened is determined by synthesis. 5 and 6 are graphs schematically showing the concentration profile of the impurity distribution after the synthesis, taking the source side as an example, and FIG. 5 shows a horizontal cross section along the line AA in FIG. 6 shows a cross section in the substrate depth direction along the line BB in FIG. 5 and 6, reference numeral 20 denotes an N-type impurity concentration of the source region 2 and the LDD region 7, 21 denotes a P-type impurity concentration of the channel forming region 4, and 21a denotes a rearrangement concentration distribution added in the present invention. . The broken line in the figure indicates
It is a P-type impurity concentration of a conventional classical simulation that does not consider impurity rearrangement due to a point defect, which is added for reference.

As is apparent from FIG. 5, the P-type impurity concentration portion added in the present invention, that is, the rearrangement distribution 21a
Is positionally distant from the N-type impurity concentration 20 of the opposite conductivity type, and therefore does not affect the PN junction position. This is because, when the redistribution distribution 21a overlaps with the N-type impurity concentration 20, the PN junction position is shifted to the outside of the gate to increase the effective gate length. This is to prevent model fluctuation. Therefore, when the effective gate length of the model is adjusted in consideration of this variation, such a constraint (the condition (2)) is not necessarily required. Further, as is clear from FIG. 6, in the present invention, the P-type impurity concentration is located on the surface of the semiconductor substrate so as to be the maximum. This is due to the fact that a pile-up of impurities due to point defects is formed on the surface of the substrate near the source and drain regions. Impact of High Temperature RTA ”IEICE Transactions on Electronics, Vol.J79-CII, No.6, pp.25
2, 1996.)). The drain side in FIG. 2 is obtained by folding FIG. 5 right and left. The distribution in the depth direction is exactly the same as in FIG.

Generation of the rearrangement distribution as described above (step ST11) and distribution synthesis (step ST12)
Is repeatedly executed for each gate length Lg through the change of the distribution condition in step ST14 until the end of the distribution adjustment is determined in step ST13. The determination of the end of the distribution adjustment and the change of the distribution condition are controlled by the distribution updating means 19 in FIG. 3 based on the rearrangement data. If it is determined in step ST13 that the distribution adjustment has been completed, the process proceeds to step S13.
At T15, a plurality of post-synthesis impurity distribution data are output to step ST7, and a numerical calculation is performed according to the above-described procedure. It should be noted that this adjustment end determination (step ST1)
3) may be performed after step ST9, and the numerical calculation and the distribution adjustment may be alternately repeated. If the integration time required for this distribution adjustment is equal to or shorter than the time required for modeling and setting conditions, the procedure of FIG. 4 is more efficient.

Hereinafter, the change of the distribution condition in step ST14 will be described in detail. 7 and 8
5 schematically shows the concentration distribution after the gate length Lg becomes short and the rearrangement distributions on the left and right overlap. FIG. 7 (a) →
The gate length L is in the order of FIG. 7 (b) → FIG. 8 (c) → FIG. 8 (d).
g is shorter. In FIG. 7A, the point in time when the left and right rearrangement distributions 21a start to overlap is defined as an arbitrary value Lgx of the gate length. Before reaching the value Lgx, the shape of the rearrangement distribution 21a is constant regardless of the gate length Lg. When the overlapping portion of the rearrangement distribution 21a is simply added by the synthesis of impurities, the concentration of this overlapping portion becomes higher than the concentration of the original rearrangement distribution. This rapid increase in concentration is contrary to the phenomenon of an extremely fine gate region in an actual device. That is, as shown in FIG. 11, the short-channel effect becomes dominant in the ultra-fine gate region where the gate length is shorter than the point where the gate threshold voltage increases due to the inverse short-channel effect. It has been empirically found that it is not desirable to increase the concentration in order to match the behavior.

Therefore, as shown in the above condition (6), from the gate length Lgx at which the density of the superimposed rearrangement distribution starts to become higher than the original density, the degree of spread toward the gate center is determined by the gate length Lg. It was decided to gradually decrease as the length became shorter. FIG. 7B shows a case where the gate length Lg is shorter than that of FIG. 7A. Comparing the two figures, it can be seen that the degree of spread on the gate center side is small (ie, steep). I can ask.

FIG. 8C shows a case where the gate length Lg is further reduced and the rearrangement distributions 21a on the left and right are completely overlapped with each other. After this point, the rearrangement distribution 21a
In the direction toward the center of the gate, and only the outside of the gate is added. Therefore, as shown in FIG. 8 (d), when the gate length Lg is further reduced, the intersection of the spread outside the two gates gradually moves downward, and the entire rearrangement distribution 21a gradually decreases. At the end it disappears. Although the comparison with the actual device is not clear, in the simulation, such an operation is performed because the process in which the short-channel effect gradually becomes dominant can be well expressed in the above-described extremely fine gate region.

Next, the change in the degree of spread of the rearrangement distribution 21a toward the gate center will be described in more detail. FIG. 9 is an example of a graph showing a change in how the rearrangement distribution spreads toward the gate center with respect to the gate length.
A Gaussian distribution represented by the following equation is used for the first rearrangement distribution 21a.

C (x) = Cmax × exp (−x ² / 2σ _x ² ) (1) where C (x) is the impurity concentration of the rearrangement distribution, and Cmax is the maximum impurity concentration of the rearrangement distribution. the value, x is the distance from the position of the Cmax to the gate center direction is a parameter indicating the sigma _x spreads degree. In FIG. 9, the vertical axis represents the value of σ _x ,
The horizontal axis represents the gate length L _g. The slope 30 of σ _x in FIG. 9 is expressed by the following equation using arbitrary constants a, b, c, and d.

Σ _x = a × (b−Lg) ^d + c (2) Specifically, in the inclined portion 30 shown in FIG. 9, a = −0.34
832, b = 0.745 and c = 1.5. Also, L
_{When g} > 0.745 μm, σ _x is constant.

Simulation Results FIG. 10 shows the results obtained by using the equations shown in FIG.
7 is a graph showing the result of simulating the gate length dependence of the gate threshold voltage of a MOSFET. FIG. 10 shows simulation results when the drain voltage is 0.1 V and when the drain voltage is 2.5 V, respectively, in comparison with actual measurement values.
In FIG. 10, reference numeral 40 denotes a simulation result, and 41 denotes an actually measured value. For comparison, reference numeral 42 shows a result of a conventional classical simulation that does not consider diffusion due to point defects or mutual diffusion between different impurities. The semiconductor device based on the measured values is based on the NMOSFET having the structure shown in FIG.
A lower concentration of P than the LDD region 7 covers the DD region 7.
Type impurities are implanted. Therefore, in the result of the conventional classical simulation indicated by reference numeral 42 in FIG. 10, the inverse short channel effect appears slightly. However, there is a large difference from the measured values.

As is clear from the graph of FIG. 10, the simulation result 40 of the present invention is
When the gate length Lg is in the range of 0.2 μm to 5 μm, the degree of coincidence is high in any case where the drain voltage is different, and the tendency of the reverse short channel effect and the short channel effect is well represented.
On the other hand, the conventional classical simulation result 42
Is far from the measured value, and it can be seen that the inverse short channel effect cannot be simulated.

As described above, according to the simulation method of the present invention, an adjustment is performed on the result of a normal impurity simulation assuming that impurities are rearranged due to a point defect, and the adjusted impurity distribution data is used. By performing the device simulation, the reverse short channel effect closer to the actually measured value can be simulated in the MOSFET. Further, the impurity distribution can be adjusted by simply adding the newly generated distribution (rearranged distribution) to the distribution obtained by the impurity simulation or the like. It has been demonstrated that the inverse short channel effect and the short channel effect can be accurately simulated even by such simple data processing.

Further, in the simulation apparatus according to the present invention, distribution adjusting means 17, 18, 19 for performing simple calculation or control are provided in the preprocessing section (preprocessor 11) of the ordinary device simulation apparatus.
And the device configuration is simple. Also,
The data processing for the above distribution adjustment is easy, and it is not necessary to repeat the processing from the process simulation when making a change to the data. This makes it possible to achieve high accuracy without prolonging the processing time. . In particular, in the simulation device 10 of the present embodiment, the data processing of distribution adjustment is processed in parallel with other pre-processing (modeling and condition setting, etc.). Simulation of the channel effect is also possible.

[0042]

As described above, according to the method for simulating a semiconductor device according to the present invention, a conventional classical simulation method which does not consider a point defect is used as a basis, and a channel modulation by a point defect is performed. In consideration of the above, it is possible to provide a method of simulating a semiconductor device that can easily and quickly simulate the inverse short channel effect. In addition, it is possible to provide a simulation device and a recording medium with a built-in simulation program suitable for performing the simulation method.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view of a surface channel NMOSFET suitable for a simulation method of a semiconductor device according to the present invention, showing a normal case where a source or drain region is arranged below both ends of a gate.

FIG. 2 shows a surface channel type NMO according to an embodiment of the present invention.
FIG. 3 is a schematic cross-sectional view of an SFET, showing a case where an LDD is arranged on a gate center side.

FIG. 3 is a block diagram illustrating a schematic configuration of a simulation device according to an embodiment of the present invention.

FIG. 4 is a follow chart showing an overall flow of a simulation method according to the embodiment of the present invention.

5 is a graph schematically showing a concentration profile of an impurity distribution after the distribution synthesis (step ST14) in FIG. 4, taking a source side as an example, and showing a horizontal cross section along the line AA in FIG. 2; Show.

6 is a graph schematically showing a concentration profile of an impurity distribution similarly to FIG. 5, and shows a cross section in a substrate depth direction along line BB of FIG. 2;

FIGS. 7A and 7B are diagrams schematically showing the concentration distribution after the gate length is reduced and the left and right rearrangement distributions begin to overlap. FIGS.

8 (c) and 8 (d) schematically show the concentration distribution after the point where the gate length is further reduced and the rearrangement distribution completely overlaps, following FIG. 7 (b). FIG.

FIG. 9 is a graph showing an example of how the rearrangement distribution spreads in the gate center direction with respect to the gate length.

FIG. 10 is a graph showing the result of simulating the gate length dependence of the gate threshold voltage of an NMOSFET under the conditions of the present embodiment using the equation shown in FIG.

FIG. 11 is a graph schematically showing a relationship between a gate length and a gate threshold voltage when a short channel effect and an inverse short channel effect appear.

FIG. 12 is a schematic view for explaining impurity rearrangement at the end of a channel formation region which has conventionally been a cause of the inverse short channel effect, taking an NMOSFET as an example and focusing on a portion where the P-type impurity concentration is higher than the surroundings. FIG. 5 shows a case of a normal surface channel type in which a source or drain region is arranged below both ends of a gate.

FIG. 13 is a schematic diagram similar to FIG. 12, for explaining the rearrangement of impurities at the end of a channel formation region, and shows a case of a surface channel type in which a low-concentration LDD region is arranged on the gate center side.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... Source region, 3 ... Drain region,
4 channel region, 5 gate insulating film, 6 gate electrode, 7 LDD region, 8 sidewall spacer, 1
0: simulation device, 11: preprocessor, 1
2 ... Main processor, 13 ... Post processor, 14
... Process simulator (means for simulating impurity introduction), 15 ... Input unit (input means),
16: Model / condition setting means, 17: Distribution generation means, 1
8: distribution synthesizing means, 19: distribution updating means, 20: N-type impurity concentration distribution, 21: P-type impurity concentration distribution, 21a: rearrangement distribution, 30: degree of spread of the rearrangement distribution in the gate center direction, 40: lines Simulation result of the invention, 41: actual measurement value, 41: conventional classic simulation result, S
... Source electrode terminal, D ... Drain electrode terminal, G ... Gate electrode terminal.

Claims (17)

[Claims] 1. A method of simulating a semiconductor device for estimating a predetermined characteristic of a semiconductor device, the method further comprising: when introducing a first conductivity type impurity into a semiconductor substrate, reusing an already introduced second conductivity type impurity. After generating rearrangement distribution data indicating the bias at the time of arrangement, adding the generated rearrangement distribution data to the input impurity distribution data and synthesizing new impurity distribution data, the new impurity distribution is obtained. A method for simulating a semiconductor device, wherein a predetermined physical equation or characteristic equation is solved using data to calculate the predetermined characteristic. 2. The method according to claim 1, wherein, in synthesizing the impurity distribution data, the rearrangement distribution data is added to the impurity distribution data of the first conductivity type in the input impurity distribution data in a form of being spatially separated. A simulation method of the semiconductor device described in the above. 3. The semiconductor device simulation method according to claim 1, wherein a simulation is performed on impurity introduction in a semiconductor manufacturing process, and the impurity distribution data is obtained from the simulation result. 4. Whenever a predetermined parameter is changed,
2. The simulation method for a semiconductor device according to claim 1, wherein the relocation distribution data is updated, and synthesis of the new impurity distribution data and calculation of a predetermined characteristic are repeatedly performed. 5. The method according to claim 1, wherein the generation of the rearrangement distribution data is performed based on a position in the semiconductor substrate, an impurity amount, a maximum value of the impurity concentration, and a value indicating a degree of distribution distribution. 5. The simulation method for a semiconductor device according to claim 4, wherein a value indicating a degree of spread of the distribution is changed according to a change in the predetermined parameter. 6. The semiconductor device simulation method according to claim 5, wherein the impurity concentration of the rearrangement distribution data has a maximum value on the surface of the semiconductor substrate. 7. The predetermined parameter is a gate length of an insulated gate field effect transistor, and the predetermined characteristic for estimating the dependence of the parameter is:
A gate threshold voltage of the transistor, wherein the value indicating the degree of spread of the distribution is constant from a position indicating the maximum value of the impurity concentration to a direction toward the center of the gate over an arbitrary value of the gate length, which is constant. 6. The method according to claim 5, wherein the value is changed so as to gradually decrease as the value becomes shorter than an arbitrary value. 8. The value indicating the degree of spread of the distribution is constant regardless of the gate length in the direction outside the gate, in the depth direction of the semiconductor substrate, and in the channel width direction from the position indicating the maximum value of the impurity concentration. Item 8. A simulation method for a semiconductor device according to item 7. 9. A simulation device for a semiconductor device for estimating predetermined characteristics of the semiconductor device, comprising: an impurity distribution data of an impurity introduced into a semiconductor substrate;
Input means for inputting, when the first conductivity type impurity among the impurities is introduced into the semiconductor substrate, rearrangement data indicating a bias when the already introduced second conductivity type impurity is rearranged; A distribution setting means for generating and outputting the relocation distribution data based on the relocation data from the input means; and a relocation distribution from the distribution setting means for the impurity distribution data from the input means. A distribution synthesizing unit for synthesizing new impurity distribution data by adding data, and solving a predetermined physical equation or characteristic equation by using the new impurity distribution data from the distribution synthesizing unit and changing a predetermined parameter. Analyzing means for calculating the predetermined characteristic; and changing the relocation distribution data based on the relocation data. And a distribution updating unit for updating the new impurity distribution data output to the analyzing unit. 10. The distribution synthesizing unit, wherein the rearrangement distribution data is stored in the first impurity distribution data in the input impurity distribution data.
The semiconductor device simulation apparatus according to claim 9, wherein the semiconductor device is added to the conductivity type impurity distribution in a form separated in position. 11. The semiconductor device simulation apparatus according to claim 9, further comprising means for simulating impurity introduction in a semiconductor manufacturing process, wherein said input means inputs said impurity distribution data from said simulation means. . 12. The predetermined parameter is a gate length of an insulated gate field effect transistor, and the predetermined characteristic for estimating the dependence of the parameter is:
The input means is a gate threshold voltage of the transistor, and the input means, for the rearrangement distribution data, indicates a position in the semiconductor substrate, an impurity amount, a maximum value of the impurity concentration, and a value indicating a degree of spread of the impurity distribution. The distribution updating means inputs a value indicating the degree of spread of the impurity distribution from the position indicating the maximum value of the impurity concentration toward the gate center, and keeps the value constant over an arbitrary value of the gate length. 10. The simulation device for a semiconductor device according to claim 9, wherein the rearrangement distribution data is changed so as to gradually decrease as the value becomes shorter than the arbitrary value. 13. The semiconductor device simulation apparatus according to claim 12, wherein the maximum value of the impurity concentration takes the maximum value on the surface of the semiconductor substrate. 14. Estimating a predetermined characteristic of a semiconductor device, when an impurity of a first conductivity type is introduced into a semiconductor substrate, a bias when an impurity of a second conductivity type already introduced is rearranged is determined. The generated rearrangement distribution data is generated, and the generated rearrangement distribution data is changed according to a predetermined parameter. Each of the generated and changed rearrangement distribution data is added to the input impurity distribution data. A simulation program for a semiconductor device for synthesizing a plurality of new impurity distribution data, repeatedly solving a predetermined physical equation or characteristic equation using the plurality of new impurity distribution data, and calculating the predetermined characteristic is stored. Recording media. 15. The method according to claim 14, wherein, in synthesizing the impurity distribution data, the rearrangement distribution data is added to the impurity distribution of the first conductivity type in the input impurity distribution data in a form of being spatially separated. Recording medium. 16. The rearrangement data includes, for the rearrangement distribution data, a position in a semiconductor substrate, an impurity amount, a maximum value of an impurity concentration, and a value indicating a degree of distribution distribution. 15. The recording medium according to claim 14, wherein in the updating, a value indicating a degree of spread of the distribution is changed according to a change in the predetermined parameter. 17. The method according to claim 17, wherein the predetermined parameter is a gate length of an insulated gate field effect transistor, the predetermined characteristic for estimating an influence of the parameter change is a gate threshold voltage of the transistor, The value indicating the condition is changed from the position indicating the maximum value of the impurity concentration to the center of the gate to be constant at an arbitrary value of the gate length or more, and is gradually reduced as the gate length becomes shorter than the arbitrary value. The recording medium according to claim 16, wherein