JPH10177795A - Non-volatile semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a non-volatile semiconductor memory in which a writing time can be shortened and threshold voltage can be controlled highly accurately. SOLUTION: A threshold value detecting circuit 60 is provided at an output side of a sense amplifier 50, at the time of writing, a writing pulse is applied to a selection memory cell, after applying a pulse, threshold voltage of the selection memory cell is detected, a detected value is discriminated by a control circuit 80, a pulse width is increased with the prescribed increment rate and the pulse is applied until threshold voltage reaches the prescribed range including a target value VTH, Since after threshold voltage reaches the prescribed range, an increment rate of the pulse width is made small, applying a pulse is repeated until threshold voltage reaches the target value VTH or near the value, the number of times of applying a pulse can be largely reduced at the time of writing, a writing time can be shortened, threshold voltage of a memory cell can be controlled highly accurately.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a write operation of a nonvolatile semiconductor memory device.

[0002]

2. Description of the Related Art In a nonvolatile semiconductor memory device having a floating gate as a charge storage layer, a normal writing operation is performed using a writing pulse having a pulse width of an equal interval. FIG. 8 shows such a nonvolatile semiconductor memory element (hereinafter, referred to as a nonvolatile semiconductor memory element).
FIG. 2 is a circuit diagram showing a portion 10a of a memory cell array constituted by memory cells (referred to as memory cells). As shown, the memory cells M ₁₁ , M ₁₂ , M ₂₁ , M ₂₂ are arranged in a matrix,
The control gates of the memory cells M ₁₁ and M ₁₂ arranged in the same row are commonly connected to a word line WL ₁ , and the control gates of the memory cells M ₂₁ and M ₂₂ are commonly connected to a word line WL _2. ing. The sources of the memory cells M ₁₁ and M ₂₁ arranged in the same column are commonly connected to the source line SL ₁ , and the drain is commonly connected to the bit line BL ₁ . The sources of the memory cells M ₁₂ and M ₂₂ arranged in the same column are commonly connected to a source line SL ₂ , and the drain is commonly connected to a bit line BL ₂ .

[0003] The memory cell array 1 having the above configuration
In 0a, for example, chip erasing or block erasing is performed at the time of erasing. In this case, the word line WL
₁ and WL _2, a positive high voltage, for example, by applying a voltage of 12V, the source lines SL _1, SL ₂ and the bit lines B
L ₁ and BL ₂ are held at the ground potential GND, and the substrate of each memory cell is also held at the ground potential GND. As a result, in memory cells M ₁₁ , M ₁₂ , M ₂₁ and M ₂₂ , FN
By tunneling, electrons are injected from the substrate into the floating gate, the threshold voltage of each memory cell is maintained at a high level, and each memory cell is set to the erased state.

On the other hand, at the time of writing, a negative voltage, for example, a voltage of -7 V is applied to a word line to which a selected memory cell (hereinafter simply referred to as a selected memory cell) is connected, and other word lines are applied. Positive voltage, for example, 3.3V
And a positive voltage, for example, 3.3 V, is applied to the bit line to which the selected memory cell is connected at a predetermined time, and the other bit lines are connected to the ground potential GN.
Hold at D. Thereby, in the selected memory cell,
By FN tunneling, electrons are extracted from the floating gate to the channel region formed between the source / drain diffusion layers. By writing, the threshold voltage of the selected memory cell is set low.

Generally, at the time of writing, the same pulse width t ₀ shown in FIG. 9 is applied to the bit line connected to the selected memory cell.
Is applied. After the application of the write pulse, the threshold voltage of the selected memory cell is detected by the threshold voltage detection circuit. When the threshold voltage falls within a predetermined range, the write operation ends. By such control, the threshold voltage of the selected memory cell can be set to a predetermined value.

[0006]

However, in the above-mentioned conventional writing, there is a problem that the required writing time becomes long. As shown in FIG. 10A, before the start of writing, the memory cell is in an erased state, and its threshold voltage is V _th0 as shown. In order to change the threshold voltage at the time of writing, the application time of the write pulse must be set to be gradually larger exponentially. Therefore, by applying the write pulse having the same pulse width shown in FIG. In addition, the change in the threshold voltage of the memory cell becomes gradually smaller, and the number of application of the write pulse increases to change the threshold voltage to a predetermined threshold voltage _VTH . In writing, an operation of confirming whether or not a threshold voltage has reached a predetermined value (hereinafter referred to as "verify")
Accordingly, the application of the write pulse and the verification are repeatedly performed, so that if the number of application of the write pulse is increased, the time required for the write is lengthened.

In the writing method in which the width of the writing pulse is set to be longer at a predetermined rate, the time required for writing can be shortened, but the change in the threshold voltage due to one application of the writing pulse increases, and the "Pass" can occur. As shown in FIG. 10B, assuming that the target value of the threshold voltage _Vth is within the range of (V _TH ± ΔV _TH ), after the (i + 1) th write pulse is applied, the threshold voltage V _th becomes the target range. In some cases, it jumps over and comes off. In particular, in the case of a multi-valued memory, a lower voltage, or the like, the distribution width of the threshold voltage becomes narrower. Therefore, it is important to accurately control the threshold voltage distribution of the memory cell without lowering the writing speed.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a nonvolatile semiconductor memory device capable of shortening a writing time and accurately controlling a distribution of threshold voltages. .

[0009]

In order to achieve the above object, the present invention provides a method for controlling a threshold voltage by applying a write signal to change the amount of charge stored in a charge storage layer of a memory cell. A non-volatile semiconductor memory device for writing data, wherein at the time of writing, a pulse generating means for applying the write signal having a pulse width gradually increased to a selected memory cell; A threshold voltage detecting means for detecting a threshold voltage of the memory cell, wherein the rate of increase of the pulse width is reduced when a difference between the detected threshold voltage and a predetermined target value is equal to or less than a preset value. It has write control means.

Preferably, in the present invention, the pulse generating means sets the writing time to be longer by one digit until the threshold voltage detected by the threshold voltage detecting means reaches a predetermined range. I do.

Further, in the present invention, the write control means includes a step of determining whether a difference between the threshold voltage detected by the threshold voltage detection means and a predetermined target value is equal to or less than a preset value.
The width of the pulse is maintained at a constant value, or the width of the pulse is set gradually smaller.

According to the present invention, the width of the write pulse generated by the pulse generating means at the time of writing is set gradually wider in accordance with the number of times of writing, and is applied to the selected memory cell to be written. When the difference between the threshold voltage of the memory cell after writing and a predetermined target value reaches a certain range, the rate of increase of the write pulse width is set to a small value, and the change in threshold voltage due to writing is set. Smaller. Alternatively, hold the write pulse width at a constant value,
Alternatively, the change amount of the threshold voltage is set small by gradually setting the write pulse width to be narrow. And
When the threshold voltage of the memory cell reaches a predetermined target value or a value close to the target value by the writing, the writing ends.

Thus, the number of times of writing until the threshold voltage of the selected memory cell reaches a predetermined range can be reduced, the time required for writing can be greatly reduced, and the threshold voltage can be controlled with high precision.

[0014]

FIG. 1 is a circuit diagram showing one embodiment of a nonvolatile semiconductor memory device according to the present invention. In FIG. 1, 10 is a memory cell array, 20 is a row decoder,
Reference numeral 30 denotes a column decoder, 40 denotes a selection gate, 50 denotes a sense amplifier circuit, 60 denotes a threshold detection circuit, 70 denotes an input / output circuit, and 80 denotes a control circuit.

The row decoder 20 includes the address ADR,
For example, by receiving a row address ADR _X of m bits, by selecting a predetermined word line from the word lines WL in response to these signals, it is activated. For example, a negative voltage, for example, a voltage of -7 V is applied to a selected word line at the time of writing, and a high voltage of 12 V, for example, is applied to the selected word line at the time of erasing. In the case of batch erasing, all word lines or all word lines corresponding to the selected block are activated.

The column decoder 30 of the address ADR, for example, receives the n column address ADR _Y bits, in response to these signals, selects a predetermined signal line from the selection signal line YL, activated. A high-level voltage, for example, a power supply voltage V _CC is applied to the selected signal line.

The selection gate 40 selects a predetermined bit line BL in accordance with a signal from the selection signal line YL, and connects the selected bit line to a predetermined sense amplifier in the sense amplifier circuit 50.

The sense amplifier circuit 50 is constituted by a plurality of sense amplifiers, detects the signal potential of each bit line transferred via the selection gate 40, and reads data stored in the selected memory cell.

The threshold detection circuit 60 detects the threshold voltage of the selected memory cell based on the data read by the sense amplifier circuit 50, and outputs the detection result to the control circuit 80.
Output to

In the present embodiment, at the time of writing, the width of the write pulse applied to the selected memory cell is different from the above-described conventional write pulse, and the pulse width is gradually increased according to a predetermined algorithm in accordance with the number of times of application of the pulse. Set to a large value. The control circuit 80 controls operations such as writing in the memory chip. For example, at the time of writing, after the application of the write pulse, the control circuit 80 determines whether or not the threshold voltage of the selected memory cell has reached a predetermined range according to the detection result from the threshold detection circuit 60. Then, the write pulse width is set or the continuation / end of the write is controlled according to the determination result.

After the start of writing, until the threshold voltage of the selected memory cell reaches a predetermined range, the write pulse width is set to gradually increase at a constant increasing rate, and the writing is repeated, and the threshold voltage of the selected memory cell is repeated. Is within a predetermined range, the write pulse width is reset. For example, writing is repeated by reducing the rate of increase of the pulse width, keeping the pulse width constant, or sequentially setting the pulse width to be smaller. When the threshold voltage of the selected memory cell reaches a predetermined target value or a value near the predetermined target value, the writing is terminated. By performing such control, the control circuit 80 can set the threshold voltage of the selected memory cell to the target value or a value very close to the target value while reducing the number of times of writing.

The memory cell array 10 is composed of memory cells arranged in a matrix. The memory cells in each row are connected to the same word line, and the memory cells in each column are connected to the same bit line. For example, at the time of writing, externally input write data is input to the memory cell array 10 via the input / output circuit 70 and the selection gate 40, and a write pulse is applied to the selected memory cell in accordance with the write data. Then, writing is performed. After the application of the write pulse, the threshold voltage of the selected memory cell is detected by the threshold detection circuit 60 via the selection gate 40 and the sense amplifier circuit 50, and the detection result is transmitted to the control circuit 80.

On the other hand, at the time of reading, a memory cell at the intersection of the word line selected by the row decoder 20 and the bit line selected by the selection gate 40 is selected.
The data stored in the selected memory cell is input to the sense amplifier circuit 50 via the selected bit line and the selection gate 40, and the stored data is read out by the sense amplifier, and Output to the outside.

At the time of erasing, a predetermined word line is selected and activated by the row decoder 20 in accordance with chip batch erasing or block batch erasing. Thereby, all the memory cells or the memory cells in the selected block are selected and set to the erased state. In addition to the batch erasing, if necessary, a predetermined word line and a selection signal line are activated by the row decoder 20 and the column decoder 30 to select and erase only a predetermined memory cell. It is possible.

FIG. 2 is a flowchart showing a writing algorithm according to the present embodiment. FIG. 3 is a waveform diagram showing an example of the write pulse. FIG. 4 is a graph showing a change in the threshold voltage of the memory cell at the time of writing in the present embodiment. Hereinafter, the write operation in the present embodiment will be described with reference to FIGS. In the present embodiment, the write pulse is, as shown in FIG.
The first-time pulse width is t _0, 2~4-time pulse width is 3t _0, pulse width of from 5 th is a 30t _0. Thereafter, the pulse width is set large according to the number of times of writing. Then, by the write, threshold voltage V _th of the memory cell shown in FIG. _{4 (V TH -ΔV TH ~V TH} + ΔV
_TH ).

FIG. 2 shows a write algorithm for realizing the above-described write operation. As shown in FIG. 2, the write operation according to the present embodiment is realized by repeatedly performing the application of the write pulse and the confirmation of the threshold voltage. Note that, as described above, the width of the write pulse increases at a predetermined rate in accordance with the number of times of writing.

As shown in FIG. 2, after the start of the write operation,
First, for example, a write pulse having a pulse width t ₀ is applied, and the first write is performed. After writing, the threshold voltage of the selected memory cell is detected by the threshold detection circuit 60 shown in FIG. Here, the write target value of the threshold voltage of the selected memory cell is V _TH , the detected threshold voltage is V _th , and the preset approach range is ΔV
_{Assuming TH} , the threshold voltage V _th after writing is (V _th <
When V _TH + ΔV _TH has not been reached, the control circuit 80 shown in FIG. 1 repeats step SS1 (pulse application) and step SS2 (detection and determination of threshold voltage) in the flowchart of FIG. During this time, the width of the write pulse depends on the number of writes, for example,
t _0, is 3t _0, 30t ₀ and set large. As a result, the first pulse application time is t ₀ , and then the width 3t ₀
Is applied three times, the writing time is 10t.
It becomes ₀ . Further, if a pulse having a width of 30t ₀ is applied three times, the total writing time becomes 100t ₀ . Thus, the writing time is set to increase by one digit.

When the detected threshold voltage V _th is (V _th <V
_TH + ΔV _TH ) when the condition is satisfied, step S in FIG.
S3 is performed. That is, it is determined whether or not the detected threshold voltage V _th has reached (V _th ≦ V _TH ). When this condition is satisfied, the write operation is completed. When the condition is not satisfied, a write pulse is applied again to the selected memory cell, and writing is performed again. At this time, the rate of increase of the write pulse width to avoid excessive writing is set to a small value. Alternatively, the number of times of writing is increased so that the writing time is increased by one digit in several times, and a change in the threshold voltage of the memory cell due to each writing is set to be small.

As a result, the change in the threshold voltage of the memory cell is reduced by the application of the pulse, and the threshold voltage _Vth of the memory cell can be set to the target value _VTH or near the target value with high accuracy. 2 until the threshold voltage V _th of the selected memory cell reaches (V _th ≦ V _TH ).
Step SS3 (detection and determination of the threshold voltage _Vth ) and Step SS4 (application of a pulse) are repeated.

By the above-described write operation, the threshold voltage _Vth of the selected memory cell is set to the target value _VTH or a value near the target value _VTH . As a result, variation in the threshold voltage distribution after writing is significantly reduced, and the accuracy of writing can be improved.

FIG. 5 shows an example of the write pulse generation circuit 100 according to the present embodiment. The operation of the write pulse generation circuit is controlled by, for example, the control circuit 80 shown in FIG. 1 to generate a write pulse having a predetermined width and apply it to the selected memory cell. Note that the pulse generation circuit 100 can be incorporated in, for example, the control circuit 80 shown in FIG. Alternatively, it can be formed separately from the control circuit 80. FIG. 6 shows a configuration of a partial circuit of the pulse generation circuit 100 shown in FIG. 5, and FIG. 7 is a waveform diagram showing an operation of the partial circuit. Hereinafter, the configuration and operation of the write pulse generation circuit according to the present embodiment will be described with reference to these drawings.

As shown in FIG. 5, the pulse generation circuit 100 of the present embodiment comprises an oscillation circuit 101, pulse generation stages 102,
3 and 104, a switch control circuit 110, a plurality of nMOS transistors NT ₁ ,
NT _2, NT _3, ..., is constituted by NT _m.

The oscillation circuit 101 has a pulse width t ₀ , a period T
It generates a clock signal CLK ₀ having _zero, and supplies to the pulse generation stage 102 and the switch control circuit 110. The pulse generation stages 102, 103 and 104 generate clock signals having different pulse widths according to the input clock signal. For example, the pulse generator stage 102 generates a pulse signal having a width 3T _0, and supplied to the switch control circuit 110, or the period generates a clock signal CLK ₁ with 10 times the clock signal CLK _0, the pulse generation stage 10
Supply 3

Since the pulse generation stages 102, 103 and 104 have the same configuration, the configuration and operation of these pulse generation stages will be described using the pulse generation stage 102 as an example. As shown, the pulse generation stage 102
Is a binary counter BC ₁ and a decimal counter DC
It is composed of _one .

As shown in FIG. 6A, the binary counter BC ₁ has two stages of T-type flip-flops TFF ₁ and TFF ₁ .
It is composed of FF ₂ and NAND gates NAGT _1. The NAND of the outputs Q ₁ and Q ₂ of the flip-flops TFF ₁ and TFF ₂ is obtained by the NAND gate NAGT ₁ , and the output signal S ₁ is obtained as shown in FIG.
This is a pulse signal having a width of 3T ₀ and a period of 4T ₀ . Decimal counter DC _1, as shown in FIG. 6 (b), the 5-stage T-type flip-flop _{TFF 3, TFF 4, TFF 5} , TFF
₆ , TFF ₇ and NOR gate NRGT ₁ . The NOR gate NRGT _1, negative logical sum of the output of the flip-flop TFF ₃ ~TFF ₇ is determined, the output signal has a width T _0, the clock signal CLK ₁ cycle 10T _0.

The pulse generation stages 103 and 104 have the same configuration as 102. The pulse generation stage 103 has a width of 30T ₀ according to the clock signal CLK ₁ input from 102,
It generates a pulse signal S ₂ of the periodic 40T _0, supplies the switch control circuit 110. Further generates a clock signal CLK ₂ cycle 100T _0, and supplies the next pulse generation stage. Pulse generation stage 104 is responsive to a clock signal CLK _n-1 supplied from the previous stage, and generates a pulse signal S _n of width _{^{3 × 10 n-1 T 0}} , and supplies the switch control circuit 110.

The switch control circuit 110 includes the oscillation circuit 10
1 and the clock signal CLK ₀ and the pulse signals S ₁ , S ₂ ,.
Based on S _n , nMOS transistors NT ₁ , NT ₂ ,
A switch control signal for controlling the on / off state of the switching elements constituted by NT ₃ ,..., NT _m is generated and applied to the gate electrodes of the respective switching elements. Accordingly, each switching element is set to the conductive state at a predetermined timing, and during that time, the write voltage V _PP is output to the output terminal T _out of the write pulse. During writing, an example of the output pulse from the pulse output terminal T _out is, for example, as shown in FIG.

In the above description, the write pulse generated by the pulse generation circuit 100 is controlled so that the width increases at a predetermined rate, thereby increasing the write time by one digit. However, the present invention is not limited to this, and a method of increasing the pulse width at another ratio is also conceivable. Further, when the threshold voltage _Vth of the selected memory cell reaches a preset approaching range due to the application of the write pulse, the increase rate of the write pulse width is set to a small value. Without limitation
When the threshold voltage _Vth of the selected memory cell reaches a preset approaching range, writing is performed by holding the write pulse width at a constant value, or by gradually narrowing the write pulse width. , The threshold voltage _Vth of the memory cell after writing can be controlled with high accuracy.

[0039] Thus, since the beginning of the threshold voltage V _th is close range, but the number of writes reaches the target value V _TH or near value thereof increases, the threshold voltage V _th is reached close range By this time, the control is performed so that the write pulse width gradually increases, so that the write time until reaching the approaching range is greatly reduced, and as a whole, compared to the conventional write with the equal width write pulse, As a result, the writing time is greatly reduced.

In the above description, erasing of a memory cell is performed by injecting electrons into the floating gate by FN tunneling, and writing is performed by discharging electrons from the floating gate by FN tunneling. Is not limited to this, and it goes without saying that the principle of the present invention can be applied even when erasing is performed by emitting electrons from the floating gate of the memory cell and writing is performed by injecting electrons into the floating gate. .

As described above, according to the present embodiment, the threshold detection circuit 60 is provided on the output side of the sense amplifier 50.
Is provided, at the time of writing, a memory cell to be written is selected by the row decoder 20 and the column decoder 30 according to the address ADR, and a write pulse is applied thereto. After the pulse application, the threshold voltage of the selected memory cell is detected, and the detected value is determined by the control circuit 80 until the threshold voltage reaches a predetermined range.
The pulse width is applied while increasing at a predetermined increase rate. After the threshold voltage reaches a predetermined range, the rate of increase of the pulse width is reduced and the pulse application is repeated until the threshold voltage reaches the target value _VTH. , The writing time can be shortened, and the threshold voltage of the memory cell can be controlled with high accuracy.

[0042]

As described above, according to the nonvolatile semiconductor memory device of the present invention, the time required for writing can be greatly reduced, and the threshold voltage of the memory cell can be controlled with high accuracy.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing one embodiment of a nonvolatile semiconductor memory device according to the present invention.

FIG. 2 is a flowchart showing a writing algorithm of the present invention.

FIG. 3 is a waveform diagram showing an example of a write pulse according to the present invention.

FIG. 4 is a graph showing a change in threshold voltage of a memory cell at the time of writing.

FIG. 5 is a circuit diagram illustrating an example of a write pulse generation circuit according to the present invention.

FIG. 6 is a circuit diagram of a partial circuit of the pulse generation circuit.

FIG. 7 is a waveform chart showing an operation of a partial circuit of the pulse generation circuit.

FIG. 8 is a circuit diagram showing a part of a memory cell array constituted by nonvolatile semiconductor memory elements.

FIG. 9 is a waveform diagram of a conventional write pulse.

FIG. 10 is a graph showing a conventional change in threshold voltage at the time of writing and "overwriting".

[Explanation of symbols]

10 ... memory cell array, 20 ... row decoder, 30 ...
Column decoder, 40 selection gate, 50 sense amplifier circuit, 60 threshold detection circuit, 70 input / output circuit,
80: control circuit, 100: pulse generation circuit, 101: oscillation circuit, 102, 103, 104: pulse generation stage, 11
0 ... switch control _{circuit, NT 1, NT 2, NT} 3, ...,
NT _m ... switching device, V _PP ... write voltage, GN
D: ground potential.

Claims (5)

[Claims] 1. A nonvolatile semiconductor memory device for writing data by controlling a threshold voltage by changing a charge storage amount of a charge storage layer of a memory cell by applying a write signal, comprising: A pulse generating means for applying the write signal having a pulse width gradually increased to a selected memory cell, and a threshold voltage detection for detecting a threshold voltage of the selected memory cell after applying the write pulse signal A non-volatile semiconductor memory device comprising: a write control unit configured to reduce a rate of increase in the pulse width when a difference between the detected threshold voltage and a predetermined target value is equal to or less than a preset value. 2. The nonvolatile memory according to claim 1, wherein said pulse generation means sets the writing time by one digit longer until the threshold voltage detected by said threshold voltage detection means reaches a predetermined range. Semiconductor storage device. 3. The write control means, when the difference between the threshold voltage detected by the threshold voltage detection means and a predetermined target value reaches a predetermined value or less, sets the pulse width to a predetermined value. 2. The nonvolatile semiconductor memory device according to claim 1, wherein the value is held at a value. 4. The write control means gradually increases the pulse width when the difference between the threshold voltage detected by the threshold voltage detection means and a predetermined target value reaches a predetermined value or less. 2. The nonvolatile semiconductor memory device according to claim 1, wherein the value is set to be small. 5. The non-volatile memory according to claim 1, wherein said write control means terminates the write operation when the threshold voltage detected by said threshold voltage detection means reaches a predetermined target value or a value in the vicinity thereof. Semiconductor memory device.