JPH10177061A - Integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an integrated circuit that can shorten the time required for executing leakage tests. SOLUTION: The integrated circuit 45 has a functional network 44, a plurality of output buffers 6, which respectively have inputs coupled with the network and, at the same time, outputs respectively coupled with corresponding ones of a plurality of output pins, a plurality of mode control pins M for receiving operation mode codes, and an output disabling logic circuit 41, which have inputs coupled with the mode control pins M, generates disabling signals in response to a plurality of mode control pins M, which receive first operation mode codes, and receives second operation mode codes, which are the logical complements of the first disabling signals in response to the mode control pins. In the integrated circuit 45, the output buffers 6 respectively receive the disabling signals, which make the buffers 6 to set their corresponding signal pins to high-impedance states in response to the disabling signals.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to integrated circuit technology, and more particularly, to a leakage test of an integrated circuit.

[0002]

2. Description of the Related Art Modern integrated circuits are typically tested many times during their manufacturing process to ensure that the completed circuit meets appropriate functional and parameter specifications. . Typically, for more complex integrated circuits,
It is tested at least once in wafer form to avoid the costs associated with packaging devices that do not meet specifications. In addition, they are tested at least once in packaged form to ensure compliance with customer specifications. Additional tests may be performed at many temperatures (eg, extreme hot and cold extremes of the specified temperature range). Complex integrated circuits that undergo burning or other similar processing will be specially tested before burning. Therefore, the defective device does not occupy the burning volume, that is, the burning of another device can be performed quickly. Finally, the packaged device undergoes a special continuous test as a partial inspection of the quality of the final product. As is technically basic, the tests in each case are performed according to a pre-prepared test program, so as to apply the control voltage levels and signals required for the test and to interpret the response of the integrated circuit. This is done by automated test equipment to determine compliance with specifications.

[0003]

As mentioned above, a typical test program involves integrating an integrated circuit in terms of functionality (ie, ensuring that it will fully operate under certain cycle times and voltage conditions). , And determining that a functional device meets certain parameters, such as power consumption. Common parametric tests also include input and output leakage tests to determine that the terminals or pins of the integrated circuit are sufficiently electrically isolated from the internal nodes of the integrated circuit. Excessive leakage at integrated circuit pins causes excessive loading around the system. In addition, input and output leakage often occurs within the integrated circuit itself (eg, oxide leakage, ie, metal filaments or polysilicon) or within the package of the integrated circuit (eg, cross-connects, bond damage at bond pads on the chip). ) Indicates a manufacturing defect. A typical specification limit for leakage at individual pins is a DC between 10 μA (microamps) at a voltage between the maximum supply voltage and ground.
(DC) current. As expected, the leakage current is generally greatest at the two voltage extremes. Therefore,
Leak testing typically applies one of those voltage extremes to the pins and waits for a transient period to collapse (thus,
This is done by comparing the current into or out of the pin currently being tested against the specification limits. The test is repeated by applying the other voltage extreme to the pin.

Since most integrated circuit terminals leak only a very small amount of current in the absence of defects, conventional leakage tests apply a common voltage to many terminals and reduce the transient period before settling. This is usually done in a so-called "fire-and-fire" manner, which is performed by waiting and then measuring the current flowing through each pin, for example, where every other pin of the integrated circuit is connected to the maximum supply voltage (ie, depending on the technology). Determined from 3.6 volts to 5.5 volts), and the remaining pins are grounded.After an appropriate delay time (in units of 30 milliseconds), each pin is determined by that bias. The current is measured and compared to the test limits, since modern automated test equipment generally has a parametric measurement device for each pin of the device under test. Measurement of the individual leakage current at Les integrated circuit pins, are performed in parallel. Thereafter, the test is
This is repeated with a reverse bias structure. Especially in the case of integrated circuits such as microprocessors having a very large number of pins (hundreds of hundreds), moreover, leakage failures occur less frequently in modern integrated circuits, The shooting leak test saves a lot of testing time by eliminating the repetition of waiting and measurement intervals.

In a leak test of a pin related to an output terminal,
Of course, the output buffers or drive networks connected to them need to be disabled and placed in a high impedance state. The disabling and enabling of the output buffer circuitry is controlled by the internal functions of the integrated circuit, typically similar to modern microprocessors. Alternatively, it may alternatively be controlled by an external signal applied to the output enable pin. In either case, disabling the output buffer represents the complexity of leak testing integrated circuits, as described in connection with FIG.

In FIG. 1, a conventional integrated circuit 2 has a functional network 4 which is a complicated logic network such as a central part of a microprocessor. The function circuit 4 includes pins P0 to Pn
, An exchange of giving data to an external device or obtaining data from the external device is performed. In this example, pins P0, P1, and Pn are output pins, and pin P2 is a common input / output pin. Of course, dedicated input pins are also included in typical conventional integrated circuits, and a similar leak test is performed simultaneously with the output and I / O. P
Each pin from 0 of Pn are driven from the corresponding output buffer 6 ₀ by the output of 6n. Each buffer has an input for receiving a data signal from a functional circuit on the corresponding data line D0 to Dn. Common I / O pin is P
In case 2, the input buffer 72 has an input connected to pin P2 and an output driving the data on line DI2 to the functional circuit 4.

In this example, the output buffer 6₀From 6n
Each responds to an external signal on output enable pin OE
Enabled and disabled. Some conventional VL
In the SI logic circuit, the output buffer 6
A number of output enable pins OE (or
Internal signal). Input buffer 5 output enabled
Receives pin OE and in response drives line EN,
Associated output buffer 6 ₀To each of 6n
You. Output buffer 6₀Is shown in detail in FIG.
I have. In this example, the output buffer 6₀Is a push-pull
Type. In addition, it is an n-channel pull-up
Transistor 9PU and n-channel pull-down
It has a transistor 9PD. The transistor 9PU
The source / drain path is a power supply node (for example, Vdd)
And the pin P0. In addition, transistors
The source / drain path of 9PD is connected between pin P0 and ground.
Has been continued. Each of the transistors 9 is relatively large
For a particular output load condition on pin P0.
To provide the appropriate output drive. Pull Up Transis
The data gate is driven by the AND function 8H. one
On the other hand, the gate of the pull-down transistor
Driven by 8L. AND gates 8H and 8L
Is the line EN and data at their inputs, respectively.
Receive line D0. AND gate 8L drives to the "high" state.
Of the activated line EN and the data line D0 in the "low" state.
In response to the combination, drive its output to a "high" state.
To turn on the transistor 9PD. On the other hand, AND machine
No. 8H is connected to line EN and data line D at a high logic level.
In response to both zeros, drive its output to a "high" state.
Then, the transistor 9PU is turned on. Therefore, out
Force buffer 6₀Is a pin as long as line EN is in the "high" state.
P0 is driven to the state of the data line D0. Conversely, the line EN
If it is "low" (ie, pin OE is "low"),
Transistors 9PU and 9PD are both non-conductive and
Put P0 in a "high" impedance state. Output buffer
A6₁, 6_Two, 6n are the output buffers 6 shown in FIG.₀
The configuration is the same as

[0008] Three passes are required to perform a leak test on all pins of the conventional integrated circuit 2. First, the output enable pin OE is driven "low" state, all the output buffer 6 ₀ 6n is disabled, Pn are placed in a high impedance state from their pin P0. Thereafter, preferably by biasing every other pin to the Vdd supply voltage and the remaining pins to the first ground to ensure that any pin-to-pin leakage is measured, A “fire” leak test is performed. For example, in the first simultaneous leak test, the pins P0, P2
This is done by biasing even numbered pins such as Vdd at Vdd, and grounding odd numbered pins such as pin P1 to bias all output enable pins OE to a "low" state. Required settling time (for example, 30 ms)
After that, the current flowing through each of the pins that are biased to a “high” state and the current flowing through each of the pins that are biased to a “low” state are separately (preferably,
Measured (in parallel with each other) and compared to the test limits. Thereafter, a second pass simultaneous test is performed. Output enable pin OE is kept "low" state, the output buffer 6 ₀ 6
_2. Disable all 6n. However, the bias of each of the pins being tested is reversed (ie, pins P0, P2, etc. are grounded, pins P1 etc. are at Vd
d). Thereafter, the waiting time and the current measurement are repeated for this state.

However, in the conventional apparatus, when the output enable pin must be held low is biased to a high voltage in order to disable the 6n from the output buffer 6 _0, output enable pin OE was not tested. Therefore, to perform a complete leak test, 30
Separate leak testing of the high voltage (Vdd) biased output enable pin OE, including the settling time in milliseconds, had to be performed separately. Thus, leak testing of such and similar conventional integrated circuits requires three passes.

As noted above, certain types of conventional integrated circuits include a bank of pins, each bank being under the control of a separate output enable signal, typically generated by internal logic functions. . Leak testing of output pins arranged in such a bank requires several pairs of passes. Each pair of paths corresponding to one bank of the output buffer is disabled at one time. Furthermore, the execution of the instructions required to disable one or more banks of output buffers is relatively cumbersome, and in addition to the latency required to settle the transients during the leak test itself, such a priori is required. Requires extra test time for processing.

In particular, as integrated circuits become more complex and automated test equipment becomes more expensive, especially in the testing of increasingly faster integrated circuits, the cost per test time increases. continuing. Therefore, it is desirable to reduce the time required to test each integrated circuit without sacrificing the accuracy or completeness of the test program. Accordingly, it is an object of the present invention to provide an integrated circuit in which the time required to perform a leak test is reduced. Another object of the present invention is to provide a method for performing such a leak test. It is yet another object of the present invention to provide an integrated circuit and method that can fully perform a leak test on all device pins.

[0012]

SUMMARY OF THE INVENTION The present invention comprises providing a plurality of mode control pins for receiving at least two complementary codes that disable an output buffer.
It is implemented in an integrated circuit such as a microprocessor. Mode control pins are already provided for controlling the operating mode of the integrated circuit. Here, at least two modes are used to disable the output buffer. The leak test is performed by setting the mode control pin to a first disabled state while setting the signal pin to the first state. After the waiting time has elapsed, the leakage current into and out of the pin under test, including the mode control pin, is measured and compared to a limit value. The leak test then places the mode control pin in the second complementary disable state while setting the signal pin in the second complementary bias state and waits for a specific settling time,
The process is then completed by measuring the leakage current from the pin under test, again including the mode control pins. Since each of the mode control pins is tested at each bias level in the two passes, the leak test is terminated after the two passes.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIG. FIG. 2 shows an exemplary integrated circuit 25 according to a first preferred embodiment of the present invention. Here, only one example of the structure of the integrated circuit is shown, but it is clear that the present invention can be used as it is for various types of integrated circuits such as microprocessors of various structures. Thus, the present invention is directed to silicon substrates, silicon on insulators, gallium arsenide, and other manufacturing technologies, as well as MOS, CMOS, BiC
Implemented in integrated circuits made using MOS, or other device configurations.

As shown in FIG. 2, the integrated circuit 25
It has a functional circuit 24, and the functional circuit may be of any type as long as it can appropriately communicate digital or analog information with an external device or subsystem. The present invention relates to a VLSI such as a modern microprocessor containing hundreds of external terminals or pins.
Particularly effective when used in connection with a logic device.
In the following description, the external terminals of the integrated circuit 25 will be referred to as “pins”. Of course, the present invention provides that the external terminals are integrated circuit chips themselves (i.e., leak testing of integrated circuits in wafer form), e.g.
Package pins used in in-line and single-in-line packages, leads as used in J-shaped leads and tape carrier packages, such as lands used in surface mount chip carrier packages, and various alternatives The present invention can also be applied to a leak test of an integrated circuit coupled to another type of terminal mounted in a package form.

In the exemplary integrated circuit 25 of FIG. 2, signal pins P0, P1, and Pn are shown by way of example. In this example, the signal pin P0 is a common input / output pin, while the pins P1 and Pn are output pins. Each signal pin P0, P1, and Pn, are driven by a corresponding output buffer 6 _0, 6 _1, 6n. Each of these output buffers has an input coupled to a corresponding data signal line D0, D1, Dn from functional circuit 24. Input buffer 7 _0, common input and output states of pins P0 receives, coupled to the functional circuit 24 signal lines DI0
Drive. Each of output buffers 6 ₀ , 6 ₁ , 6n (and others, not shown) is enabled by a line EN at a high logic level and a line E at a low logic level.
Controlled by line EN, as disabled by N. From the output buffer 6 ₀ 6n may be constructed in accordance with conventional design simple such as a push-pull drive circuit which is described above in connection with FIG. Alternatively, output buffer 6
₀ to 6n can be configured in an open drain drive circuit, a single-ended drive circuit with an active pull-up circuit, or the like, or other conventional methods. In another alternative, a bidirectional transceiver is provided within integrated circuit 25.
In that example, output buffers 6 would be placed in their transceivers and enabled by an output enable signal combined with a directional control signal. In either case, 6n from the output buffer 6 ₀ according to an embodiment of the present invention, the line EN, eg selectively configured to be in a high impedance state by the gate line EN. Thus, each drive transistor becomes non-conductive in response to line EN being at the disabled level (low logic level in this example).

According to the embodiment of the invention shown in FIG.
Integrated circuit 25 has multi-mode control pins M3 to M0. The mode control pins M3 to M0 respectively receive a mode control signal externally applied to the integrated circuit 25,
These mode control signals are supplied to the input buffers 15 ₃ to 15
Give to ₀ . Each output of the input buffer 15 ₃ to 15 _0, in order to control the operation of the integrated circuit 25 in various modes, and sent on to the functional circuit 24. Examples of operating modes in which the integrated circuit 25 operates include one or more normal operating modes and one or more special test modes, such as a scan test of the functional circuit 24, for example. In this example of the invention, four mode control pins M3 to M0 are provided, so that sixteen operating modes are available.
In this example, four mode control pins M3 to M0 are shown; however, more or less mode control pins can be provided depending on the desired number of modes to be used. In fact, as described, two of the 16 available modes are actually in control of the output disable logic 21, such as described in accordance with embodiments of the present invention, from the output buffer 6 ₀ 6n Assigned to disabling.

[0017] The output of the input buffer 15 ₃ 15 _0,
AND function 20 ₀ Output disable logic circuit 21 of integrated circuit 25 is supplied to 20 of the _input. AND function 2
0 _0, 20 ₁ is configured to provide an output of the high logic level for complementary states given from the mode control pin M3 to M0. In this example, the AND function 20 _0, in response to a combination of mode control pin M1 undergoing respectively a high logic level of the mode control pins M3, M2, M0 receiving a low logic level, providing an active output (i.e.,
0010 mode control code). On the other hand, AND function 20
₁ is the mode control pins M3, M that receive a high logic level
2, an active output is provided in response to a combination of each of M0 and a mode control pin M1 receiving a low logic level (ie, a mode control code of 1101).

The output disabling logic circuit 21 also has an AND
Function 20 _0, NOR having an input for receiving the 20 _first output
Function 22 is included. The input buffer 5 receives the state of the output enable pin OE and adds this state to the third input of the NOR function 22. This connection when the integrated circuit 25 is in normal operation (i.e., in this example, when M0 from the mode control pin M3 receives a code other than 0010 or 1101), disabling and enabling of 6n from the output buffer 6 ₀ Can be controlled by the output enable pin OE. NOR function 22 drives line EN at its output. Further, the NOR function, in combination with the output enable pin OE high level, without answering to either the AND function 20 _0, 20 ₁ to drive a high logic level,
Line EN is configured to be at a high logic level. In other words, the line EN is at the low level of the output enable pins OE,
Or in response to any one of mode control pin M3 which is consistent with any of the case of assert its output to one of the AND function 20 _0, 20 ₁ combination of logic levels of M0, of the NOR function 22 Driven to low level.

According to the configuration of the integrated circuit 25 as shown in FIG. 2, 2 is applied to the mode control pins M3 to M0.
One bit per complementary code, regardless of the state of the output enable pin OE, it is operable to disable the 6n from the output buffer 6 _0. This is because the output enable pin OE is both high and low bias at pins P0 through P0.
It is possible to receive simultaneous leak detection together with n.
Further, since the two disabling combinations of mode control pins M3 to M0 are logically complementary to each other, a sufficient and complete leak test of mode control pins M3 to M0 can be performed on signal pins P0 to Pn and output pins. It can be performed simultaneously with the OE pin in a simultaneous manner. The operation of the integrated circuit 25 for performing a leak test according to the preferred embodiment of the present invention will be described with reference to FIG.

The sequence of the leak test depicted in FIG. 3 is automated as part of a full test program for testing integrated circuit 25, useful in any one or all of several manufacturing and qualification tests. It is performed by a test apparatus. An exemplary program is that each pin is connected to a network in the integrated circuit 25 (ie, all connections are connected).
Starting with a simple continuity test to ascertain the actual operation and boundary scan test of the integrated circuit 25 to the extent desired, such as the leak test of FIG. Perform rigorous functional tests, including:

Referring to FIG. The leak test according to the preferred embodiment of the present invention, after some preliminary tests,
0, in which process a first disabling code is applied to the mode control pins M3 to M0. For example, refer to FIG. The first disabling code is AND function 20
₀ drives its output to a high level, to the line EN drives the NOR function 22 to a low level, so as to inoperable to 6n from the output buffer 6 _0, the response from the pin M3 code 0010 on M0 I do. The first disabling code is preferably applied to the mode control pins M3 to M0, the mode control pins M3, M2, M0 are fully grounded, and the mode control pin M1 is fully Vdd (preferably its maximum specified). Voltage). As a result, a leak test may be performed simultaneously on the mode control pins M3 to M0 in operation 32.

[0022] from the output buffer 6 _0, which is inoperable 6
n, then operation 32 is performed, and the first of the leak tests is performed.
Make a pass. In process 32, each of the signal pins P0 to Pn and the output enable pin OE are biased to one of the extremes of the specified voltage, as are the other pins (not shown) on which the leak test is performed. For example, all pins tested may be biased to ground, and all pins may be biased to the maximum supply voltage. Alternatively, some
Others may be biased to ground and others to a maximum supply voltage. A preferred method is to test for leakage between adjacent pins by alternately biasing the pins to ground and the maximum power supply voltage Vdd. As mentioned above, the mode control pins M3 to M0 are already biased to a suitable voltage extremum associated with the first disabling code (0010 in this example). Thereafter, the selected bias condition (state 1 in FIG. 3) is changed for a predetermined waiting period (for example, 3).
0 msec) and settles the transient. After the waiting period, for both the high biased and ground biased pins,
The current drawn by each pin under test is measured. This current measurement is performed not only on all signal pins P0 to Pn, but also on output enable pin OE and mode control pins M3 to M0.

As described above, recent automated test equipment is
Typically, it has a parametric measurement unit for each pin of the device. Thus, the current measurement performed in process 32 measures the individual leakage currents at all pins of the device simultaneously and in parallel, in a favorable manner. Such a parallel measurement of leakage current not only ensures proper leakage testing with a pin-by-pin bias, but also efficiently performs leakage current measurements on all pins at once. Alternatively, the leakage current can be measured collectively for many pins, especially if the automated test equipment does not include a parametric measurement unit for each device pin. This is done, for example, by measuring the collective leakage current drawn by all pins biased high and measuring the collective leakage current generated at all pins biased low.

In a preferred embodiment of the present invention, the decision 3
At 3, it is determined whether any of the measured leakage currents exceeds an appropriate specification limit for that pin.
As mentioned above, this typical limit value is in the order of 10 μA. If any of the measured leakage currents exceed the appropriate specification limits for that pin (i.e., NO determination), the integrated circuit 2 to be tested
5 will be dropped from the test program and discarded. If none of the measured leakage currents exceeds the appropriate specification limit for that pin (i.e., YES), there is no excessive leakage at one pin and control returns to step 36. Move on.

In operation 36 according to the preferred embodiment of the present invention, mode control pins M3 through M0 are set to a second disabling code that is complementary to the disabling code of operation 30. In this example, the mode control pins M3 to M0 are:
The code of 1101 is received. Again, as in process 30,
The bias on the mode control pins M3 to M0 having the second code is set to the specification limit. That is, the mode control pins M3, M2, and M0 are set to the maximum power supply voltage value Vdd, and the mode control pin M1 is grounded, and a leak test of the mode control pins M3 to M0 is performed in the complementary bias state.

Thereafter, a process 38 is executed to perform a second simultaneous leak test. In the process 38, the signal pins P0 to Pn
Respectively, the output enable pin OE, and the other pins that are preferably tested for leakage, are determined from their values by the reverse voltage extremes of the values at which these pins were biased in process 32 (FIG.
State 2). This reverse bias causes each pin to be tested for leakage at both high and low voltages (ie, leakage to ground and leakage to Vdd, respectively). Again, after a latency of the order of 30 milliseconds, the leakage current flowing in each of those pins is measured in a manner similar to that described for process 32. The current measurement in process 38 is performed on all signal pins P0 to Pn, output enable pin OE, and mode control pins M3 to M0. In decision 39, each of the measured leakage currents is compared to an appropriate pin limit. If any of the measured leakage currents exceed the test limit (i.e., decision 39 is NO), the integrated circuit 25 being tested does not meet specifications and will be discarded. Become. If none of the measured leakage currents exceeds its test limit (ie, decision 39 is YES), there is no excessive leakage at one pin and the leakage test of integrated circuit 25 is completed. . Thereafter, control passes to the next test in the special test program.

According to this embodiment of the [0027] present invention, the output enable pin OE from the output buffer 6 ₀ in the integrated circuit 25 6
n is a voltage that enables normal operation (high level in this example)
The leak is tested at both voltage extremes, including The leak test of the output enable pin OE is performed simultaneously with the leak test of the signal pins P0 to Pn. Furthermore, by disabling code M0 from the mode control pin M3 causes the inoperative to 6n from the output buffer 6 _0, mode control pins M3
To M0 also at both voltage extremes,
The leak is tested simultaneously with the signal pins P0 to Pn and the output enable pin OE. Thus, as a result of the preferred embodiment of the present invention, no extra pass of the leak test is required to completely complete the specific leak test required.
Thus, the time required for such additional passes, including the required latency, is eliminated from the test program.

Referring to FIG. A configuration of an integrated circuit 45 according to an alternative embodiment of the present invention will be described. Components of the integrated circuit 45 shown in FIG. 4 that are the same as components of the integrated circuit 25 of FIG. 2 are referred to by the same reference numerals. The integrated circuit 45 includes a functional circuit 44 in this example. This functional circuit 44 is a functional circuit 24 in the integrated circuit 25 described above.
Any type of functional circuit may be used, as long as it can perform digital or analog communication with external devices or subsystems.

However, in integrated circuit 45, the pins or terminals are grouped or banked into groups that are separately enabled or disabled in response to signals generated by functional circuit 44. Are arranged. As shown in FIG. 4, pins P0, P1
Is there in one bank, the output enable line is caused to allow and inoperable operation by enabling and disabling signal on ENa, and a corresponding output buffer 6 _0, 6 _1. Pins P2, P3 are be in a second bank have respectively controlled by enabling and disabling signal on another of the output enable line ENb, the output buffer 6 _2, 6 ₃ corresponding . Although two pins are shown in FIG. 4 in association with each bank, each bank can of course include a large number of pins, for example, 64 to 72 pins per bank. The enabling lines ENa, ENb are:
Generated by output disable logic 41 in response to an output enable signal on lines OEa, OEb generated by internal functions within function circuit 44, for example, generated in response to execution of certain program commands. You.

Output disabling according to the second embodiment of the present invention
The logic circuit 41 includes the input buffer 15 _ThreeFrom 15₀Through
And are coupled to mode control pins M3 to M0. Collection
As in the integrated circuit 25, the input buffer 15_ThreeFrom 1
5₀Each have their associated mode control pin M_ThreeFrom
M₀Receives one bit of the external mode control code, and
The desired operating mode in response to that bit.
To the functional network 44 to perform. Input buffer 15_ThreeFrom 1
5₀Mode control pin M at the output of _ThreeTo M₀State
Also, the AND in the output disable logic 41 of the integrated circuit 45
Function 20₀, 20₁Sent to Similarly, the integrated circuit 25
As in the case of the output disabling logic 21 in FIG.
No. 20₀, 20₁Is the mode control pin M_ThreeTo M₀Received at
High logic level for transmitted complementary mode control code
Is configured to give In this example, the integrated circuit 25
As in AND function 20₀Is the mode of 0010
An active output is provided in response to the control code. On the other hand, AND
Function 20₁Is the mode control pin M_ThreeTo M₀11 in
An active output is provided in response to the mode control code of 01.

However, according to the second embodiment of the present invention,
Output disable logic 41 also has two NOR functions 42a,
42b. Each of those NOR functions is A
Having ND function 20 _0, 20 ₁ of input connected to the output. In addition, NOR function 42a has an input for receiving an output enable signal on line OEa from functional circuitry 44. On the other hand, NOR function 42b has an input for receiving an output enable signal on line OEb from functional network 44. In this example, NOR function 42a in response to one of the signal lines OEa from AND function 20 _0, 20 ₁ of the output or function circuitry 44 is low level, a high level, a line ENa low level driven in, causing the output buffer 6 _0, 6 ₁ inoperable. On the other hand, the NOR function 42
b drives line ENb low in response to either the output of AND function 20 ₀ , 20 ₁ being high or signal line OEb from functional network 44 being low, and the output buffer 6 ₂ and 6 ₃ are disabled. Therefore, normal operation (ie, 0010 or 110
In a mode control code other than 1), the functional network 44
Output buffer 6 _0, 6 ₁ and 6 _2, 6 ₃ of the bank can be separately inoperable possible and operation.

The mode control pin M3 of this embodiment of the present invention
M0 is, the AND function 20 _0, 20 ₁ and NOA function 42a, the operation of 42b, acts as a master output disable control pin from. Mode control pins M3 to M0
At the complementary disabling code (in this example, 0010, 110
When any of the above 1) is received, the NOR functions 42a and 42b
Drive their corresponding output lines ENa, ENb low, and output lines OEa, OE from functional network 44.
b, regardless of the state of the output enable signal on
Disables all of the output buffers 60 to 63 within. This arrangement allows simultaneous leakage testing at high and low bias for all signal pins P tested without requiring cumbersome pre-processing of output buffer 6 by operation of functional circuit 44. Accordingly, the leak test method described in connection with FIG. 3 may be provided to an integrated circuit 45 according to this second embodiment of the present invention.

As in the embodiment of the invention described with reference to FIG. 2, the complementary nature of the two disabling combinations of mode control pins M3 to M0 is similar to that of signal pins P0 to P6.
At the same time, it enables a full and complete simultaneous leak test of the mode control pins M3 to M0. Thus, all output buffers 6 can pass one of the two complementary disabling codes from mode control pin M0 without requiring cumbersome pre-processing of output buffer 6 by executing a series of commands, such as by functional circuit 44. Disabled by applying to M3. Thus, in each of the preferred embodiments of the present invention, an integrated leak test can be efficiently performed on all signal and mode control pins, and, if present, any output enable pins of the integrated circuit. A circuit is provided. This efficiency is due to the elimination of additional leakage test paths applied to the pins used in disabling the output buffer, especially when the mode control pins are used to disable the output buffer. , Will be bigger. As described above, the present invention and the preferred embodiments have been described. However, the present invention is not limited to the embodiments, and improvements in the embodiments that achieve the effects of the present invention are included in the protection scope of the present invention. Things.

With respect to the above description, the following items are further disclosed. 1. A functional network, a plurality of output buffers each having an input coupled to the functional network and having an output coupled to an associated one of the plurality of output pins, and an operating mode code. A plurality of mode control pins for receiving a first operating mode code, the mode control pins having an input coupled to the mode control pins for receiving the first operating mode code; Output disabling logic for receiving a second operating mode code which is a logical complement of the first disabling code in response to a mode control pin of An integrated circuit, wherein a plurality of output buffers receive the disabling signal that places their associated signal pins in a high impedance state in response to the disabling signal. 2. The integrated circuit of claim 1, further comprising an output enable pin coupled to another input of said output disable logic for receiving an output disable signal, said output disable logic also comprising: An integrated circuit for generating a disable signal in response to an output enable pin receiving an output disable signal. 3. 2. The integrated circuit of claim 1, wherein said output disable logic also has an input coupled to a functional network;
An integrated circuit for receiving a first output disabling signal and wherein the output disabling logic circuit also generates a disabling signal in response to receiving the first output disabling signal. 4. 4. The integrated circuit of claim 3, wherein said output disable logic also has an input coupled to a functional network,
Upon receiving a second output disabling signal, the output disabling logic generates a disabling signal for a first bank of the plurality of output buffers in response to receiving the first output disabling signal. The output disabling logic circuit may be configured to respond to the reception of the second output disabling signal in response to receiving the second output disabling signal.
Generating a disabling signal for the bank; further, the output disabling logic circuit also includes a plurality of mode control pins responsive to receiving a first or second operating mode code. An integrated circuit for generating a disable signal for output buffer first and second banks. 5. The integrated circuit of claim 1, wherein said mode control pin is also coupled to a functional network to provide an operating mode code thereto. 6. 2. The integrated circuit of claim 1, further comprising a plurality of mode control input buffers, each having an input coupled to one of the plurality of mode control pins, and coupled to the output disable logic circuit. An integrated circuit having a modified output. 7. The integrated circuit of claim 1, further comprising an input buffer having an input coupled to said output enable pin and an output coupled to said output disable logic. 8. 2. The integrated circuit of claim 1, further comprising at least one input buffer having an input coupled to one of the signal pins and an output coupled to the functional network. 9. 2. The integrated circuit of claim 1 wherein said output disable logic is coupled to a plurality of mode control pins for generating a disable signal in response to a mode control pin receiving a first operating mode code. A first AND logic function coupled to the control input of the output buffer; and a plurality of mode control pins for generating the disable signal in response to the mode control pin receiving the second operation mode code. And a second AND logic function coupled to the control input of the output buffer. Ten. 10. The integrated circuit according to claim 9, wherein said output disabling logic circuit further comprises an output responsive to a mode control pin receiving either the first or second operation mode code or receiving an output disable signal. Having an input coupled to the outputs of the first and second AND logic functions, generating an disable signal in response to the enable pin, having an input coupled to the output enable pin; An integrated circuit having an OR logic function having an output coupled to a control input of an output buffer. 11． An integrated circuit 45 capable of efficiently testing for leakage at external terminals is disclosed. The integrated circuit 45 is enabled and disabled according to the state of the signal EN generated by the output disable logic 41.
Has a signal pin P driven. The mode control pins M receive two operating mode codes that are complementary to each other but each serve to render the output buffer 6 inoperable. Output enable pin OE is also coupled to output disable logic 41 to disable the output buffer in normal operation. Instead, the output enable signal OE
a, OEb are generated by a functional network 44 for controlling the banks of the output buffer 6. Thereafter, one of the output disable codes is applied to the mode control pin M to bias the signal pin P and the output enable pin OE to the first state, and waits for a transitional period until the setting, and thereafter, A leak test is performed by comparing the pin current to specification limits. The leakage at other voltage conditions is tested by applying a complementary output disable code to control pin M and repeating it. Since the mode control pin M and the output enable pin OE are tested together with the signal pin P, ensuring that all output buffers 6 are disabled, there is no need to perform a third leakage stage. .

[Brief description of the drawings]

FIG. 1 is an electric circuit diagram schematically showing a part of an output circuit in a conventional integrated circuit.

FIG. 2 is an electric circuit diagram schematically showing a part of an output network in the integrated circuit according to the first preferred embodiment of the present invention;

FIG. 3 is a flowchart illustrating an operation of a leakage method according to a preferred embodiment of the present invention.

FIG. 4 is an electric circuit diagram schematically showing a part of an output network in an integrated circuit according to a second preferred embodiment of the present invention.

[Description of Signs] 6 Output buffer 41 Output disable logic 44 Functional circuit network 45 Integrated circuit

Claims (1)

[Claims] A functional network and a plurality of output buffers each having an input coupled to the functional network and having an output coupled to an associated one of the plurality of output pins. A mode control pin for receiving an operation mode code; and an input coupled to the mode control pin, wherein the disable signal is provided in response to the plurality of mode control pins for receiving the first operation mode code. An output disabling logic circuit for receiving, in response to a plurality of mode control pins, a second operating mode code that is a logical complement of the first disabling code, the output buffer comprising: Wherein each of the plurality of output buffers receives the disabling signal in response to the disabling signal, the output buffers placing their associated signal pins in a high impedance state.