JPH10173534A - Delta-sigma modulation circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a delta-sigma modulation circuit of a small scale which has a high S/N and can prevent increase of the number of quantizers. SOLUTION: A 1st subtracter 100 calculates the difference between an analog input signal αX and a feedback signal FB which is multiplied by α (>1) by an amplifier 107 and supplied from a feedback delay unit 106. The output of the subtracter 100 is inputted to a 1st integrator 101. Then the output of a 2nd subtracter 103 which calculates the difference between the output of the integrator 101 attenuated down to 1/α by an attenuator 102 and the output of the unit 106 is inputted to a 2nd integrator 104. The output of the integrator 104 is quantized by a quantizer 105, delayed by the unit 106 by a single sample period, converted into the analog signals and fed back to the subtracters 100 and 103. At the same time, the output of the quantizer 105 is extracted as a digital output signal Y.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delta-sigma modulation circuit in an analog / digital converter used for digital AV equipment and the like.

[0002]

2. Description of the Related Art As a conventional delta-sigma modulation circuit,
For example, IEICE Technical Report CS83-198, 8
3 [307] (1984-3-23) P. 93-100
There is one described in.

FIG. 4 is a block diagram showing a configuration of a conventional double integral type delta-sigma modulation circuit. In FIG. 4, 400 is a first subtractor, 401 is a first integrator, 4
02 is a second subtractor, 403 is a second integrator, 404 is a quantizer, and 405 is a delay unit.

The analog input signal X is supplied to a first subtractor 400
The difference from the feedback signal FB is calculated by the first integrator 4
01 is integrated. The output of the first integrator 401 is obtained as a difference from the feedback signal FB by the second subtractor 402, and is integrated by the second integrator 403. The output of the second integrator 403 is quantized by a quantizer 404, and the digital output signal Y from the quantizer 404 is converted into an analog feedback signal FB by a delay unit 405. 2 is negatively fed back to the subtractor 402.

The transfer characteristic of the delta-sigma modulation circuit of the double integral type shown in FIG. 4 is obtained by using a Z-transformation display to generate an input signal as X (Z), an output signal as Y (Z), and a quantizer 404. Let Q (Z) be the quantization noise

[0006]

(Equation 1)

[0007] Here, (1-Z ^-1 ) ^-1 means integration, and Z ^-1 means unit delay (one sample delay). Solving (Equation 1) gives

[0008]

(Equation 2)

## EQU1 ##

From equation (2), the signal component of the output signal Y (Z) matches the input signal X (Z), and a flat characteristic is obtained within the signal band.

An output of the quantizer 404 is a signal Y obtained by removing a high-frequency noise component by a digital low-pass filter connected to a subsequent stage (not shown) and quantizing the analog input signal X.
Becomes

[0012] However, the double integral type delta
In the sigma modulation circuit, the integrated voltage of the first integrator 401 is required to be about 1 to 2 times the analog input signal X, and the integrated voltage of the second integrator 403 is required to be about 2 to 4 times.
Therefore, it is necessary to relatively decrease the amplitude of the analog input signal X. However, the amplitude of the analog input signal X tends to be affected by internal noise, and the signal-to-noise ratio (S / N) characteristics of the entire circuit deteriorate. There was a point.

In order to solve the above-mentioned problem, a delta-sigma modulation circuit capable of expanding an amplitude of an analog input signal by suppressing an integrated voltage of a second integrator and improving an S / N characteristic. Has been proposed (for example,
-97749). Such a double integral type delta-sigma modulation circuit will be described below.

FIG. 6 is a block diagram showing a configuration of a delta-sigma modulation circuit in which the S / N characteristic is improved by suppressing the integration voltage of the second integrator. In FIG. 6, 600
Is a first subtractor, 601 is a first integrator, and 602 is a first integrator.
, 603 is a second subtractor, 604 is a second integrator, 605 and 606 are first and second quantizers, respectively.
607 is an adder, 608 is an amplifier, and 609 is a second delay unit.

The first subtractor 600 calculates the difference between the analog input signal X of this circuit and the feedback signal FB output from the feedback second delay unit 609, and converts the difference signal into a first integrator 601. Give to. The first integrated signal output from the first integrator 601 is input to the first delay unit 602 and also to the first quantizer 605 at the same time. The first integrated signal input to the first quantizer 605 becomes a binary quantized signal OS11 whose polarity is determined and quantized, and is input to the adder 607. On the other hand, the first integrated signal input to the first delay unit 602 is delayed and output, and then input to the second subtractor 603 together with the feedback signal FB from the second delay unit 609. These two signals become signals that have been subtracted by the second subtractor 603, and pass through the second integrator 604 to become a second integrated signal. The second integrated signal is input to a second quantizer 606, the polarity of which is determined and the quantized binary quantized signal OS12
And input to the adder 607.

Further, an adder 607 outputs an added signal of the binary output quantized signal OS11 of the first quantizer 605 and the binary output quantized signal OS12 of the second quantizer 606. . This addition signal is supplied to the amplifier 60 for correction.
Through 8, a three-valued digital output signal Y is obtained.

The output signal Y is supplied to a second delay unit 6 for feedback.
09 to generate a feedback signal FB, which is supplied to the first and second subtracters 600 and 603, respectively.

In the above circuit configuration, the transfer characteristics of the delta-sigma modulation circuit are as follows: the input signal is X (Z), the output signal is Y (Z), the first quantizer 605 Output signal and quantization noise are Y1 (Z),
Assuming that Q1 (Z), the output signal of the second quantizer 606, and the quantization noise are Y2 (Z) and Q2 (Z), respectively.

[0019]

(Equation 3)

[0020]

(Equation 4)

[0021]

(Equation 5)

## EQU1 ## here,

[0023]

(Equation 6)

By solving Equations (3) to (6),

[0025]

(Equation 7)

## EQU1 ## (Equation 7) is

[0027]

(Equation 8)

In other words,

[0029]

(Equation 9)

## EQU2 ## Here, the correction amplifier 608 is used.
If the gain of G is 0.5, for example, F (Z) becomes

[0031]

(Equation 10)

[Mathematical formula 9]

[0033]

[Equation 11]

## EQU1 ##

According to (Equation 7) and (Equation 11), when the input signal X (Z) is converted into the quantized output signal Y (Z), the transfer function corresponding to the coefficient of X (Z) is obtained. Is F (Z), and indicates that the product of X (Z) multiplied by the filter characteristic indicated by F (Z) is Y (Z). In the transfer characteristic of the delta-sigma modulation circuit of FIG. 4 shown in (Equation 2), the signal component of Y (Z) matches X (Z), but the transfer function shown in (Equation 7) Does not match. However, if the transfer function F (Z) shown in (Expression 10) approximates a flat characteristic within a required signal band, Y
The in-band signal component of (Z) is approximated to X (Z) and Y
The A / D-converted signal is obtained by removing the out-of-band noise component (Z) by a digital low-pass filter (not shown) at the subsequent stage.

According to a computer simulation in Japanese Patent Publication No. Hei 7-97749, the input level of the conventional delta-sigma modulation circuit shown in FIG.
In the range of 10 dB, the second integrated signal voltage is about three times the input signal voltage, and the voltage of the input signal is relatively limited to about one third of the internal operating voltage. Therefore, in a practical circuit, it becomes a factor of deteriorating the S / N characteristics due to the influence of internal noise.

On the other hand, in the delta-sigma modulation circuit shown in FIG. 6, the output of the first quantizer 605 and the output of the second quantizer 606 are added and corrected, and the ternary output signal Y
, The internal operation voltage is set to be one time the voltage of the input signal X, and the level of the input signal X can be relatively increased.
/ N characteristics can be improved.

[0038]

However, in the conventional delta-sigma modulation circuit shown in FIG. 6, the number of relatively large-scale quantizers in a practical circuit is doubled. was there.

The present invention has been made in view of the above problems, and provides a delta-sigma modulation circuit which has good S / N characteristics, does not increase the number of quantizers, and does not increase the circuit scale. It is intended for.

[0040]

In order to achieve the above object, a delta-sigma modulation circuit according to the present invention comprises: an amplifier for amplifying an output signal of a feedback delay unit by a predetermined magnification α;
A first subtractor for subtracting an output signal of the amplifier from an analog input signal, a first integrator for integrating an output of the first subtractor, and an output of the first integrator reduced to 1 / α. An attenuator that attenuates, a second subtractor that subtracts an output signal of the delay device from an output of the attenuator, a second integrator that integrates an output of the second subtractor, A quantizer for quantizing the output of the integrator; and the delay unit for delaying the output of the quantizer for one sample period and converting the output to an analog signal, and extracting a digital output signal from the quantizer. It is characterized by having such a configuration.

The amplifier, the first subtractor, and the first integrator are connected to an input terminal of an analog input signal, the first resistor having a resistance value of R, and an inverting output terminal of a delay unit. A second resistor having a resistance value of R / α, a first inverting amplifier, and a first capacitor having a capacitance value C connected between input and output terminals of the first inverting amplifier. Wherein the attenuator, the second subtractor, and the second integrator have a resistance value α · R connected to an output terminal of the first inverting amplifier. A third resistor, a fourth resistor connected to a non-inverting output terminal of the delay device and having a resistance value of R, a second inverting amplifier, and an input / output terminal of the second inverting amplifier A second addition integrator including a second capacitor having a capacitance value C connected therebetween.

The signal obtained by subtracting the output of the delay unit multiplied by α from the amplifier from the input signal having a voltage multiplied by α (α> 1) is input to the first integrator, whereby the S / N characteristic of the circuit is obtained. The internal signal voltage of the first stage of the delta-sigma modulation circuit which has a large effect on the internal signal voltage is increased, while the output of the first integrator is multiplied by 1 / α by the attenuator to the second stage where the integrated voltage is increased. By making the signal voltage equal to the conventional one, overflow in the subsequent stage of the delta-sigma modulation circuit is prevented.

[0043]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
The sigma modulation circuit includes an amplifier for amplifying the output signal of the delay unit by a predetermined magnification α, a first subtractor for subtracting the output signal of the amplifier from an analog input signal, and integrating the output of the first subtractor. A first integrator, an attenuator for attenuating the output of the first integrator to 1 / α, a second subtractor for subtracting the output signal of the delay unit from the output of the attenuator, A second integrator for integrating the output of the second subtractor, a quantizer for quantizing the output of the second integrator, and delaying the output of the quantizer by one sample period and converting the output to an analog signal And a delay unit that converts the digital output signal from the quantizer.

The S / N characteristic of the circuit is obtained by inputting a signal obtained by subtracting the output of the delay unit, which has been multiplied by α by the amplifier, from the input signal having a voltage multiplied by α (α> 1) to the first integrator. The internal signal voltage of the first stage of the delta-sigma modulation circuit which has a large effect on the internal signal voltage is increased, while the output of the first integrator is multiplied by 1 / α by the attenuator to the second stage where the integrated voltage is increased. By making the signal voltage equal to the conventional one, there is an effect of preventing an overflow of the subsequent stage of the delta-sigma modulation circuit. Therefore, it is possible to provide a delta-sigma modulation circuit that has good S / N characteristics, does not increase the number of quantizers, and does not increase the circuit scale.

According to a second aspect of the present invention, in the delta-sigma modulation circuit according to the first aspect, the amplifier, the first subtractor, and the first integrator have one terminal connected to an input terminal of an analog input signal. A first resistor having a resistance value of R, a second resistor having one terminal connected to the inverting output terminal of the delay device and having a resistance value of R / α, and a first inverting amplifier. Connected between the input and output terminals of the first inverting amplifier,
A first capacitor having a capacitance value C, wherein the other terminal of each of the first and second resistors is connected to an input terminal of the first inverting amplifier. And an attenuator, a second subtractor, and a second integrator, one terminal of which is connected to the output terminal of the first inverting amplifier, and the third resistor having a resistance value of α · R. One terminal is connected to a non-inverting output terminal of the delay device, and a fourth resistor having a resistance value of R, a second inverting amplifier, and an input / output terminal of the second inverting amplifier. Connected and capacitance value C
And a second capacitor having a second capacitance having the following configuration: the second and third resistors are each configured to have a second terminal connected to an input terminal of the second inverting amplifier. It is characterized by having.

The first inverting amplifier integrates an input signal having a voltage α times the conventional value with an integration constant RC determined by the first resistor and the first capacitor, and outputs an inverted output signal of the delay unit. The signal is integrated by an integration constant RC / α determined by the second resistor and the first capacitor, and an added signal of both signals is inverted and output. The output of the first integrator is input to a second inverting amplifier via a third resistor, is integrated by an integration constant αRC determined by a combination with a second capacitor, and outputs a signal from a delay unit. The inverted output is integrated with the integration constant RC via the fourth resistor, and the added output of both signals is inverted and output. The output of the first integrator is multiplied by 1 / α with an attenuator to the subsequent stage where the integrated voltage becomes large, and the internal signal voltage is made equal to the conventional one, thereby preventing the overflow of the subsequent stage.

Hereinafter, specific embodiments of the delta-sigma modulation circuit according to the present invention will be described in detail with reference to the drawings.

(Embodiment 1) FIG. 1 is a block diagram showing a configuration of a delta-sigma modulation circuit according to Embodiment 1 of the present invention. In FIG. 1, 100 is a first subtractor, 1
01 is the first integrator, 102 is the attenuation rate 1 / α (α> 1)
, 103 is a second subtractor, 104 is a second integrator, 105 is a quantizer, 106 is a feedback delay unit, 10
Reference numeral 7 denotes a feedback amplifier having an amplification factor α. The input terminal of the analog input signal αX is connected to the (+) input terminal of the first subtractor 100, and the output terminal of the feedback amplifier 107 is connected to the first input terminal.
Is connected to the (-) input terminal of the subtractor 100. The output terminal of the first subtractor 100 is connected to the input terminal of the first integrator 101, and the output terminal of the first integrator 101 is connected to the input terminal of the attenuator 102. Attenuator 102
Is connected to the (+) input terminal of the second subtractor 103, the output terminal of the feedback delay unit 106 is connected to the input terminal of the feedback amplifier 107, and the second subtractor 103 (-) Input terminal. Second
The output terminal of the subtractor 103 is connected to the input terminal of the second integrator 104, and the output terminal of the second integrator 104 is connected to the input terminal of the quantizer 105. Quantizer 10
The output terminal 5 is connected to the output terminal of the delta-sigma modulation circuit and to the input terminal of the delay 106 for feedback.

The feedback amplifier 107 amplifies the feedback signal FB output from the delay unit 106 by α times, and a signal obtained by amplifying the feedback signal FB by α times is input to the first subtractor 100. The analog input signal αX is supplied to the first subtractor 100
Then, the difference between the feedback signal FB from the amplifier 107 and the signal obtained by multiplying the feedback signal FB by α is calculated by the first integrator 101. The integrated output of the first integrator 101 is attenuated by a factor of 1 / α by the attenuator 102, and the difference between the integrated output of the first integrator 101 and the feedback signal FB from the delay unit 106 is calculated by the second subtractor 103. The integration is performed by the integrator 104. Second
The integrated output of the integrator 104 is quantized by a quantizer 105, output as a digital output signal Y, and input to a feedback delay 106.

The feedback delay 106 delays the quantized digital output signal Y by one sample period,
It has a function of converting into an analog signal corresponding to the magnitude of the signal Y.

In the above circuit configuration, the transfer characteristics of the delta-sigma modulation circuit are expressed by using the Z-transformation notation, where the input signal is αX (Z), the output signal of the quantizer 105 and the quantization noise are Y ( Z), Q (Z),

[0052]

(Equation 12)

Is as follows. Solving this,

[0054]

(Equation 13)

In terms of characteristics, the characteristics are the same as those of (Expression 2) for the conventional delta-sigma modulation circuit shown in FIG.

However, when internal circuit noise existing in a practical circuit is considered, there is a difference in the S / N characteristics of the circuit. FIGS. 2 and 5 show circuit blocks in a case where the internal circuit noise is represented as the input conversion noise for the first and second integrators 101, 104, 401, and 403 in FIGS.

The components denoted by reference numerals 100 to 107 in FIG. 2 are the same as those in FIG. 1, and the first adder 200 and the second adder 201 are convenient for explaining the effect of internal circuit noise. It is added to the drawing in the drawing, and is not a component of an actual circuit.

The same applies to FIG. 5, and reference numeral 4 in FIG.
The components of 00 to 405 are the same as those in FIG.
The first adder of 00 and the second adder of 501 are for explanation of internal circuit noise and are not components of an actual circuit.

First, the case of the conventional delta-sigma modulation circuit shown in FIG. 5 will be described.

First subtractor 400 and first integrator 401
The internal circuit noise of the pre-stage 502 of the delta-sigma modulation circuit composed of
Is added to the first adder 500, and the second subtractor 4
02 and the internal circuit noise of the latter stage 503 of the delta-sigma modulation circuit composed of the second integrator 403 are added to the second adder 501 as the input equivalent noise ε2 of the second integrator 403.

When the transfer characteristics including the internal circuit noise are represented by using a Z-transform expression,

[0062]

[Equation 14]

Is obtained. Solving this,

[0064]

(Equation 15)

Is obtained. Internal circuit noise ε1 of former stage 502
The component appears as is in the output. However, the internal circuit noise ε2 component of the latter stage 503 includes

[0066]

(Equation 16)

The transfer characteristic coefficient H (Z) is applied.

(Equation 16) represents the differential characteristic, and since the low-frequency noise level is suppressed, the influence of the internal circuit noise ε2 of the subsequent stage 503 on the S / N characteristic is small.

For example, when the oversampling ratio is 64, the influence of the internal circuit noise ε2 of the rear stage 503 on the S / N characteristic of the delta-sigma modulation circuit is different from the influence of the internal circuit noise ε1 of the front stage 502 on the sigma. The level is about -28 dB and can be almost ignored. On the other hand, the influence of the internal circuit noise ε1 of the former stage 502 is large. Therefore, (Equation 15) is approximately (Equation 17) as a result.

[0070]

[Equation 17]

On the other hand, as described with reference to the conventional delta-sigma modulation circuit shown in FIG.
Is required to be about 1 to 2 times the analog input signal X, and the integrated voltage of the second integrator 403 is required to be about 2 to 4 times, so that the amplitude of the analog input signal X is relatively reduced. I was letting it. As a result, there is a problem in that the circuit is easily affected by internal noise, and the S / N characteristics of the entire circuit deteriorate.

Next, the case of the delta-sigma modulation circuit according to the first embodiment of the present invention will be described with reference to FIG.

As in the case of the conventional delta-sigma modulation circuit shown in FIG. 5, the first subtractor 100 and the first integrator 1
01 of the delta-sigma modulation circuit comprising
3 is added to the first adder 200 as the input equivalent noise ε1 of the first integrator 101, and the second subtractor 1
The internal circuit noise of the subsequent stage 204 of the delta-sigma modulation circuit composed of the second integrator 104 and the second integrator 104 is added to the second adder 201 as the input equivalent noise ε2 of the second integrator 104.

Since the integrated voltage of the first integrator 101 is smaller than the integrated voltage of the second integrator 104, the internal signal level of the first integrator 101 can be amplified. When the amplification degree is α (> 1), the amplitude of the analog input signal can be given as α times the amplitude of the conventional signal, that is, an input signal having an amplitude of αX. However, the signal level input to the second integrator 104 is attenuated to 1 / α by the attenuator 102 because the signal overflows in the second integrator 104 as it is.

When the transfer characteristic including the internal circuit noise is represented by using a Z-transform expression,

[0076]

(Equation 18)

Is obtained. Solving this,

[0078]

[Equation 19]

When the differential term is ignored, (Equation 19)
Is approximately (Equation 20) as a result.

[0080]

(Equation 20)

As is clear from the comparison between (Equation 17) and (Equation 20), the influence of the internal circuit noise ε1 of the former stage 203, which greatly affects the S / N characteristics of the delta-sigma modulation circuit, is larger than that of the conventional one. , 1 / α, and the S / N characteristics are greatly improved.

On the other hand, in the case of the delta-sigma modulation circuit shown in FIG. 6, while the integrated voltage of the second integrator 604 is suppressed, the first Is limited on the side of the first integrator 601, and the performance is almost the same as that of the first embodiment. In the case of FIG. 6, two expensive quantizers are required, whereas in the case of the first embodiment, only one quantizer is required, and the cost can be reduced. That is, it is possible to improve the S / N characteristics without increasing the circuit scale without increasing the number of quantizers.

(Embodiment 2) Next, a delta-sigma modulation circuit according to Embodiment 2 of the present invention will be described in detail with reference to FIG.

In FIG. 3, reference numeral 300 denotes a first resistor, 3
01 is a second resistor, 302 is a first capacitor, 303 is a first inverting amplifier, 304 is a third resistor, and 305 is a fourth resistor.
, 306 is a second capacitor, 307 is a second inverting amplifier, 308 is a quantizer, and 309 is a delay unit. First
One end of the resistor 300 is connected to the input terminal of the analog input signal αX, and the other end is connected to the input terminal of the first inverting amplifier 303. The second resistor 301 has a resistance value R / α that is 1 / α times the resistance value R of the first resistor 300,
One end is connected to the inverted output terminal of the delay unit 309, and the other end is connected to a connection point A between the first resistor 300 and the first inverted amplifier 303. The first capacitor 302 is connected between the output terminal of the first inverting amplifier 303 and the connection point A. The first resistor 300, the second resistor 301, the first inverting amplifier 303, and the first capacitor 302
Constitutes a first addition integrator 310. The first addition integrator 310 is equivalent to the amplifier 107, the first subtractor 100, and the first integrator 101 in FIG. The third resistor 304 has a resistance value α · R that is α times the resistance value R of the first resistor 300, one end of which is connected to the output terminal of the first inverting amplifier 303, and the other end of which has the second value. Is connected to the input terminal of the inverting amplifier 307. The fourth resistor 305 has the same resistance R as the resistance R of the first resistor 300, one end of which is connected to the non-inverting output terminal of the delay unit 309, and the other end of which is connected to the third resistor 304. It is connected to a connection point B with the second inverting amplifier 307. The second capacitor 306 is connected between the output terminal of the second inverting amplifier 307 and the connection point B. Second inverting amplifier 307
Is connected to the input terminal of the quantizer 308, and the output terminal of the quantizer 308 is connected to the output terminal of the delta-sigma modulation circuit and to the input terminal of the delay unit 309. .

The analog input signal αX is input to the first inverting amplifier 303 via the first resistor 300 having the resistance value R. The first inverting amplifier 303 includes a delay unit 3
09 and the sign of the quantizer output signal / FB delayed by one sample period and inverted (for the sake of notation, in this specification, instead of the bar indicating the inversion in FIG. /) Is input via a second resistor 301 having a resistance value R / α. These signals are supplied to a first inverting amplifier 303, a first resistor 300, a second resistor 301, and a first capacitor 302 having a capacitance value C inserted between the input and output of the first inverting amplifier 303. Are integrated by the first addition integrator 310 composed of

The output of the first inverting amplifier 303 is input to the second inverting amplifier 307 via the third resistor 304 having the resistance value α · R. Also, the second inverting amplifier 307
The quantizer output signal FB delayed by one sample period by the delay unit 309 has a resistance R
5 is input. These signals are supplied to a second inverting amplifier 307, a third resistor 304, and a fourth resistor 305.
And a second addition integrator 311 composed of a second capacitor 306 having a capacitance value C inserted between the input and output of the second inverting amplifier 307.

The output of the second inverting amplifier 307 is quantized by the quantizer 308 and is taken out as a digital output signal Y. The output is delayed by one sample period by the delay unit 309 and is converted into an analog signal. F
B and / FB.

Here, the time constant R · C determined by the resistance value R and the capacitance value C is given by fs where the sampling frequency of the delta-sigma modulation circuit is fs.

[0089]

(Equation 21)

Is selected so that

First resistor 300 and second resistor 301
Since the connection point A to this receives the inverted quantizer output signal / FB of the delay unit 309, it functions as the first subtractor 100 in FIG. The analog input signal αX is supplied to a quantizer 308 by two inverting amplifiers 303 and 307.
, No inversion occurs as a result. A connection point B between the third resistor 304 and the fourth resistor 305 receives the non-inverted quantizer output signal FB of the delay unit 309 here. Since the inversion is performed by the first inverting amplifier 303, it plays the role of the second subtractor 103 in FIG.

The resistance value R / α of the second resistor 301 is equal to the first resistance value R / α.
Is 1 / α times the resistance value R of the resistor 300 of FIG.
When the integral gain on the side of the resistor 300 is set to 1 (reference value), the integral gain on the side of the second resistor 301 is α, and FIG.
Can be replaced by a resistor.

The resistance value α · R of the third resistor 304
Is α times the resistance value R of the first resistor 300, the integral gain of the third resistor 304 is 1 / α, and the role of the attenuator 102 in FIG. 1 can be replaced by a resistor. it can.

Therefore, the delta-sigma modulation circuit of FIG. 2 is electrically equivalent to the delta-sigma modulation circuit of FIG. 1 and, as described above, without increasing the number of quantizers and without increasing the circuit scale. , S / N characteristics can be improved.

[0095]

As described in detail above, the present invention provides a
According to the sigma modulation circuit, the S / N characteristics of the circuit can be improved without increasing the number of quantizers and without increasing the circuit scale.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a delta-sigma modulation circuit according to a first embodiment of the present invention.

FIG. 2 is a pseudo block diagram for explaining the influence of internal circuit noise in the delta-sigma modulation circuit according to the first embodiment of the present invention.

FIG. 3 is a block circuit diagram showing a configuration of a delta-sigma modulation circuit according to Embodiment 2 of the present invention.

FIG. 4 is a block diagram showing a configuration of a delta-sigma modulation circuit according to a first conventional technique.

FIG. 5 is a pseudo block diagram for explaining the influence of internal circuit noise in a delta-sigma modulation circuit according to a first conventional technique.

FIG. 6 is a block diagram showing a configuration of a delta-sigma modulation circuit according to a second conventional technique.

[Explanation of symbols]

 100 first subtractor 101 first integrator 102 attenuator 103 second subtractor 104 second integrator 105 quantizer 106 delay 107 .., An amplifier 203... A first stage 204... A second stage 300... A first resistor 301 with a resistance value R 301... A second resistor 302 with a resistance value R / α 302. ... A first inverting amplifier 304... A third resistor 305 having a resistance value α · R 305 a fourth resistor 306 having a resistance value R 306 a second capacitor 307 having a capacitance value C 307. Inverting amplifier 308 Quantizer 309 Delay device 310 First addition integrator 311 Second addition integrator α α

Claims (2)

[Claims] 1. An amplifier for amplifying an output signal of a feedback delay unit with a predetermined magnification α, a first subtractor for subtracting an output signal of the amplifier from an analog input signal, and a first subtractor. A first integrator for integrating the output; an attenuator for attenuating the output of the first integrator to 1 / α; a second subtractor for subtracting the output signal of the delay unit from the output of the attenuator A second integrator for integrating the output of the second subtractor, a quantizer for quantizing the output of the second integrator, and delaying the output of the quantizer by one sample period. A delta-sigma modulation circuit, comprising: the above-mentioned delay unit for converting the digital output signal into an analog signal; and extracting a digital output signal from the quantizer. 2. An amplifier, a first subtractor, and a first integrator, one terminal of which is connected to an input terminal of an analog input signal;
A first resistor having a resistance value of R, a second resistor having one terminal connected to the inverting output terminal of the delay device and having a resistance value of R / α, a first inverting amplifier, A first capacitor connected between the input and output terminals of the first inverting amplifier and having a capacitance value C, and the other terminals of the first and second resistors are respectively connected to the first inverting amplifier. The first connected to the input terminal
And an attenuator, a second subtractor, and a second integrator each having one terminal connected to the output terminal of the first inverting amplifier and having a resistance value α · R. A resistor connected to a non-inverting output terminal of the delay device;
A fourth resistor having a resistance value of R, a second inverting amplifier, and a second capacitor having a capacitance value C connected between input and output terminals of the second inverting amplifier; A second resistor connected to the input terminal of the second inverting amplifier with the other terminal of each of the third and fourth resistors connected thereto;
2. The delta-sigma modulation circuit according to claim 1, wherein the delta-sigma modulation circuit is configured as an addition integrator.