JPH10173533A - Low noise sigma-delta modulation type ad converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a Σ-Δ modulation type AD converter which can reduce the intensity of noises due to an idling pattern by superimposing the DC voltage on an analog signal. SOLUTION: This AD converter 2 oversamples an inputted analog signal via a modulator 11, generates a one-bit data string, eliminates a high frequency component of the data via the digital processing of a decimation filter 12, and outputs the digital data. The DC voltage superimposing devices 41 and 41 are added to an input stage of the converter 2 to superimpose the the DC voltage to the analog signal. This analog signal is processed by the modulator 11. Thus, the noises due to an idling pattern are eliminated when the analog signal is set at OV. The superimposed DC voltage can be eliminated after the oversampling.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the technical field of AD converters, and more particularly to a technique for improving the characteristics of a Σ-Δ modulation type AD converter.

[0002]

2. Description of the Related Art In recent years, digital recording compact discs and digital audio tapes have been widely used in place of analog recording records.
A converters are widely used.

In the field of digital audio technology, A
The successive approximation method was adopted as the D converter,
This system requires a high-precision DA converter, and it is said that it is not easy to obtain a 12-bit resolution without trimming. Further, a high-order and high-accuracy analog filter is also required, and it has been difficult to reduce the price.

Therefore, even in the prior art, an AD converter based on an oversampling method has been adopted in place of the successive approximation method, and the sampling frequency has been increased by several tens of times (oversampling) with respect to the frequency of a desired band, and By digitally processing the signal, a signal with a good S / N ratio can be obtained without using an expensive analog filter.

FIG. 4 shows a オ ー バ -Δ modulation type AD converter among such conventional oversampling type AD converters. This Σ-Δ modulation type AD converter 101
Is the modulator 111 and the decimation filter 1
And a differential input signal IN, which is an analog signal, is input to the modulator 111.

The input differential input signal IN is oversampled in the modulator 111, and the quantization noise included in the band is shaped out of the band based on the transfer function of the modulator 111, and a 1-bit data string Is converted to Next, the decimation filter 1
At 12, the out-of-band quantization noise is removed by its stopband characteristic and output as an in-band output signal (digital data).

In general, the modulator of the Σ-Δ modulation type AD converter is composed of an adder, an integrator, a delay circuit, a DA converter, and a comparator.
Assuming that 11 is the fourth order, four adders 131 to
134 and four integrators 141 to 144 are connected in series in an alternate arrangement, and the output of the last-stage integrator 144 is input to a 1-bit comparator 151. Comparator 151 compares the input signal with a reference voltage and outputs a 1-bit data string.
12 and via a delay circuit 160
Are input to the D / A converters 161 to 164.
Each of the DA converters 161 to 164 converts the input 1-bit data string into an analog signal,
To 134. Each of the adders 131 to 134 is a DA
Output signals of converters 161 to 164 and differential input signal I
N or the outputs of the pre-stage integrators 141 to 143 are added, respectively, and the post-stage integrators 141 to 143 of the adders 131 to 134 are added.
144. Thus, the 1-bit data string output from the comparator 151 is input to the decimation filter 112 as an output signal, and is also fed back to the input stages of the four integrators 141 to 144. ing.

With such a configuration, the first stage adder 1
31 differential input voltage IN is inputted to the sampling is performed in addition 64 times the frequency of the sampling frequency F _s,
Noise shaping is performed when a 1-bit data string is generated. Next, the quantization noise outside the band is removed by the decimation filter 112 by its stop band characteristic, and the signal component within the band is output as digital data. Such Σ-Δ conversion type A / D converters are widely used as middle speed A / D converters because they can follow steep changes in input signals and are inexpensive.

However, in the above-described conventional Σ-Δ modulation type A / D converter, not only the noise that cannot be completely removed by the decimation filter 112 but also the analog signal contains zero V in the output digital data. However, it is known that noise is included even when the digital signal does not become zero.
When the analog signal is at zero volt, the differential input signal IN is at zero volt and contains no AC component, so the digital signal should also show zero. However, even in such a case, the digital output data includes a noise signal having a frequency component (one frequency component or a plurality of frequency components) within a band, and the noise signal is required to have high quality. This is a problem that cannot be ignored in audio systems and the like.

[0010]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned disadvantages of the prior art, and an object of the present invention is to provide a low-noise Σ-Δ modulation AD converter.

[0011]

Generally, in a Σ-Δ modulation type AD converter, when a modulator or a decimation filter is in an idling state, an output data string of the modulator, a data string inside the decimation filter, or a decimation filter. It is known that a specific idling pattern has occurred in the output of.

When a frequency band component or a folded frequency component included in the idling pattern enters a modulator or a preceding analog signal processing system via a power supply line, a ground line, or the like, they become noise. Signal. In the modulator, the noise signal is sampled in the same manner as a signal to be converted such as an audio signal, and even when a zero DC signal whose analog signal is zero V is input, a noise sound having a noise intensity in the output signal is obtained. Is thought to be included.

FIG. 5 shows the noise included in the digital output of the left and right channels when the analog signal is zero V in the conventional Σ-Δ modulation type AD converter.

The low level side of the differential analog input is 2.5 V
, And the horizontal axis represents the differential input DC voltage (not including the AC component) when the high-level potential is changed between 2.2 V and 2.9 V, and the vertical axis represents the frequency. ,
FIG. 6 is a graph showing the relationship between the differential DC voltage and the peak noise frequency when the differential input DC voltage is changed.

When the differential input DC voltage is zero V, the noise peak is at a low frequency close to zero Hz. However, when the absolute value of the differential input DC voltage is increased, the frequency of the peak noise increases linearly, At ± 0.1 V, the frequency becomes 24 kHz. When the frequency is further increased, the frequency starts to decrease. At ± 0.2 V, the frequency becomes the same as when zero V is applied.

As described above, depending on the magnitude of the differential input DC voltage, the frequency of the peak noise exhibits a folding characteristic between a low frequency and 24 kHz, but the intensity of the noise peak is zero V to ± 0.1 V. In the range of about -110 dB, ±
In the range of (0.1 to 0.2) V, it is about -125 dB, and it can be seen that the noise intensity decreases as the differential input DC voltage increases.

By the way, the general noise intensity output from the 方式 -Δ modulation type AD converter is determined by the noise transfer function of the modulator and the attenuation of the pass band in the decimation filter. It is known that it is determined by the characteristics of the decimation filter.

However, from the noise intensity graph shown in FIG. 6, no dependence on the transfer function (noise shaping characteristics) of the modulator or the characteristics of the decimation filter is observed, and the relationship between the noise intensity and the frequency is determined by the band. (In FIG. 6, the differential input DC voltage is −0.2,
The noise intensity is constant within a range of ± 0.1 V with respect to 0 and 0.2 V, respectively, and the noise intensity decreases each time the frequency of the peak noise returns.

According to the present invention, the DC voltage is smaller than the noise intensity that occurs when an analog signal is not input (when the AC component and the DC component of the differential analog signal are at zero volts), such as when there is no sound in an audio system. It is created based on the knowledge that the noise intensity is smaller when the frequency is folded back by being superimposed, and the invention described in claim 1 is based on the input analog signal. And a decimation filter that is disposed downstream of the modulator and that digitally processes the digital data stream to remove a high-frequency component (out-of-band noise component). ＡＤ-Δ modulation type A / D converter, the preceding stage of the modulator or the signal sampling stage. Provided DC voltage superimposing circuit, characterized in that it is configured to superimpose a DC voltage to the analog signal.

When a DC voltage is superimposed on an analog signal, the noise intensity due to the idling pattern decreases as described above. In general, the noise floor level of the digital signal output from the decimation filter is about -120 dB. Therefore, there is no problem if the DC voltage is superimposed to make the noise intensity equal to or lower than -120 dB.

In the は -Δ modulation type A / D converter according to the first aspect, as in the second aspect, the decimation filter can remove the superimposed DC voltage component by digital processing. With such a configuration, the output of the Σ-Δ modulation type AD converter is
The superimposed DC voltage has no effect.

According to a third aspect of the present invention, a correction operation circuit is provided at a stage subsequent to the decimation filter, and the output of the decimation filter is subjected to an operation process, so that the output of the decimation filter can be changed. Even if the superimposed DC voltage component is removed, similarly, the superimposed DC voltage does not affect the output of the Σ-Δ modulation type AD converter.

Furthermore, as in the invention according to claim 4,
The same applies to a case where a digital high-pass filter is provided downstream of the decimation filter so that the superimposed DC voltage component is not transmitted to the downstream.

If the digital high-pass filter is configured to be switched from a state with a small attenuation factor to a state with a high attenuation factor when the operation is started, the attenuation factor is small. If the A / D converter is started up quickly, then the attenuation factor is increased to remove the superimposed DC voltage component, the settling time is shortened, and the Σ-Δ modulation A / D converter starts operating at a predetermined performance. Time can be shortened.

The magnitude of the DC voltage component to be superimposed is Σ−Δ
Since the attenuation rate is constant depending on the type of the AD converter, when the attenuation rate is switched, a certain time elapses with the attenuation rate being small as in the invention according to claim 6, and the superimposed DC voltage component becomes a predetermined value. After being attenuated to the level, switching and the attenuation rate can be increased.

[0026]

Mark 2 DETAILED DESCRIPTION OF THE INVENTION Figure 1 is a sigma-delta modulation type AD converter for audio of an embodiment of the present invention, a differential analog signal IN ₁ showing the left and right channels in a stereo audio signal, is input as iN _2, is converted to a digital signal by one output signal DAT
Output as A. That is, when performances and voices are collected in a two-channel stereo system and converted into two-channel differential analog signals, they can be converted into one digital data and output (here, differential input is used). signal iN ₁ is 1 channel side, the differential input signal iN ₂ is assumed to be 2-channel side).

This Σ-Δ modulation type AD converter 2
Modulator 11 and decimation filter 12
, A digital high-pass filter 13 and an interface 14.

In the modulator 11, reference numeral 11 in FIG.
Two unit modulators of the fourth order shown in FIG. 1 are incorporated, and are assigned to the first channel side and the second channel side, respectively. Two analog signals input to the modulator 11, a band 64 times the frequency for doubling the sampling frequency F _s of (24kHz) (3.072MHz),
Each unit modulator oversamples, performs fourth-order noise shaping as shown in FIG. 4, and converts the data into two 1-bit data strings (digital density modulation signals) for one channel and two channels. Is done.

When two digital signals each consisting of a 1-bit data string are input to the decimation filter 12, noise components outside the band after noise shaping by the modulator 11 are performed by the digital low-pass filter in the decimation filter 12. Is removed. Then, the digital data string 64F _s rate is decimation in 1F _s rate of data is output as a digital signal of 20 bits of the frequency F _s.

The digital signal is input to the interface 14 via the digital high-pass filter 13, and the two-system digital signals on the one-channel side and the two-channel side are combined into one digital signal, and the digital output signal ( DATA).

The input stage or the signal sampling stage of the Σ-Δ modulation type AD converter 2 has a DC voltage superposition configured so that a desired DC voltage (delta offset: Δ) can be superimposed on the input signal. Circuits 4 ₁ and 4 ₂ are provided, and the collected left and right two-channel differential input signals IN ₁ and IN ₂ are first input to DC voltage superimposing circuits 4 ₁ and 4 ₂ , respectively, and each DC voltage superimposing circuit is superimposed. The circuits 4 ₁ and 4 ₂ are configured such that a preset DC voltage is superimposed and then input to the modulator 11 described above.

The ＡＤ-Δ modulation type AD converter 2
When an AC signal of the differential input signal IN ₁ is zero V, when superimposing a DC voltage by the DC voltage superimposing circuit 4 _1, Figure a relationship between magnitude and peak noise frequency of the DC voltage 2
This is shown in the graph of FIG.

When the DC voltage is not superimposed (zero V),
Although the frequency of the peak noise is a low frequency close to zero Hz, when the DC voltage to be superimposed is increased (the absolute value is increased), the frequency of the peak noise is linearly increased, and ±
It is 24 kHz at 0.1 V. When the DC voltage to be superimposed is further increased in the positive and negative directions, the frequency starts decreasing, and at ± 0.2 V, the frequency becomes as low as that when no DC voltage is superimposed. When the DC voltage to be superimposed is further increased in the positive and negative directions to ± 0.2 V or more, the frequency of the peak noise starts to increase again.

As described above, the frequency of the peak noise changes linearly depending on the magnitude of the DC voltage to be superimposed. When the DC voltage exceeds a specific level, the frequency of the peak noise returns between a low frequency and 24 kHz. The intensity of the peak noise is about -110d in the range of -0.1V to + 0.1V.
B, about -125 dB in the range of -0.1 V or less and in the range of +0.1 V or more, and the peak noise intensity decreases as the absolute value of the DC voltage to be superimposed increases.

[0035] Based on this graph, DC voltage superimposing circuit 4 ₁ described above is about + 0.12 V with respect to the differential input signals IN ₁
Is set so as to superimpose the DC voltage (Δ ₁ = 0.12 V) on the channel 1 side of the modulator 11 even if the differential input signal IN ₁ is zero V (when there is no sound in the audio signal). , delta ₁ of the magnitude of the DC voltage is configured to be input. Thus, the differential input signal IN ₁ is the peak noise intensity when the zero V is equal to or less than -125 dB.

Next, +0.12 V DC is applied to the channel 1 side.
While superimposing the voltage to operate the DC voltage superimposing circuit 4 _2, obtained by superimposing a DC voltage to the differential input signal IN ₂ channel 2 side. The relationship between the DC voltage and the frequency of the peak noise at that time is shown by a solid line graph in FIG. This figure 2
In FIG. 2B, the graph of FIG.

On the channel 2 side, when the superimposed DC voltage is increased in the positive and negative directions from the state of zero V, the peak noise frequency starts to decrease, and becomes the lowest frequency at about ± 0.12 V, When the frequency increases further in the positive and negative directions, the frequency of the peak noise starts to increase again.

When the magnitude of the DC voltage to be superimposed exceeds ± 0.2 V, the voltage falls from −110 dB to −125 dB or less. From this graph, about 0.22 for two channels
When a DC voltage of V is superimposed (Δ ₂ = 0.22 V), even when the differential input signal IN ₂ is in a state of zero V or close to zero V, noise caused by the idling pattern is reduced by −12.
It can be 5 dB or less.

As described above, the differential input signals IN ₁ and IN ₂ composed of the two differential analog signals are applied to the DC voltage superimposing circuits 4 ₁ and 4 ₂ by Δ ₁ = 0.12 V and Δ ₂ =
A DC voltage of 0.22 V is superimposed, and the input voltage range of the differential analog signal input to the modulator 11 is shifted by the DC voltage superimposed by the DC voltage superimposing circuits 4 ₁ and 4 _2. (If the DC voltage is positive, the maximum input voltage and the minimum input voltage increase by the DC voltage, and if the DC voltage is negative, the DC
Voltage).

Therefore, the input voltage range of the modulator 11 is set with a margin for the DC voltage to be superimposed, and the number of internal processing bits is increased even in the decimation filter stage.

In the Σ-Δ modulation method, the DC voltage component is also converted into digital data. Therefore, the 1-bit data string output from the modulator 11 of the Σ-Δ modulation method AD converter 2 is superimposed on the data. That is, the obtained DC voltage component is included.

Further, when a 1-bit data string including the DC voltage is input to the decimation filter 12, the decimation filter 12 digitally processes the input data string and converts a 20-bit signal. Output, the output of the decimation filter 12 is also D
C voltage superimposing circuit 4 _1, 4 ₂ is that it contains the superimposed DC voltage component.

Therefore, in the Δ-Δ modulation type AD converter 2, the 20-bit digital signal output from the decimation filter 12 is input to the digital high-pass filter 13 so that the superimposed DC voltage component is removed. Is configured.

Such a digital high-pass filter 1
3 is shown in a schematic block diagram of FIG.
In the digital high-pass filter 13, the switch S
By using W ₁ and SW ₂ , it is configured to be switched between a case where it is used as a 13th-order digital high-pass filter and a case where it is used as a ninth-order digital high-pass filter. Power is supplied to the Σ-Δ modulation type AD converter 2,
It is assumed that the internal circuit starts operating. When functioning as a 13th-order digital high-pass filter, the attenuation factor at frequencies below 1 Hz is -3 dB, and when functioning as a 9th-order digital high-pass filter, the attenuation factor at frequencies below 165 Hz is -3 dB.

The operation of the high-pass filter 13 will be described schematically. First, the switches SW ₁ and SW ₂ are connected to the output side of a ninth-order digital high-pass filter, and are input from the pre-stage decimation filter 12. 20
The bit signal X (z) is operated as a ninth-order digital high-pass filter.

During this time, the digital high-pass filter 13
Is gradually reduced from zero dB according to the attenuation characteristic of the ninth-order digital high-pass filter. When indicating this in the graphs of schematic attenuation in FIG. 3 (b), the attenuation characteristics of the digital high-pass filter dashed straight lines of ninth order indicated by the reference numeral L _1.

After a lapse of a predetermined time, when the switches SW ₁ and SW ₂ are connected to the output side of the digital high-pass filter having a total order of 13 at time t ₁ , thereafter,
The digital high-pass filter 13 starts operating as a 13th-order high-pass filter. In this case, the output of the digital high-pass filter 13, the attenuation factor -A having reached 9 order digital high-pass filter at time t _1, it begins to initiate damping in accordance with the attenuation characteristics of the 13-order digital high-pass filter, the time t ₂ Attains an attenuation rate of −60 dB. Straight broken line indicated by reference numeral L ₂ is, when connected to the digital high-pass filter side of the switch SW _1, SW ₂ order of total of 13 primary from the beginning, the attenuation characteristics of the digital high-pass filter 13.

In general, in the case of a digital high-pass filter, the higher-order filter and the lower-order filter have higher attenuation characteristics, but the increase rate of the attenuation rate is slow, and the desired attenuation rate is obtained. There is a disadvantage that it takes a long time for the settling time to reach. As is clear from the graph of FIG. 3B, the time when the ninth-order and thirteenth-order digital high-pass filters reach the same -60 dB attenuation factor is later in the thirteenth-order.

[0049] In general, if the order of the digital high-pass filter n, the operating frequency is f (In the sigma-delta modulation scheme AD converter 2 is F _S described above.), The n
The next high-pass filter has a predetermined attenuation rate H (in dB notation, 2).
It is known that the settling time T required to reach 0 × logH) is represented by T = 2 ⁿ × f × ln (1 / H).

[0050] According to the above equation, to reach the same attenuation factor, 13 order digital high-pass filter requires a settling time of 2 ⁴ times the 9 order digital high-pass filter (2 ^{13/2 9} = 2 ⁴⁾ Will be.

The digital high-pass filter 13 operates as a low-order (ninth-order) digital high-pass filter immediately after the start of operation, and after its operation is stabilized to some extent in that state, starts operating as a 13-order digital high-pass filter. (Time t ₁ ), the attenuation characteristic changes as indicated by the broken line indicated by the symbol L. Accordingly, the initial attenuation rate increases quickly, and the target -6 is reduced in a shorter time (time t ₂ ) than when the digital filter operates as a 13th-order digital filter from the beginning.
An attenuation rate of 0 dB is obtained. Is that time t ₂ or later,
It operates with an attenuation rate of -60 dB to -80 dB.

As described above, in the Σ-Δ modulation type AD converter 2 described above, the DC voltage is superimposed by the DC voltage superimposing circuits 4 ₁ and 4 _{2 so} that the differential input voltages IN ₁ and IN ₂ are zero volts. The noise at the time is reduced to convert the analog differential input signals IN ₁ and IN ₂ into digital signals, and then the superimposed DC voltages Δ ₁ and Δ ₂ are settled with a short settling time,
Since high-performance digital high-pass filter 13 removes the signal, high-quality analog / digital conversion can be performed.

The above-mentioned Σ-Δ modulation type AD converter 2
Is a two-channel stereo input type, but the Σ-Δ modulation type AD converter of the present invention is not limited to this. If there are N unit modulators that individually process _N differential input voltages IN _{1 to} IN _N , then N D modulators
The C voltage superimposing circuit 4 ₁ to 4 _N, each of the differential input voltage IN ₁
To to IN _N, you can superimpose a DC voltage Δ ₁ ~Δ _N. In this case, the output from the decimation filter is shown in the graph of FIG. 2C as in FIGS. 2A and 2B.

In the graph of FIG. 2C, the graphs of the first and second channels are indicated by broken lines, the graph of the Nth channel is indicated by solid lines, and other graphs are omitted. The peak noise intensity of the solid line graph is -110 dB.

The DC voltages Δ ₁ and Δ ₂ described above are superimposed on the differential input voltages IN ₁ and IN ₂ of the first and second channels. From the third channel to the _Nth channel, DC voltages Δ _{3 to} ΔN are similarly superimposed to reduce the peak noise intensity to −120 dB.
I did it below.

Incidentally, the DC voltage described above does not need to be removed by a digital high-pass filter. For example, in place of the digital high-pass filter, a correction operation circuit may be provided downstream of the decimation filter to delete the data indicating the superposed DC voltage from the 20-bit data. Further, the digital low-pass filter in the decimation filter may be replaced with a digital band-pass filter, and when removing the high-frequency component, the superposed DC voltage component having a low frequency may be removed together.

A digital high-pass filter may be provided in the decimation filter separately from the digital low-pass filter. In short, the superimposed DC
Since the voltage is included as digital data in the digital signal output from the modulator or the decimation filter, if the digital signal is digitally processed and the data indicating the superimposed DC voltage component is deleted, the output digital signal is obtained. The data can be free from the influence of the DC voltage component.

The graphs in FIGS. 2A to 2C show the operating principle of the Σ-Δ modulation type AD converter of the present invention, and the values of the noise intensity are examples.

[0059]

As described above, by superimposing the DC voltage, the intensity of the noise due to the idling pattern can be reduced, so that a low noise Σ-Δ modulation type AD converter can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an example of the present invention.

FIGS. 2A to 2C are graphs for explaining the relationship between the peak noise frequency and the intensity DC voltage.

FIG. 3 (a): an example of a digital high-pass filter (b): a graph for explaining its settling time

FIG. 4 is a block diagram of a conventional Σ-Δ modulation type AD converter.

FIG. 5 is a graph of measured values showing the relationship between the peak noise frequency and the intensity.

FIG. 6 is a graph of measured values of frequency and intensity of peak noise with respect to DC voltage.

[Explanation of symbols]

2... 変 調 -Δ modulation type AD converter 4 ₁ , 4 ₂ …
DC voltage superposition device 11: modulator 12: decimation filter 13: digital high-pass filter

Claims (6)

[Claims] 1. A modulator for oversampling an input analog signal to generate a digital data sequence, and a decimation filter disposed downstream of the modulator for digitally processing the digital data sequence to remove high-frequency components. In the Σ-Δ modulation type AD converter having the following, DC is provided in a stage preceding the modulator or a signal sampling stage.
A Σ-Δ modulation type A / D converter, comprising a voltage superimposition circuit and configured to superimpose a DC voltage on the analog signal. 2. The method according to claim 1, wherein the decimation filter is configured to be able to remove the superimposed DC voltage component by digital processing.
Δ modulation type AD converter. 3. A correction operation circuit is provided at a stage subsequent to the decimation filter, and by performing an operation process on an output of the decimation filter, the superimposed DC voltage component can be removed from an output of the decimation filter. The Σ-Δ modulation type A / D converter according to claim 1, wherein: 4. The Σ-Δ modulation method according to claim 1, wherein a high-pass filter is provided at a stage subsequent to said decimation filter so as not to transmit said superimposed DC voltage component to a stage subsequent thereto. AD converter. 5. The Σ-Δ filter according to claim 4, wherein the high-pass filter is configured to switch from a state with a small attenuation factor to a state with a high attenuation factor at the start of operation.
Modulation type AD converter. 6. The method according to claim 6, wherein the switching of the attenuation factor is performed by the superimposed D.
6. The Σ-Δ modulation type AD converter according to claim 5, wherein the conversion is performed after the C voltage component is attenuated to a predetermined level.