JPH10173005A - Method for mounting flip chip - Google Patents
Method for mounting flip chipInfo
- Publication number
- JPH10173005A JPH10173005A JP8332087A JP33208796A JPH10173005A JP H10173005 A JPH10173005 A JP H10173005A JP 8332087 A JP8332087 A JP 8332087A JP 33208796 A JP33208796 A JP 33208796A JP H10173005 A JPH10173005 A JP H10173005A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- resin
- temp
- mounting
- under
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
- H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
- H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、プリント基板等の
実装基板にLSI等のチップをバンプを介して実装する
際に、実装基板とチップの間に充填材としてアンダーフ
ィルレジンを用いたフリップチップ実装方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flip chip using an underfill resin as a filler between a mounting board and a chip when mounting a chip such as an LSI on a mounting board such as a printed board via bumps. Regarding implementation method.
【0002】[0002]
【従来の技術】図3はフリップチップ実装方法の説明
図、図において、1はプリント基板、2はプリント配
線、3はバンプ接続部、4はパッド、5はチップ、7は
バンプ、8は基板バンプである。2. Description of the Related Art FIG. 3 is an explanatory view of a flip chip mounting method, in which 1 is a printed board, 2 is a printed wiring, 3 is a bump connection, 4 is a pad, 5 is a chip, 7 is a bump, and 8 is a board. It is a bump.
【0003】従来、アンダーフィルレジンを用いたフリ
ップチップ実装は、図3のフリップチップ実装方法に示
すように、プリント基板1等の実装基板上にICやLS
Iのチップ5上に形成されているアルミ等のパッド4上
に金線ボンディングで作製した金のバンプ7と、プリン
ト基板1上の銅等のプリント配線2上に形成したはんだ
等の基板バンプ8とを密着して、両者を200〜250
℃程度に加熱しながら接続して実装後、一旦、プリント
基板1とチップ5を常温に冷ましてから、再度加熱して
アンダーフィルレジン6をプリント基板1とチップ5と
の間にシリンジ等により注入するというアンダーフィリ
ング作業を行なっていた。Conventionally, flip-chip mounting using an underfill resin is performed by mounting an IC or LS on a mounting substrate such as a printed circuit board 1 as shown in a flip-chip mounting method shown in FIG.
A gold bump 7 formed by gold wire bonding on a pad 4 made of aluminum or the like formed on an I chip 5 and a board bump 8 made of solder or the like formed on a printed wiring 2 such as copper on a printed board 1 And 200 to 250
After connecting and mounting while heating to about ° C, the printed board 1 and the chip 5 are once cooled to room temperature, and then heated again to inject the underfill resin 6 between the printed board 1 and the chip 5 using a syringe or the like. I was doing underfilling work.
【0004】[0004]
【発明が解決しようとする課題】しかし、大集積なLS
Iのチップ5になると、チップの一片が15mm以上に
もなり、チップ5の周縁に配置されたバンプの大きさは
小さくなって90μm程度であり、図3(a)に示すよ
うに、シリコンのチップ5及びプリント基板1は熱膨張
係数がシリコンのチップ4ppm/℃、プリント基板3
0〜40ppm/℃と大きく異なるため、チップ5のサ
イズが15mm角といった具合に大きくなると、図4に
示す従来のフリップチップ実装温度プロファイルでは、
チップ実装後やアンダーフィルレジン注入後の常温まで
の自然冷却により、プリント基板1が収縮して、チップ
5とプリント基板1の接続部が200℃の温度差で12
0μmもずれるので、図5(a)に示すバンプ接続部3
が、図5(b)に示すように、直径90μmのバンプで
はプリント基板等の材質や板厚により、断線してしまう
ことがある。However, a large integrated LS
In the case of the chip 5 of I, one piece of the chip becomes 15 mm or more, and the size of the bumps arranged on the periphery of the chip 5 is reduced to about 90 μm. As shown in FIG. The chip 5 and the printed board 1 have a coefficient of thermal expansion of 4 ppm / ° C.
When the size of the chip 5 becomes large, for example, 15 mm square, the conventional flip chip mounting temperature profile shown in FIG.
The printed circuit board 1 shrinks due to natural cooling to room temperature after chip mounting or injection of the underfill resin, and the connection between the chip 5 and the printed circuit board 1 has a temperature difference of 200 ° C.
0 μm, the bump connection 3 shown in FIG.
However, as shown in FIG. 5B, a bump having a diameter of 90 μm may be disconnected due to the material and thickness of a printed circuit board or the like.
【0005】[0005]
【課題を解決するための手段】図2は本発明のフリップ
チップ実装の温度プロファイルである。本発明の課題を
解決する手段として、図2に一例を示すように、プリン
ト基板等の実装基板へLSI等のチップをバンプにより
加熱接続するフリップチップ実装から、アンダーフィリ
ング作業に入るまでの時間、アンダーフィルレジンをプ
リント基板とチップの間に注入するアンダーフィル作業
の間、アンダーフィル作業が終わってアンダーフィルレ
ジンを加熱硬化するまでの時間において、常に実装基板
をアンダーフィル作業温度以上の温度に保つように管理
する。FIG. 2 shows a temperature profile of flip chip mounting according to the present invention. As a means for solving the problem of the present invention, as shown in FIG. 2, as an example, a time from a flip chip mounting in which a chip such as an LSI is heated and connected to a mounting board such as a printed board by bumps, to a time when an underfilling operation is started, During the underfill operation, in which the underfill resin is injected between the printed circuit board and the chip, the mounting substrate is always kept at a temperature equal to or higher than the underfill operation temperature during the time from when the underfill operation is completed to when the underfill resin is heated and cured. To manage.
【0006】このことにより、フリップチップ実装か
ら、アンダーフィルレジンの硬化まで、常に温度の変化
が小さく、チップ、及びプリント基板等の実装基板の温
度も変化する差が少ないので、熱膨張変化も小さく、バ
ンプに加わるストレスを軽減することが出来る。[0006] Thus, from the flip chip mounting to the hardening of the underfill resin, the change in temperature is always small, and the change in the temperature of the mounting substrate such as the chip and the printed board is small, so that the change in thermal expansion is small. Thus, stress applied to the bumps can be reduced.
【0007】従って、アンダーフィルレジンが完全に硬
化して、チップとプリント基板等の実装基板との間を完
全に固着する迄、バンプ接続部のずれが起こらず、断線
は起こらない。Therefore, no displacement of the bump connection portion occurs and no disconnection occurs until the underfill resin is completely cured and the chip and the mounting board such as a printed board are completely fixed.
【0008】[0008]
【発明の実施の形態】図1は本発明の一実施例の説明図
であり、フリップチップ実装模式断面図、図2は本発明
のフリップチップ実装の温度プロファイルである。DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is an explanatory view of one embodiment of the present invention, and is a schematic cross-sectional view of flip-chip mounting, and FIG. 2 is a temperature profile of flip-chip mounting of the present invention.
【0009】図において、1はプリント基板、2はプリ
ント配線、3はバンプ接続部、4はパッド、5はチッ
プ、6はアンダーフィルレジンである。図1により本発
明の実施例として、LSIのチップ5のプリント基板1
へのフリップチップ実装方法について説明する。In the figure, 1 is a printed board, 2 is a printed wiring, 3 is a bump connection, 4 is a pad, 5 is a chip, and 6 is an underfill resin. FIG. 1 shows a printed circuit board 1 of an LSI chip 5 as an embodiment of the present invention.
A method of mounting a flip chip on a semiconductor device will be described.
【0010】チップ5は15mm角の大規模集積回路チ
ップを用い、このチップの表面の周縁には図3(a)に
示されたように、内部の回路素子に導通するアルミのパ
ッド4が多数形成されている。パッドの大きさ及びパッ
ド間の間隔は、いずれも100μmである。この上に金
のバンプ7が金線のボールボンディングで形成され、ボ
ンディング後、金銭を切断するので形状が図3(c)に
示すようなたまねぎ状のバンプ7となっている。The chip 5 is a large-scale integrated circuit chip of 15 mm square, and a large number of aluminum pads 4 are provided on the periphery of the surface of the chip, as shown in FIG. Is formed. Both the size of the pad and the interval between the pads are 100 μm. A gold bump 7 is formed thereon by ball bonding of a gold wire, and after bonding, the money is cut, so that the shape is an onion-shaped bump 7 as shown in FIG. 3C.
【0011】一方、プリント基板1上には複数個のチッ
プ5が搭載されているが、その1個に注目すると、搭載
するチップ5のバンプ7に対応する位置のプリント配線
2上にははんだ製の100μm径のはんだ等の基板バン
プ8が形成されている。On the other hand, a plurality of chips 5 are mounted on the printed circuit board 1. When paying attention to one of the chips 5, the solder wiring is provided on the printed wiring 2 at a position corresponding to the bump 7 of the mounted chip 5. A substrate bump 8 made of solder or the like having a diameter of 100 μm is formed.
【0012】LSIのチップ5のプリント基板1への接
続は、図3(d)に示すようにチップ5を裏返し、チッ
プ5上のバンプ7を下側にして基板バンプ8と位置合わ
せした後、チップ5を230℃に加熱しながら押圧し
て、図3(e)或いは図1(a)に示すように接着す
る。この時、チップ5とプリント基板1の間の隙間、す
なわちバンプ接続部3の高さは高々100μm前後とな
る。As shown in FIG. 3D, the connection of the LSI chip 5 to the printed circuit board 1 is performed by flipping the chip 5 upside down and aligning the bumps 7 on the chip 5 with the substrate bumps 8. The chip 5 is pressed while being heated to 230 ° C. and bonded as shown in FIG. 3 (e) or FIG. 1 (a). At this time, the gap between the chip 5 and the printed board 1, that is, the height of the bump connection portion 3 is at most about 100 μm.
【0013】バンプ接続部3形成後、アンダーフィルレ
ジン6注入の90℃の温度に至る間に、従来では25℃
前後の常温まで一旦放置して自然冷却していたが、本発
明では、この後、ひき続きプリント基板1ならびにチッ
プ5全体を120℃に絶えず保温するように設定する。After the bump connection portion 3 is formed, the temperature is conventionally 25 ° C. while the temperature reaches 90 ° C. for injecting the underfill resin 6.
In the present invention, the entire temperature of the printed circuit board 1 and the entire chip 5 is set to be constantly maintained at 120 ° C.
【0014】そして、アンダーフィルレジン6を小型の
シリンジ(注射器)で、毛細管現象を利用して、90℃
の温度でチップ5とプリント基板1の間の100μmの
隙間に注入すると、図1(b)に示すように、粘度の低
いアンダーフィルレジン6は表面張力によりチップ5の
下側部分にバンプ接続部3を埋めて広がる。Then, the underfill resin 6 is heated at 90 ° C. using a small syringe (syringe) by utilizing the capillary phenomenon.
When the resin is injected into the gap of 100 μm between the chip 5 and the printed circuit board 1 at the temperature shown in FIG. 1B, as shown in FIG. Fill 3 and spread.
【0015】アンダーフィルレジン6の注入後、従来は
一旦常温まで冷却していたのを、前と同様にチップ5な
らびにプリント基板1をアンダーフィルレジン6の注入
温度の90℃より高く、120℃に保温しておき、その
後アンダーフィルレジン6の硬化温度150℃で1〜2
時間加熱し、アンダーフィルレジン6を完全に固化す
る。After the injection of the underfill resin 6, the chip 5 and the printed circuit board 1 are cooled down to 120 ° C., which is higher than the injection temperature of the underfill resin 6 of 90 ° C. Keep the temperature, then set the curing temperature of the underfill resin 6 at 150 ° C for 1-2
Heating is carried out for a time to completely solidify the underfill resin 6.
【0016】この結果、プリント基板1上の基板バンプ
8とチップ5上のバンプ7はチップ5とプリント基板1
の熱膨張の差があっても、ずれることなくアンダーフィ
ルレジン6で固化され、その後で常温になっても、バン
プ接続部3がずれて断線することがなくなる。As a result, the substrate bumps 8 on the printed board 1 and the bumps 7 on the chip 5 are
Even if there is a difference in thermal expansion, the bump connection portion 3 is solidified by the underfill resin 6 without displacement, and thereafter, even at room temperature, is not disconnected due to displacement.
【0017】[0017]
【発明の効果】以上説明したように、LSI等のチップ
とプリント基板等の実装基板はフリップチップボンディ
ングからアンダーフィルレジンの硬化まで、温度差を最
小限に抑えて、結果としてフリップチップ実装部の熱ス
トレスを最小限に軽減できるため、チップと実装基板と
の互いのずれを生ずることなくバンプを介してチップと
実装基板とを完全に接続することが出来る。As described above, a chip such as an LSI and a mounting substrate such as a printed circuit board can minimize the temperature difference from flip chip bonding to curing of the underfill resin, and as a result, a flip chip mounting portion can be formed. Since the thermal stress can be reduced to a minimum, the chip and the mounting substrate can be completely connected via the bumps without causing the mutual displacement between the chip and the mounting substrate.
【図1】 本発明のフリップチップ実装模式断面図FIG. 1 is a schematic cross-sectional view of flip-chip mounting according to the present invention.
【図2】 本発明のフリップチップ実装温度プロファイ
ルFIG. 2 shows a flip chip mounting temperature profile of the present invention.
【図3】 フリップチップ実装方法FIG. 3 Flip chip mounting method
【図4】 従来例のフリップチップ実装温度プロファイ
ルFIG. 4 shows a conventional example of a flip chip mounting temperature profile.
【図5】 従来例のフリップチップ実装接続部断線図FIG. 5 is a sectional view of a conventional flip-chip mounting connection part.
1 プリント基板 2 プリント配線 3 バンプ接続部 4 パッド 5 チップ 6 アンダーフィルレジン 7 バンプ 8 基板バンプ DESCRIPTION OF SYMBOLS 1 Printed board 2 Printed wiring 3 Bump connection part 4 Pad 5 Chip 6 Underfill resin 7 Bump 8 Board bump
Claims (1)
ンダーフィルレジンを用いたフリップチップ実装方法に
おいて、 該チップ上のバンプを介して該実装基板上に該チップを
加熱接続し、該チップと該実装基板との間にアンダーフ
ィルレジンを加熱注入し、該アンダーフィルレジンが硬
化するまでの間、該チップならびに該実装基板をアンダ
ーフィルレジンの注入温度を越える温度に保つことを特
徴とするフリップチップ実装方法。1. A flip-chip mounting method using an underfill resin as a filling hardening material between a chip and a mounting substrate, wherein the chip is heated and connected to the mounting substrate via bumps on the chip. Heating and injecting an underfill resin between the substrate and the mounting substrate, and keeping the chip and the mounting substrate at a temperature exceeding the injection temperature of the underfill resin until the underfill resin is cured. Flip chip mounting method.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP33208796A JP3629345B2 (en) | 1996-12-12 | 1996-12-12 | Flip chip mounting method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP33208796A JP3629345B2 (en) | 1996-12-12 | 1996-12-12 | Flip chip mounting method |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH10173005A true JPH10173005A (en) | 1998-06-26 |
JP3629345B2 JP3629345B2 (en) | 2005-03-16 |
Family
ID=18251008
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP33208796A Expired - Lifetime JP3629345B2 (en) | 1996-12-12 | 1996-12-12 | Flip chip mounting method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP3629345B2 (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008047764A (en) * | 2006-08-18 | 2008-02-28 | Fujitsu Ltd | Method for mounting semiconductor element and method for manufacturing semiconductor device |
US7521799B2 (en) | 2005-04-19 | 2009-04-21 | Renesas Technology Corp. | Semiconductor device and method of manufacturing the same |
WO2011007531A1 (en) | 2009-07-17 | 2011-01-20 | 住友ベークライト株式会社 | Method for manufacturing electronic component and electronic component |
WO2016137733A1 (en) * | 2015-02-27 | 2016-09-01 | Qualcomm Incorporated | Compartment shielding in flip-chip (fc) module |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05327028A (en) * | 1992-05-26 | 1993-12-10 | Sharp Corp | Manufacture of optical device |
JPH08195414A (en) * | 1995-01-12 | 1996-07-30 | Toshiba Corp | Semiconductor device |
-
1996
- 1996-12-12 JP JP33208796A patent/JP3629345B2/en not_active Expired - Lifetime
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05327028A (en) * | 1992-05-26 | 1993-12-10 | Sharp Corp | Manufacture of optical device |
JPH08195414A (en) * | 1995-01-12 | 1996-07-30 | Toshiba Corp | Semiconductor device |
Cited By (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9576890B2 (en) | 2005-04-19 | 2017-02-21 | Renesas Electronics Corporation | Semiconductor device and method of manufacturing the same |
US8018066B2 (en) | 2005-04-19 | 2011-09-13 | Renesas Electronics Corporation | Semiconductor device and method of manufacturing the same |
US8822269B2 (en) | 2005-04-19 | 2014-09-02 | Renesas Electronics Corporation | Semiconductor device and method of manufacturing the same |
US9299681B2 (en) | 2005-04-19 | 2016-03-29 | Renesas Electronics Corporation | Semiconductor device and method of manufacturing |
US8928147B2 (en) | 2005-04-19 | 2015-01-06 | Renesas Electronics Corporation | Semiconductor device and method of manufacturing the same |
US10714415B2 (en) | 2005-04-19 | 2020-07-14 | Renesas Electronics Corporation | Semiconductor device and method of manufacturing the same |
US8314495B2 (en) | 2005-04-19 | 2012-11-20 | Renesas Electronics Corporation | Semiconductor device and method of manufacturing the same |
US10283444B2 (en) | 2005-04-19 | 2019-05-07 | Renesas Electronics Corporation | Semiconductor device and method of manufacturing the same |
US8575757B2 (en) | 2005-04-19 | 2013-11-05 | Renesas Electronics Corporation | Semiconductor device and method of manufacturing the same |
US8581410B2 (en) | 2005-04-19 | 2013-11-12 | Renesas Electronics Corporation | Semiconductor device and method of manufacturing the same |
US7791204B2 (en) | 2005-04-19 | 2010-09-07 | Renesas Technology Corp. | Semiconductor device and method of manufacturing the same |
US7521799B2 (en) | 2005-04-19 | 2009-04-21 | Renesas Technology Corp. | Semiconductor device and method of manufacturing the same |
US9831166B2 (en) | 2005-04-19 | 2017-11-28 | Renesas Electronics Corporation | Semiconductor device |
US9496153B2 (en) | 2005-04-19 | 2016-11-15 | Renesas Electronics Corporation | Semiconductor device and method of manufacturing the same |
JP2008047764A (en) * | 2006-08-18 | 2008-02-28 | Fujitsu Ltd | Method for mounting semiconductor element and method for manufacturing semiconductor device |
WO2011007531A1 (en) | 2009-07-17 | 2011-01-20 | 住友ベークライト株式会社 | Method for manufacturing electronic component and electronic component |
US8531028B2 (en) | 2009-07-17 | 2013-09-10 | Sumitomo Bakelite Co., Ltd. | Method for manufacturing electronic component, and electronic component |
KR20120041733A (en) | 2009-07-17 | 2012-05-02 | 스미또모 베이크라이트 가부시키가이샤 | Method for manufacturing electronic component, and electronic component |
WO2016137733A1 (en) * | 2015-02-27 | 2016-09-01 | Qualcomm Incorporated | Compartment shielding in flip-chip (fc) module |
CN107408551A (en) * | 2015-02-27 | 2017-11-28 | 高通股份有限公司 | Flip-chip(FC)Compartment shield in module |
US10242957B2 (en) | 2015-02-27 | 2019-03-26 | Qualcomm Incorporated | Compartment shielding in flip-chip (FC) module |
Also Published As
Publication number | Publication date |
---|---|
JP3629345B2 (en) | 2005-03-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6046077A (en) | Semiconductor device assembly method and semiconductor device produced by the method | |
US6258626B1 (en) | Method of making stacked chip package | |
US6560122B2 (en) | Chip package with molded underfill | |
JP3813797B2 (en) | Manufacturing method of semiconductor device | |
US7566586B2 (en) | Method of manufacturing a semiconductor device | |
US7906857B1 (en) | Molded integrated circuit package and method of forming a molded integrated circuit package | |
JP2004356529A (en) | Semiconductor device and method for manufacturing the semiconductor device | |
JP2001244362A (en) | Semiconductor device | |
JPH11274241A (en) | Producing method for semiconductor device | |
US20070170599A1 (en) | Flip-attached and underfilled stacked semiconductor devices | |
KR20040030659A (en) | Chip lead frames | |
US8193085B2 (en) | Method for fabricating flip-attached and underfilled semiconductor devices | |
US7687314B2 (en) | Electronic apparatus manufacturing method | |
JP3565092B2 (en) | Method for manufacturing semiconductor device | |
KR100674501B1 (en) | Method for attaching semiconductor chip using flip chip bonding technic | |
JPH10173005A (en) | Method for mounting flip chip | |
JP2014143316A (en) | Resin sealing method of flip chip component | |
JP4882570B2 (en) | Module manufacturing method and module manufactured thereby | |
WO2010134230A1 (en) | Semiconductor device and method for manufacturing same | |
US8598029B2 (en) | Method for fabricating flip-attached and underfilled semiconductor devices | |
JP2751427B2 (en) | Method for manufacturing semiconductor device | |
JP4752717B2 (en) | Module manufacturing method | |
KR100484889B1 (en) | Solderfill for semiconductor package assembly and manufacturing method the same | |
JP2001007503A (en) | Mounting method for electronic part | |
US20050051605A1 (en) | Process of manufacturing a solder-fill for applying to semiconductor package |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20040318 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20040330 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20040517 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20041207 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20041213 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20081217 Year of fee payment: 4 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20091217 Year of fee payment: 5 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20091217 Year of fee payment: 5 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20101217 Year of fee payment: 6 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20111217 Year of fee payment: 7 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20121217 Year of fee payment: 8 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20121217 Year of fee payment: 8 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20131217 Year of fee payment: 9 |
|
EXPY | Cancellation because of completion of term |