JPH10172887A - Method of exposure for photolithography process - Google Patents
Method of exposure for photolithography processInfo
- Publication number
- JPH10172887A JPH10172887A JP8331695A JP33169596A JPH10172887A JP H10172887 A JPH10172887 A JP H10172887A JP 8331695 A JP8331695 A JP 8331695A JP 33169596 A JP33169596 A JP 33169596A JP H10172887 A JPH10172887 A JP H10172887A
- Authority
- JP
- Japan
- Prior art keywords
- exposure
- semiconductor substrate
- reflectance
- wavelength
- line width
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、半導体素子の製造
に於いて用いられるフォトリソグラフィー工程の露光装
置に係わり、特にステップ アンド リピート法を用い
た縮小投影露光装置による露光方法に関するものであ
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an exposure apparatus in a photolithography process used in the manufacture of a semiconductor device, and more particularly to an exposure method using a reduced projection exposure apparatus using a step and repeat method.
【0002】[0002]
【従来の技術】従来技術のフォトリソグラフィー技術に
よるレジストパターン形成に至る行程としては図3に示
す方法が採られている。先ず始めに、工程ではウエー
ハ基板上に吸着した水分の脱離を目的とし、水(H
2 O)の沸点以上の温度設定にて脱水の為のベーク処理
を行う。2. Description of the Related Art As a process leading to the formation of a resist pattern by a conventional photolithography technique, a method shown in FIG. 3 is employed. First, in the process, water (H) is desorbed to remove water adsorbed on the wafer substrate.
A bake treatment for dehydration is performed at a temperature setting equal to or higher than the boiling point of 2 O).
【0003】次に、工程ではウエーハ基板上に塗布を
行うレジスト膜と基板との密着性を向上させる事を目的
とし、一般的にはHMDS(ヘキサメチルアンモニュウ
ムヘキサジシザラン)雰囲気中に晒す方法が採られてい
る。次に、工程ではレジストをウエーハ基板上に滴下
し、スピンコート法にて所望するレジスト膜厚の塗布形
成を行う。[0003] Next, in the process, in order to improve the adhesion between the resist film to be coated on the wafer substrate and the substrate, a method of exposing the wafer to an HMDS (hexamethylammonium hexadisizaran) atmosphere is generally used. Is adopted. Next, in the process, a resist is dropped on the wafer substrate, and a desired resist film thickness is formed by spin coating.
【0004】次に、工程ではプリベーク処理を施す事
により塗布形成を行ったレジスト膜中の不要なる残存溶
剤除去を目的としたベーク処理を行う。次に、工程で
の露光行程に於いては縮小投影露光装置を用い、(1)
アライメント計測・補正を行った後、(2)ウエーハ傾
斜成分の計測・補正、(3)フォーカス測定・補正を各
露光すべきショット毎に繰り返し行いつつ予め決定、入
力された一定露光量にて(5)露光を行う。[0004] Next, in the step, a bake treatment is performed for the purpose of removing unnecessary residual solvent from the resist film formed by applying a pre-bake treatment. Next, in the exposure step in the process, a reduction projection exposure apparatus is used, and (1)
After performing alignment measurement and correction, (2) measurement and correction of a wafer tilt component, and (3) focus measurement and correction are repeatedly performed for each shot to be exposed, and are determined in advance and input at a fixed exposure amount ( 5) Perform exposure.
【0005】次に、工程では熱拡散効果による定在波
消滅、ならびにレジストプロファイル向上を目的として
ベーク処理(一般的にはPEB(Post Expos
ure Bake)と称される)を行う。次に、工程
ではノボラック樹脂系を用いたポジ型レジストの場合に
はTMAH(テトラメチルアンモニュウムハイドロオキ
サイド)=2.38%からなるアルカリ水溶液を用いて
現像処理を行った後に純水洗浄処理を施す。Next, in the process, a baking process (generally, PEB (Post Expos) is performed for the purpose of eliminating standing waves due to a thermal diffusion effect and improving a resist profile.
ure bake). Next, in the step, in the case of a positive resist using a novolak resin system, a developing treatment is performed using an alkaline aqueous solution of TMAH (tetramethylammonium hydroxide) = 2.38%, and then a pure water cleaning treatment is performed. .
【0006】次に、工程では工程の純水洗浄にて生
じたウエーハ基板表面上の残存水分除去を目的としてプ
リベーク処理同様に水分の沸点以上からなるポストベー
ク処理を施す事でレジストパターン形成を生じせしめる
方法が採られていた。Next, in the process, a resist pattern is formed by performing a post-bake treatment at a temperature equal to or higher than the boiling point of water in the same manner as a pre-bake treatment in order to remove residual water on the wafer substrate surface generated by the pure water washing in the process. A method was adopted.
【0007】[0007]
【発明が解決しようとする課題】近年のサブミクロン領
域、ハーフミクロン領域に於いては微細化は基より、S
RAM,DRAM製品等ではメモリ容量の増加によるチ
ップサイズの拡大や、ウエーハ口径の拡大に伴いショッ
トサイズの拡大は増加の一途を辿っている。これらの進
展に伴い、チップ内、ショット内の寸法バラツキ抑制の
観点からステップ アンド リピート法による縮小投影
露光装置では像面傾斜及び湾曲については高精度化が求
められ、像面傾斜に関しては露光ショット単位で傾斜成
分の補正を行う方法(一般的にはチップレベリング、な
いしはダイバイダイチルト等の名称で呼称される)が採
られている。In the recent sub-micron and half-micron regions, miniaturization is not the first step but S
In RAM and DRAM products, etc., the increase in chip size due to the increase in memory capacity and the increase in shot size along with the increase in wafer diameter are steadily increasing. Along with these developments, from the viewpoint of minimizing dimensional variations in chips and shots, a reduction in projection and exposure apparatus using the step-and-repeat method requires higher precision for the image plane tilt and curvature, and for the image plane tilt, the exposure shot unit. (Generally referred to as chip leveling or die-by-die tilt).
【0008】しかし、レジスト寸法を決定付ける要因と
しては半導体基板上に成膜した酸化シリコン膜、窒化シ
リコン膜、多結晶ポリシリコン膜等の膜厚バラツキ、な
いしは組製状態により生じる半導体基板の反射率が大き
く影響しているが、現状の露光の際には各ウエーハ内の
露光量は一定露光量にて露光されているのが実情であ
る。However, factors that determine the resist dimensions include variations in the thickness of the silicon oxide film, silicon nitride film, polycrystalline polysilicon film, and the like formed on the semiconductor substrate, and the reflectivity of the semiconductor substrate caused by the assembled state. Has a large effect, but in the current exposure, the exposure amount in each wafer is actually exposed at a constant exposure amount.
【0009】したがって、前記ウエーハ基板上の反射率
の相違によりウエーハ内全ての露光ショットの寸法精度
低下が生じる事で規定寸法を逸脱し、特性の劣化、延い
ては歩留り低下といった問題を生じせしめていた。本発
明は上記事情に基づいてなされたものであり、工程数を
増加させる事無く反射率の異なる半導体基板上に於いて
も安定性ある寸法制御可能なフォトリソグラフィーの露
光方法を提供することを目的とするものである。[0009] Therefore, the dimensional accuracy of all the exposure shots in the wafer is reduced due to the difference in the reflectivity on the wafer substrate, thereby deviating from the specified size, causing problems such as deterioration of characteristics and a reduction in yield. Was. The present invention has been made based on the above circumstances, and an object of the present invention is to provide a photolithography exposure method which is stable and can be dimensionally controlled even on a semiconductor substrate having a different reflectance without increasing the number of steps. It is assumed that.
【0010】[0010]
【課題を解決するための手段】上記の目的を達成するた
めの本発明に係るフォトリソグラフィーの露光方法は、
半導体基板を順次脱水ベーク処理、HMDS処理、プリ
ベーク処理、レジストコート処理、露光、現像、ポスト
ベーク処理を行う事で所望寸法から成るレジストパター
ン形成を行う工程の一環として、ステップ アンド リ
ピート法を用いた縮小投影露光装置にてg線、i線、X
線、Krf等の露光波長の如何に係わらず特定単波長、
もしくは広帯域幅波長を用い、レチクルを透過、照射を
行う事で所望寸法の得られる露光を行うフォトリソグラ
フィーの露光方法に於いて、予め実験にて露光を行う半
導体基板の工程のウエーハを用い、反射率と線幅との相
関係数、及び露光量と線幅との相関係数を求め、これら
の相関係数より露光時の補正量を算出し、露光装置に入
力を行う工程と、ステップ アンド リピート法にて露
光を行う際、各露光ショットの露光に先立って各露光シ
ョット毎に半導体基板の反射率を投影レンズを透過した
状態(TTL ON LENS)で、もしくは透過しな
い状態(TTL OFF LENS)の何れかで測定す
る工程と、前記の工程で測定した反射率と前記補正量と
を用いて、各露光ショット単位で露光の補正を行って露
光を行う工程と、を具備するものである。To achieve the above object, an exposure method for photolithography according to the present invention comprises:
A step-and-repeat method was used as a part of a process of forming a resist pattern having desired dimensions by sequentially performing dehydration bake treatment, HMDS treatment, pre-bake treatment, resist coat treatment, exposure, development, and post-bake treatment on a semiconductor substrate. G-line, i-line, X
Line, a specific single wavelength regardless of the exposure wavelength such as Krf,
Alternatively, in a photolithography exposure method in which exposure is performed in a desired size by transmitting and irradiating a reticle using a wide-band wavelength, a wafer in a semiconductor substrate process in which an exposure is performed in advance through an experiment is performed by reflection. Calculating a correlation coefficient between the rate and the line width, and a correlation coefficient between the exposure amount and the line width, calculating a correction amount at the time of exposure from these correlation coefficients, and inputting the correction amount to the exposure apparatus; When performing exposure by the repeat method, the reflectance of the semiconductor substrate is transmitted through the projection lens (TTL ON LENS) or not transmitted (TTL OFF LENS) for each exposure shot prior to exposure of each exposure shot. And the step of performing exposure by performing exposure correction on each exposure shot unit using the reflectance measured in the above step and the correction amount. It is intended.
【0011】[0011]
【作用】反射率の異なる半導体基板上に同一寸法からな
るレジストパターン形成を行うにあたっては、露光量を
増減させる事で任意に制御可能である。依って、同一寸
法のえられる反射率の異なる半導体基板毎での露光量が
求められれば、縮小投影露光による各露光ショット単位
の露光前に反射率測定を行い、前記相関係数を露光量に
フィードバックする事により容易に同一寸法から成るレ
ジストパターンを反射率の異なる半導体基板内全面に均
一に形成可能となる。When a resist pattern having the same dimensions is formed on semiconductor substrates having different reflectivities, the resist pattern can be arbitrarily controlled by increasing or decreasing the amount of exposure. Therefore, if the exposure amount for each of the semiconductor substrates having the same dimensions and different reflectances is obtained, the reflectance measurement is performed before exposure of each exposure shot unit by reduced projection exposure, and the correlation coefficient is converted to the exposure amount. By providing feedback, a resist pattern having the same dimensions can be easily formed uniformly over the entire surface of a semiconductor substrate having different reflectivities.
【0012】[0012]
【発明の実施の形態】本実施形態に於いては、露光装置
にi線波長を用いたステップ アンド リピート法によ
る縮小投影露光装置を用いた場合を例に採り、グローバ
ルアライメント方法(統計計算による重ね合せ補正)を
用い、且つ各露光ショット単位で露光ショット領域の傾
斜補正を行うレベリング補正を行う場合の露光方法を例
に採り説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In the present embodiment, a case where a step-and-repeat reduction projection exposure apparatus using an i-line wavelength is used as an exposure apparatus is taken as an example, and a global alignment method (overlapping by statistical calculation) is used. A description will be given of an example of an exposure method in the case of performing leveling correction for correcting the tilt of an exposure shot area in units of exposure shots.
【0013】全般的な工程フローは図1に示す通りであ
る。本実施形態に於けるレジスト膜厚設定は、レジスト
膜自体が抱えているバルク効果、膜内多重反射効果等と
言った定在波効果、ならびに半導体基板上に形成された
段差構造を考慮して1.2ミクロン膜厚に設定を行った
場合を例に採り記述する。尚、工程から工程、及び
工程から工程までの処理は、図3に示す従来のもの
と同様であるので、その詳細な説明は省略する。The overall process flow is as shown in FIG. In the present embodiment, the resist film thickness is set in consideration of the bulk effect of the resist film itself, a standing wave effect such as an intra-film multiple reflection effect, and a step structure formed on a semiconductor substrate. The case where the film thickness is set to 1.2 microns will be described as an example. The process from step to step and the process from step to step are the same as the conventional one shown in FIG. 3, and thus detailed description thereof will be omitted.
【0014】工程の露光に際しては先ず始めに、
(1)工程ではウエーハ内に任意設定を行ったショット
のアライメント計測を行った後に統計計算にてウエーハ
の収縮率、X、Y方向のズレ量を割出し、補正を行う。
(2)工程では、各露光ショット単位にて露光領域の傾
斜成分の計測を行い、ウエーハ基板を保持しているウエ
ーハステージを動作させる事で最も平坦度が良好な状態
に傾斜補正を行う。At the time of the exposure in the process, first,
In the step (1), alignment measurement is performed on shots that have been arbitrarily set in the wafer, and then the shrinkage ratio of the wafer and the amounts of displacement in the X and Y directions are calculated and corrected by statistical calculation.
In the step (2), the inclination component of the exposure area is measured for each exposure shot, and the wafer stage holding the wafer substrate is operated to perform the inclination correction so that the flatness is the best.
【0015】(3)工程では、投影レンズを透過した状
態(TTL ON LENS)にて計測を行うか、もし
くは透過しない状態(TTL OFF LENS)の何
れかの方法にて各露光ショットの最適フォーカス点の計
測を行い、ウエーハ基板を保持しているウエーハステー
ジを上下駆動させる事でベストフォーカス状態に保持す
る。In the step (3), the optimum focus point of each exposure shot is measured in a state where the measurement is performed in a state where the light is transmitted through the projection lens (TTL ON LENS) or in a state where the light is not transmitted (TTL OFF LENS). And the wafer stage holding the wafer substrate is moved up and down to maintain the best focus state.
【0016】次の工程が本実施例の最も特徴とする処で
あり、(4)工程では縮小投影露光装置に反射率測定機
構を設け、投影レンズを透過した状態(TTL ON
LENS)にて計測を行うか、もしくは透過しない状態
(TTL OFF LENS)の何れかの方法にて各露
光ショット毎の反射率の測定を行う。この際の計測とし
ては、レジスト膜の感光を防止する事を目的とし、露光
波長とは異なる単波長、もしくは広帯域幅の波長を用い
て計測を行う。The next step is the most characteristic of this embodiment. In the step (4), a reduction projection exposure apparatus is provided with a reflectance measuring mechanism, and the light is transmitted through the projection lens (TTL ON).
LENS), or the reflectance of each exposure shot is measured by any method of not transmitting (TTL OFF LENS). At this time, the measurement is performed using a single wavelength different from the exposure wavelength or a wavelength having a wide bandwidth for the purpose of preventing exposure of the resist film.
【0017】次に、予め実験にて求めた反射率と線幅の
相関関係、及び露光量変化による線幅変動率(露光量と
線幅との相関関係)から露光補正係数を求め、露光装置
の露光制御系に入力を行っておき、本補正係数を基に適
正露光量を自動計算した後に(5)露光工程を行う。前
記補正方法の1実施例として多結晶ポリシリコン膜を成
膜した半導体基板上での実験結果による例を採り図2を
用いて説明する。Next, an exposure correction coefficient is obtained from the correlation between the reflectance and the line width obtained in advance by experiments and the line width variation rate (correlation between the exposure amount and the line width) due to the change in the exposure amount. Is input to the exposure control system, and an appropriate exposure amount is automatically calculated based on this correction coefficient, and then the exposure step (5) is performed. As an example of the correction method, an example based on experimental results on a semiconductor substrate on which a polycrystalline polysilicon film is formed will be described with reference to FIG.
【0018】図2は、本実験で行った図1のプロセス条
件の基で行った場合の前記半導体基板上に於ける同一露
光量(本実験では150mj/cm2 にて露光)で露光
を行った際の反射率毎のレジスト寸法を示す。ここで、
例えば50%反射率条件に於ける1.0μm線幅が得ら
れる露光量は150mj/cm2 であり、且つ本基板上
での反射率5%変化による線幅変化量△X=0.02μ
mとなる。尚、0.02μmの変化をさせるのに必要な
露光量は予め50%反射率の基板を用いた実験結果から
5mj/cm2 である事を求めている(図提示無し)。FIG. 2 shows an exposure at the same exposure dose (exposure at 150 mj / cm 2 in this experiment) on the semiconductor substrate when it is carried out under the process conditions of FIG. 1 conducted in this experiment. Shows the resist dimensions for each reflectance at the time of the exposure. here,
For example, the exposure at which a line width of 1.0 μm can be obtained under the condition of 50% reflectance is 150 mj / cm 2 , and the line width variation ΔX = 0.02 μm due to a 5% change in reflectance on the substrate.
m. Incidentally, it is required that the exposure amount necessary for changing the thickness by 0.02 μm is 5 mj / cm 2 in advance based on an experimental result using a substrate having a reflectance of 50% (not shown).
【0019】したがって、50%反射率基板の上で1.
0μm寸法を得る事を基準としたときには、反射率変化
に伴う各露光ショット単位の適正露光量は、上記のよう
にして求めた補正係数を使用し、下記公式により求める
事が出来る。 各露光ショット毎の適正露光量=150mj/cm2−
〔((A−50)/5)×5〕 (ここで、Aは測定した反射率である。) 但し、該公式は本実施例での1例であり、使用するレジ
スト膜厚条件、ベーク条件、現像条件、ならびに使用す
る縮小投影露光装置により異なる為に一律では無い為に
実技の上では予め実験により各々の諸条件で求める必要
がある。Therefore, on a 50% reflectance substrate, 1.
On the basis of obtaining a size of 0 μm, an appropriate exposure amount for each exposure shot due to a change in reflectance can be obtained by the following formula using the correction coefficient obtained as described above. Proper exposure amount for each exposure shot = 150 mj / cm 2-
[((A−50) / 5) × 5] (where A is the measured reflectivity.) However, this formula is an example in the present embodiment, and the resist film thickness conditions used, baking Since the conditions, development conditions, and the size of the reduction projection exposure apparatus to be used vary depending on the conditions, it is necessary to obtain experimentally various conditions in advance in experiments.
【0020】尚、上記実施例に於いてはグローバルアラ
イメントを用いた場合を例に採り説明したが、該アライ
メントについては各露光ショット単位でアライメント計
測、補正を行うダイ バイ ダイ法を用いても良い。
又、同じく露光すべき半導体基板の傾斜補正として露光
ショット単位の補正を例に採り説明したが、ウエーハ全
面の傾斜補正を行うグローバルチルト、ないし傾斜補正
を行わない場合の何れに於いても適用可能であり、最も
特徴とすべきは露光直前の状態にて傾斜補正を行う点で
あり、これを行う事によりステージ駆動の行われない最
終状態で、露光についての計測、補正を行う点にある。Although the above embodiment has been described taking the case of using global alignment as an example, the alignment may be performed by a die-by-die method for performing alignment measurement and correction for each exposure shot. .
Also, the explanation has been given by taking as an example the correction of the exposure shot unit as the tilt correction of the semiconductor substrate to be exposed. However, the present invention can be applied to any of the global tilt for correcting the tilt of the entire wafer or the case where the tilt correction is not performed. The most characteristic point is that tilt correction is performed in a state immediately before exposure. By performing this, measurement and correction of exposure are performed in a final state in which stage driving is not performed.
【0021】[0021]
【発明の効果】本発明に依れば、基板上に成膜、ないし
は蒸着形成された被膜のウエーハ内各領域に於ける反射
率が異なる場合に於いても、各露光ショット単位で同一
寸法が得られる露光量補正を行った上で露光を行う事が
可能となり、ウエーハの大口径化は基より、下層被膜の
反射率のバラツキに左右される事無くウエーハ全面、な
らびにウエーハ間のレジスト寸法の安定化を図る事が可
能と成り、寸法制御精度の向上による各製品チップ間の
素子特性の均一化による信頼性、ならびに歩留りの向上
を図る効果が得られる。According to the present invention, even when the film formed on the substrate or the film formed by vapor deposition has a different reflectance in each region in the wafer, the same size is used for each exposure shot unit. Exposure can be performed after performing the obtained exposure correction, and the increase in the diameter of the wafer, from the basis, does not depend on the variation in the reflectance of the lower layer film, the entire wafer, and the resist dimension between the wafers It is possible to achieve stabilization, and it is possible to obtain the effect of improving the reliability and the yield by making the element characteristics uniform among the product chips by improving the dimensional control accuracy.
【図1】本発明のフォトリソグラフィー行程を示す図で
ある。FIG. 1 is a diagram showing a photolithography process of the present invention.
【図2】半導体基板上で同一露光量で露光を行ったとき
の反射率と線幅寸法との相関関係を示すグラフである。FIG. 2 is a graph showing a correlation between a reflectance and a line width dimension when exposure is performed at the same exposure amount on a semiconductor substrate.
【図3】従来方法によるフォトリソグラフィー行程を示
す図である。FIG. 3 is a diagram showing a photolithography process according to a conventional method.
Claims (4)
DS処理、プリベーク処理、レジストコート処理、露
光、現像、ポストベーク処理を行う事で所望寸法から成
るレジストパターン形成を行う工程の一環として、ステ
ップ アンドリピート法を用いた縮小投影露光装置にて
g線、i線、X線、Krf等の露光波長の如何に係わら
ず特定単波長、もしくは広帯域幅波長を用い、レチクル
上のパターンを半導体基板上に縮小投影する露光を行う
フォトリソグラフィーの露光方法に於いて、 予め、所望工程の半導体基板を用い、前記半導体基板の
反射率と線幅との相関係数、及び露光量と線幅との相関
係数を求め、相互の相関係数から半導体基板の反射率が
変化した際に、同一寸法を得る為の露光量の増減を行う
補正量を算出した上で、露光装置の露光制御系に設定を
行う工程と、 ステップ アンド リピート法にて露光を行う際、各露
光ショットの露光に先立って各露光ショット毎に半導体
基板の反射率を投影レンズを透過した状態(TTL O
N LENS)で、もしくは透過しない状態(TTL
OFF LENS)の何れかで測定する工程と、 前記の工程で測定した反射率と前記補正量とを用いて、
各露光ショット単位で露光の補正を行って露光を行う工
程と、 を具備することを特徴とするフォトリソグラフィーの露
光方法。1. A semiconductor substrate is sequentially subjected to a dehydration bake treatment,
As a part of the process of forming a resist pattern having desired dimensions by performing a DS process, a pre-bake process, a resist coat process, an exposure, a development, and a post-bake process, a g-line is produced by a reduction projection exposure apparatus using a step-and-repeat method. In a photolithography exposure method, a specific single wavelength or a wide bandwidth wavelength is used regardless of the exposure wavelength such as i-line, X-ray, Krf, etc. and the pattern on the reticle is projected onto a semiconductor substrate in a reduced size. In advance, using a semiconductor substrate in a desired process, a correlation coefficient between the reflectance and the line width of the semiconductor substrate and a correlation coefficient between the exposure amount and the line width are obtained, and the correlation coefficient of the semiconductor substrate is obtained from the mutual correlation coefficient. A step of calculating a correction amount for increasing or decreasing the exposure amount to obtain the same dimension when the reflectance changes, and setting the exposure control system of the exposure apparatus; and When performing the exposure by Pete method, transmitted through the projection lens the reflectivity of the semiconductor substrate for each of the exposure shot prior to the exposure of each exposure shot state (TTL O
NLENS) or non-transmitting (TTL
OFF LENS), and using the reflectance measured in the above step and the correction amount,
A step of performing exposure by performing exposure correction for each exposure shot, and an exposure method for photolithography.
長、もしくは広帯域幅波長を用い、レチクル上のパター
ンを半導体基板上に縮小投影する露光を行う縮小投影露
光装置において、 ステップ アンド リピート法にて露光を行う際に、各
露光ショットの露光に先立って各露光ショット毎に前記
半導体基板の反射率を測定する反射率測定手段と、 予め、前記半導体基板の反射率とレジストの線幅との相
関係数、及び露光量とレジストの線幅との相関係数を求
め、これらの相関係数を用いて、前記反射率測定手段に
よって測定した反射率に応じて露光量の補正を行う補正
手段と、 を具備することを特徴とする縮小投影露光装置。2. A reduction projection exposure apparatus for performing exposure for reducing and projecting a pattern on a reticle onto a semiconductor substrate by using a specific single wavelength such as g-line, i-line, X-ray, or Krf or a wide-band wavelength. When performing exposure by an AND repeat method, prior to exposure of each exposure shot, reflectance measurement means for measuring the reflectance of the semiconductor substrate for each exposure shot, and in advance, the reflectance of the semiconductor substrate and the resist A correlation coefficient between the line width and a correlation coefficient between the exposure amount and the line width of the resist is obtained, and using these correlation coefficients, the correction of the exposure amount according to the reflectance measured by the reflectance measuring means. And a correcting means for performing the following.
なる波長の単波長又は広帯域幅の波長を用いて反射率の
測定を行うことを特徴とする請求項2記載の縮小投影装
置。3. The reduction projection apparatus according to claim 2, wherein said reflectance measuring means measures the reflectance using a single wavelength having a wavelength different from the exposure wavelength or a wavelength having a wide bandwidth.
反射率が異なることに起因するレジストの線幅の増減を
補正するものであることを特徴とする請求項2又は3記
載の縮小投影装置。4. The reduction projection according to claim 2, wherein the correction of the exposure amount corrects an increase or a decrease in a line width of the resist due to a difference in reflectance of the semiconductor substrate. apparatus.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8331695A JPH10172887A (en) | 1996-12-12 | 1996-12-12 | Method of exposure for photolithography process |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8331695A JPH10172887A (en) | 1996-12-12 | 1996-12-12 | Method of exposure for photolithography process |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH10172887A true JPH10172887A (en) | 1998-06-26 |
Family
ID=18246557
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8331695A Pending JPH10172887A (en) | 1996-12-12 | 1996-12-12 | Method of exposure for photolithography process |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH10172887A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9885960B2 (en) | 2013-12-26 | 2018-02-06 | Toshiba Memory Corporation | Pattern shape adjustment method, pattern shape adjustment system, exposure apparatus, and recording medium |
-
1996
- 1996-12-12 JP JP8331695A patent/JPH10172887A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9885960B2 (en) | 2013-12-26 | 2018-02-06 | Toshiba Memory Corporation | Pattern shape adjustment method, pattern shape adjustment system, exposure apparatus, and recording medium |
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