JPH10172285A - Semiconductor storage - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor storage for reducing a consumption current in high-voltage operation state and compensating for an operation in low-voltage operation state. SOLUTION: When an address is inputted to an address input part 22, address transition signals ATDS0-ATDSn are outputted from address transition detection circuits ATD0-ATDn to a synchronization signal generation circuit 33. Then, the synchronization signal generation circuit 33 operates a first precharge circuit 25 and performs precharging for a memory cell array 24. A precharge end detection circuit 27 detects whether precharging is sufficient or not, and a precharge control circuit 37 operates a second precharge circuit 26 for performing precharging at a higher voltage level than the first precharge circuit 25 when precharging is not sufficient, namely in a low-voltage operation state.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device which is suitably used for a RAM (random access memory) or the like, and which performs precharge to read or write data in a memory cell.

[0002]

2. Description of the Related Art Conventionally, a semiconductor memory device such as an SRAM (Static Random Access Memory) precharges a bit line of a memory cell when an address is input to an address input terminal, and inputs the input address. Processing such as activating the word line based on the
Data is read from or written to the memory cell.

FIG. 8 is a block diagram showing an internal configuration of a conventional semiconductor memory device, and FIG. 9 is a time chart showing a data reading operation of the conventional semiconductor memory device.

The conventional semiconductor memory device 1 includes address input terminals A0 to An, address transition detection circuits ATD0 to AT
Dn, synchronization signal generation circuit 2, precharge circuit 3, memory cell array 4, dummy memory cell group 5, precharge end detection circuit 6, column decoder 7, row decoder 8, input / output circuit 9, input / output terminal 10, address buffer 11 and a column gate 12.

Address transition detection circuits ATD0 to ATDn
Are address input terminals A0 to A to which an address is input.
n. For example, when reading data, if an address designating a data storage position is input to the address input terminals A0 to An (see FIG. 9A), the address transition detection circuits ATD0 to ATD0.
ATDn is an address transition signal (ATDS0 to ATDS).
n) is output to the synchronization signal generating circuit 2 (see FIG. 9B).

When the address transition signals (ATDS0 to ATDSn) are applied, the synchronization signal generation circuit 2 outputs a precharge control signal (PRC) to the precharge circuit 3 (see FIG. 9C). When the precharge signal (PRC) is applied, the precharge circuit 3 performs precharge by applying a voltage to bit lines in the column direction of the memory cell array 4 and the dummy memory cell group 5. The precharge end detection circuit 6 detects whether the precharge of the bit line in the column direction of the dummy memory cell group 5 has reached a predetermined voltage level, and sends a precharge end signal ( PRCEND) (FIG. 9)
(D)).

When receiving the precharge end signal (PRCEND), the synchronization signal generating circuit 2 outputs a decoder activation signal (DEN) to the column decoder 7 and the row decoder 8 (see FIG. 9 (e)). Row decoder 8 outputs a word line selection signal (WL) based on the address temporarily stored in address buffer 11 (FIG. 9).
(F)). At this time, the column decoder 7 controls the column gate 12 to read the data DA0 to DAm stored at the input address from the input / output terminal 10 via the input / output unit 9 (FIG. 9). (G)).

[0008]

The above-mentioned semiconductor memory device 1 is required to operate within a guaranteed voltage range of 2 V to 5 V, in particular, and the power consumption has been reduced with the spread of portable information processing devices. Is planned.

The semiconductor memory device 1 includes an n-channel type MO in the precharge circuit 3 in order to reduce current consumption.
The bit line of the memory cell array 4 is precharged by using the S transistor. For example, the gate electrode of an n-channel MOS transistor has Vtn (0.8
It is assumed that the precharge operation described above is performed by applying the voltage level V). At this time, the voltage level precharged to the bit line is the power supply voltage Vcc-V
tn (0.8 V) -α. Note that α is determined by the characteristics of the substrate on which the semiconductor memory device 1 is formed. Therefore, the high voltage operation state (power supply voltage Vcc = 5)
V), the voltage level of the bit line is about 3.6 V, and the current consumption is reduced.

However, in the low voltage operation state (power supply voltage Vcc = 2 V), the voltage level of the bit line is at least the power supply voltage Vcc necessary for precharging the bit line.
Voltage level is not more than half of Therefore, there is a problem that the precharge end state of the bit line cannot be detected and the data read operation cannot be performed.

In order to solve this problem, it is conceivable to use a p-channel MOS transistor for setting the voltage level of the bit line to the level of the power supply voltage Vcc for the precharge circuit 3. However, this precharge circuit 3
Has a problem that the current consumption increases because the voltage level of the bit line is set to the voltage level of the power supply voltage Vcc even in the high voltage operation state (power supply voltage Vcc = 5 V).

Japanese Patent Publication No. 4-56399 discloses a technique for equalizing a bit line by utilizing the difference between the p-channel type and n-channel type characteristics of a MOS transistor. However, this technique does not reduce current consumption, but is a technique for improving the processing speed of data reading and writing.

An object of the present invention is to provide a semiconductor memory device which reduces current consumption in a high voltage operation state and compensates for an operation in a low voltage operation state.

[0014]

In order to solve the above-mentioned problems, a semiconductor memory device according to the present invention comprises: a memory unit having a memory cell connected to a bit line and a word line; First precharge means for performing precharge, second precharge means for performing precharge on the bit line at a higher voltage level than the first precharge means, and completion of precharge for the bit line. Detecting means for detecting, and when the detecting means does not detect completion of precharging of the first precharging means, control means for causing the bit line to precharge by the second precharging means. And

In the semiconductor memory device of the present invention, the memory means having memory cells connected to the bit line and the word line, and the memory means and the bit line of the dummy memory cell are precharged. Precharge means, second precharge means for precharging the bit line of the storage means at a higher voltage level than the first precharge means, and precharge of the bit line of the dummy memory cell is completed Detecting means for detecting the completion of precharging by the first precharging means, and controlling means for causing the bit line of the storage means to precharge by the second precharging means when the detecting means does not detect completion of precharging by the first precharging means , Is provided.

The operating state of the semiconductor memory device is as follows.
In some cases, it may be in a high voltage operation state or in a low voltage operation state. According to the above configuration, for example, when an address is input, the first precharge unit precharges the bit line of the storage unit. When the operation state of the semiconductor memory device is a high voltage operation state, the detection means detects that the precharge performed on the bit line of the storage means is completed. That is, the detection means detects that the precharge voltage level of the bit line of the storage means is equal to or higher than a predetermined voltage level. Thus, there is no need to precharge the bit line of the storage means using the second precharge means. Therefore, current consumption can be reduced because the second precharge means for performing precharge at a high voltage level is not used. On the other hand, when the operation state of the semiconductor memory device is the low-voltage operation state, the detection unit does not detect that the precharge performed on the bit line of the storage unit is completed. That is, the detection means cannot detect that the precharge voltage level of the bit line of the storage means is equal to or higher than a predetermined voltage level. At this time, the control means uses the second precharge means to precharge the bit line of the storage means. Therefore, when the precharge to the bit line of the storage means using the first precharge means is not completed, the second
Since the precharge is performed by using the precharge means, the precharge can be reliably performed on the bit line of the storage means. Further, by detecting whether or not the precharge of the bit line of the dummy memory cell of the storage means is completed, the influence of the detection means on the precharge of the bit line of the storage means can be prevented. That is, it is possible to prevent the voltage level of the precharge from being lowered by the detection means. Therefore, it is possible to more reliably precharge the bit lines of the storage means.

Further, the detection means may detect whether the precharge is completed within a predetermined time after the precharge of the first precharge means is started. The detection means detects whether the precharge of the first precharge means is completed. Specifically, the detecting means includes:
The time from the start of the precharge to the completion thereof is held, and the time elapses from the start of the precharge of the first precharge unit to the bit line of the storage unit or the dummy memory cell. Until the completion of the precharge is detected.

The detecting means may detect in advance whether or not the precharging of the first precharging means is completed. Specifically, when the power is turned on, the detection unit detects whether the precharge of the first precharge unit is completed. Then, when the completion is detected, the control means immediately uses the second precharge means when actually precharging the bit line of the storage means.

Further, the semiconductor memory device of the present invention comprises a storage means including a memory cell connected to a bit line and a word line; a first precharge means for precharging the bit line; A second precharge means for precharging the bit line at a voltage level higher than that of the first precharge means, and a second precharge means for precharging the bit line of the pseudo dummy memory cell at the same voltage level as the first precharge means. Pseudo precharge means for performing charging in advance; pseudo detection means for detecting whether or not precharging of the bit line of the pseudo dummy memory cell is completed; and when the pseudo detection means does not detect completion of precharge, Control means for precharging the bit line by a second precharge means.

According to the above arrangement, the bit line of the storage means is precharged using the first precharge means. When the operation state of the semiconductor memory device is the high-voltage operation state, the precharge of the bit line of the storage means is completed. On the other hand, when the operation state of the semiconductor memory device is the low voltage operation state, the precharge of the bit line of the storage unit by the first precharge unit is not completed. However, the pseudo-detection means,
It is detected in advance (for example, when the power is turned on) that the precharge by the pseudo precharge means is not completed. That is, it is detected that the precharge by the first precharge means is not completed. Therefore, the control means immediately uses the second precharge means when precharging the bit line. Thus, the processing operation can be performed at a higher speed than the processing operation of the semiconductor memory device that requires a predetermined time to perform the precharge on the bit line using the second precharge means.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor memory device according to the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 is a block diagram showing an internal configuration of a semiconductor memory device according to a first embodiment. The semiconductor memory device 20 includes an address input unit 22, a synchronization signal generation circuit 33, a delay circuit 35, a precharge control circuit 3,
7, memory cell array 24, first precharge circuit 2
5, a second precharge circuit 26, a precharge end detection circuit 27, a data input / output unit 28, and a decode unit 29.

The address input section 22 includes address input terminals A0 to An, address transition detection circuits ATD0 to ATDn.
And an address buffer 31. Address input section 2
2 temporarily stores the addresses input from the address input terminals A0 to An in the address buffer 31, and outputs address transition signals (ATDS0 to ATDSn) from the address transition detection circuits ATD0 to ATDn to the synchronization signal generation circuit 33. I do. The address transition detection circuits ATD0 to ATDn detect a change in the input address and detect the address transition signals (ATDS0 to ATDSn).
n) is output.

The decoding unit 29 includes an X decoder 39 and a Y decoder
It is composed of a decoder 41. Then, the X decoder 39 and the Y decoder 41 of the decoding unit 29 receive an address from the address buffer 31 of the address input unit 22 when receiving the decode activation signal (DEN) from the synchronization signal generation circuit 33. The X decode 39 selects a word line in the row direction based on the address and outputs a word line select signal (WL) to the memory cell array 24. The Y decode 41 uses the data input / output unit 2 based on the address.
A selection signal is supplied to eight Y gates 43 (described later).

The memory cell array 24 includes a plurality of memory cells for storing data arranged vertically (Y: column direction) and horizontally (X: row direction). One memory cell is connected to a pair of bit lines formed in the column direction and one word line formed in the row direction.

When the address transition signals (ATDS0 to ATDSn) are applied, the synchronization signal generation circuit 33 activates the first precharge circuit 25 (starts precharge).
1) is given to the first precharge circuit 25 and the delay circuit 35. Further, the synchronization signal generation circuit 33 outputs a precharge end detection signal (PRC) from the precharge end detection circuit 27.
END). The precharge end detection signal (PRCEND) is a signal indicating that the precharge voltage level of the bit line of the memory cell array 24 has been detected to be equal to or higher than a predetermined voltage level (that is, the precharge has been completed). . When the precharge end detection signal (PRCEND) is applied, the synchronization signal generation circuit 33 outputs a decode activation signal (DEN) to the decode unit 29.

The delay circuit 35 supplies a delay signal (PRCHD) to the precharge control circuit 37 when a predetermined time T1 has elapsed since the first precharge control signal (PRCH1) was supplied.

The precharge control circuit 37 outputs a precharge end detection signal (P
RCEND) and the delay signal (PRCHD) from the delay circuit 35. Precharge control circuit 3
7 is a second precharge control signal (PRCH2) that activates the second precharge circuit 26 when the delay signal (PRCHD) is supplied and the precharge end detection signal (PRCEND) is not supplied. To the precharge circuit 26. On the other hand, when the delay signal (PRCHD) is given, the precharge control circuit 37 outputs the precharge end detection signal (PRCEN).
When D) is given, the second precharge control signal (PRCH2) is not output. That is, the precharge control circuit 37 operates the memory cell array 24 within the predetermined time T1.
When the voltage level of the precharge of the bit line is not higher than the predetermined level (that is, when the precharge is not completed)
Outputs a second precharge control signal (PRCH2) for activating the second precharge circuit 26.

The first precharge circuit 25 includes an n-channel MOS transistor for precharge provided for each bit line of the memory cell array 24 and an n-channel MOS transistor for equalization provided for a pair of bit lines. Type MOS transistor. When the first precharge control signal (PRCH1) is supplied from the synchronization signal generation circuit 33, each precharge MOS transistor of the first precharge circuit 25 uses the applied power supply voltage Vcc to generate the memory cell array 24. Is precharged for each bit line. MOS for equalization
The transistor controls the first precharge control signal (PR
When CH1) is given, the potentials of the pair of bit lines are made equal.

The second precharge circuit 26 is connected to the first
The configuration is the same as that of the precharge circuit 25 in which the n-channel MOS transistor for precharge is replaced with a p-channel MOS transistor, and the memory cell array 24 is arranged in parallel with the first precharge circuit 25.
Are connected to each bit line. Each precharge MOS transistor of the second precharge circuit 26 is
When the precharge control signal (PRCH2) is given,
Precharge is performed on each bit line of the memory cell array 24 using the applied power supply voltage Vcc. When the second precharge control signal (PRCH2) is supplied, the equalizing p-channel MOS transistor equalizes the potentials of the pair of bit lines.

The precharge end detection circuit 27 detects whether the precharge voltage level of the bit line of the memory cell array 24 is higher than the detection voltage level. When the precharge voltage level is higher than the detection voltage level, the precharge end detection signal (PRCEND) is output to the synchronization signal generation circuit 33 and the precharge control circuit 37.

The data input / output unit 28 is a Y gate 4 for reading or writing data in the memory cell array 24.
3, an input / output circuit 45 including a sense amplifier and a write circuit, and an input / output terminal 44 for inputting / outputting data. Then, the data input / output unit 28 reads or writes data in the memory cell array 24 according to the selection signal given from the Y decoder 41.

Next, the read operation of semiconductor memory circuit 20 having the above configuration will be described. FIG. 2 is a time chart for explaining the read operation of the semiconductor memory circuit 20. The semiconductor memory circuit 20 may be used in a circuit operating in a low-voltage operation state (for example, a power supply voltage of 2 V), but may be used in a high-voltage operation state (for example, a power supply voltage
V).

The case where the semiconductor memory circuit 20 operates in the low voltage operation state will be described below.

When a new address is input from the address input terminals A0 to An of the address input section 22 (FIG. 2).
(A)), address transition detection circuits ATD0 to ATD
n outputs a high-level address transition signal (ATD0 to ATDn) indicating a change in address to the synchronization signal generation circuit 33 (see FIG. 2B). As a result, it is detected that the address has been input to the semiconductor memory circuit 20.

When the high-level address transition signals (ATD0 to ATDn) are applied, the synchronizing signal generation circuit 33 outputs a high-level first precharge control signal (PRCH).
1) is output to the first precharge circuit 25 and the delay circuit 35 (see FIG. 2C). First precharge circuit 25
Is a high-level first precharge control signal (PRCH).
When 1) is applied, each bit line of the memory cell array 24 is precharged. Precharge end detection circuit 27
Detects whether the precharge voltage level of one bit line is equal to or higher than the detection voltage level. In the low voltage operation state, the precharge voltage level of the bit line does not become higher than the detection voltage level, so that the precharge end detection circuit 27 outputs the precharge end detection signal (PRC).
END) is not output (see the solid line in FIG. 2E: high-level signal).

After the first precharge control signal (PRCH1) is output from the synchronizing signal generation circuit 33 and a predetermined time T1 has elapsed, the high-level delay signal (PR
CHD) is supplied to the precharge control circuit 37 (see FIG. 2D).

When the delay signal (PRCHD) is input, the precharge control circuit 37 does not receive the precharge end detection signal (PRCEND), and therefore outputs the low-level second precharge control signal (PRCH2) to the second
Output to the precharge circuit 26 (see the solid line in FIG. 2 (f)). That is, the precharge of each bit line of the memory cell array 24 is performed using the second precharge circuit 26.

The second precharge circuit 26 precharges each bit line of the memory cell array 24 when the low level second precharge control signal (PRCH2) is input. When each bit line is precharged by the second precharge circuit 26, the precharge end detection circuit 27 detects that the voltage level of the precharge of the bit line is the detection voltage level, and the synchronization signal generation circuit 3
3 and outputs a precharge end detection signal (PRCEND) to the precharge control circuit 37 (see the solid line in FIG. 2E: low level signal).

When the precharge completion detection signal (PRCEND) is input, the synchronization signal generation circuit 33 outputs a high-level decoder activation signal (DEN) to the decoding unit 29 and the first precharge control signal (PRCEND). PR
CH1) from the high level to the low level,
The precharge operation of the precharge circuit 25 has been completed (see the solid lines in FIGS. 2C and 2G). When the precharge end detection signal (PRCEND) is input, the precharge control circuit 37 raises the second precharge control signal (PRCH2) from a low level to a high level, and the second precharge circuit 26 (See the solid line in FIG. 2 (f)).

The X-decoder 39 and the Y-decoder 41 of the decoding unit 29 have a high level decoder activation signal (DE).
When N) is given, the address temporarily stored in the address buffer 31 of the address input unit 22 is input. The X decoder 39 supplies a word line selection signal (WL) to the word line of the memory cell array 24 based on the address (see the solid line in FIG. 2 (h)). The Y decoder 41 outputs a selection signal to the Y gate 43 based on the address. The Y gate 43 reads data stored in the memory cell array 24 and outputs data D0 to Dm from an input / output terminal 44 via an input / output circuit 45 (see the solid line in FIG. 2 (i)).

Next, a case where the semiconductor memory device 20 operates in a high voltage operation state will be described below. The operation from the input of the address to the address input unit 22 to the activation of the first precharge circuit 26 to the precharge of each bit line of the memory cell array 24 is the same as the operation in the low voltage operation state described above. The description is omitted because it is the same as the case.

In this case, by using the first precharge circuit 26, the precharge voltage level of each bit line of the memory cell array 24 becomes equal to or higher than the detection voltage level, so that the delay signal (PRCHD) changes the precharge control circuit 3
7, the precharge control circuit 37 receives the precharge end detection signal (PRCEND) from the precharge end detection circuit 27 (FIG. 2 (e)).
(See dotted line: low level signal). Therefore, the precharge control circuit 37 outputs a low-level second precharge control signal (PRC) for activating the second precharge circuit 26.
H2) is not output to the second precharge circuit 26 (FIG. 2).
(F) See dotted line). That is, the precharge of each bit line of the memory cell array 24 using the second precharge circuit 26 is not performed.

When the precharge end detection signal (PRCEND) is input from the precharge end detection circuit 27, the synchronization signal generation circuit 33 outputs the high level word line activation signal (DEN) to the data input / output unit 28. And the first precharge control signal (PRCH).
1) falls from the high level to the low level, and the precharge operation by the first precharge circuit 25 is completed (see the dotted lines in FIGS. 2C and 2G). Thus, the above-described read operation is performed at the timing indicated by the dotted line in FIG. 2, data is read from memory cell array 24 by the input address, and data input / output unit 2
Data D0 to Dm are output from the eight input / output terminals 44.

As described above, the bit line of the memory cell array 24 is precharged using the second precharge circuit 26 in the low voltage operation state, and the memory cell array 24 is used using the first precharge circuit 25 in the high voltage operation state. Are precharged. Therefore, the bit line can be reliably precharged in the low voltage operation state, and the current consumption can be reduced in the high voltage operation state.

(Second Embodiment) FIG. 3 is a block diagram showing an electrical internal structure of a semiconductor memory device 50 of the second embodiment. The same components as those of the semiconductor memory device 20 according to the first embodiment have the same reference characters allotted, and description thereof will not be repeated.
The semiconductor memory device 50 of the second embodiment is different from the semiconductor memory device 20 of the first embodiment described above in that it further includes a dummy memory cell group 51 formed of a plurality of dummy memory cells. This is a configuration for detecting a precharge end state of the dummy memory cell group 51.

FIG. 4 is a circuit diagram showing an internal configuration of the dummy memory cells 52 included in the dummy memory cell group 51 and the precharge completion detection circuit 27. Each dummy memory cell 52 includes two n-type MOS transistors 5
3 and 54 and two inverter circuits 55 and 56. The MOS transistor 53 is connected to the memory cell array 2
4 are connected to the word lines W1 to Wn extended from the bit line 4 and to the bit line B2. Further, power supply voltage Vcc is applied to MOS transistor 53 via inverter circuit 55. MOS transistor 54
Is a word line W extended from the memory cell array 24.
1 to Wn and also to the bit line B1. Further, a ground level (GND level) is given to the MOS transistor 54 via an inverter circuit 56.

The precharge end detection circuit 27 is constituted by a NAND circuit 59. This NAND circuit 5
The detection voltage level (ICE) is input to one input terminal of the input terminal 9 and the voltage level of the bit line B2 is input to the other input terminal. As a result, the voltage level of the bit line B2 input to the other input terminal changes to the detection voltage level (IC
If E), a low-level precharge end detection signal (PRCEND) is output.

According to the above configuration, the precharge completion detecting circuit 27 determines that the precharge voltage level of the dummy memory cell group 51 in which data is not actually stored or read is equal to or higher than the detection voltage level (ICE). Detect if there is. Therefore, the precharge end detection circuit 2
7 is not connected to the memory cell array 24, the precharge end detection circuit 27 affects the precharge state of the memory cell array 24 that actually stores and reads data (for example, a decrease in precharge voltage level). It is possible to detect the voltage level of the precharge without any need.

(Third Embodiment) FIG. 5 is a block diagram showing an electrical internal configuration of a semiconductor memory device 70 according to a third embodiment. The same components as those of the semiconductor memory device 50 according to the second embodiment are denoted by the same reference numerals, and description thereof is omitted.
The semiconductor memory device 70 according to the third embodiment includes, in addition to the semiconductor memory device 50 according to the second embodiment, a power-on detection circuit 71 that detects power-on and outputs a power-on detection signal (DCIN). , A pseudo precharge unit 72 for setting a precharge state in advance, and a pseudo precharge determination detection circuit for detecting whether the preset precharge is completed and outputting a pseudo precharge detection signal (PPRC) when the precharge is completed 74. Note that the first precharge control signal (PRCH1) input from the synchronization signal generation circuit 33 to the delay circuit 35 is directly input to the precharge control circuit 77.

FIG. 6 is a circuit diagram showing the internal configuration of the pseudo precharge section 72 and the pseudo precharge determination detection circuit 74. The pseudo precharge unit 72 includes a pseudo precharge circuit 76 and a dummy memory cell 52a. The dummy memory cell 52a has the same configuration as the dummy memory cell 52 of the second embodiment shown in FIG. The word lines W1 to Wn to which the dummy memory cells 52a are connected are not connected to the memory cell array 24 but are grounded.

The pseudo precharge circuit 76 is provided by the first
The configuration is the same as that of the precharge circuit 25, and includes two n-channel MOS transistors 82 for precharge,
84 and one equalizing n-channel type MOS transistor 86. When a power-on detection signal (DCIN) indicating that power has been supplied to the semiconductor memory device 70 is given from the power-on detection circuit 71,
MOS transistor 82 precharges bit line B1 using the applied voltage, and MOS transistor 84 similarly precharges bit line B2. Also, an equalizing MOS transistor 86
When the power-on detection signal (DCIN) is supplied from the power-on detection circuit 71, the potentials of the bit lines B1 and B2 are made equal.

The pseudo precharge determination detection circuit 74 has the same configuration as the precharge end detection circuit 27 shown in FIG. 4, and one terminal of the NAND circuit 59 of the pseudo precharge determination detection circuit 74 is The same voltage level as the detection voltage level (ICE) input to the precharge end detection circuit 27 shown in FIG. The pseudo precharge determination detection circuit 74 determines that the voltage level of the bit line B2 input to the other input terminal is equal to the detection voltage level (I
CE), the pseudo precharge detection signal (PPR)
C) is output.

The semiconductor memory device 70 according to the third embodiment will be described below.
The read operation will be described. FIG. 7 is a time chart for explaining the read operation of semiconductor memory device 70.

The semiconductor memory device 70 uses the pseudo-precharge unit 72 and the pseudo-precharge determination detection circuit 74 having the above-described configuration to store the memory in the first precharge circuit 25 before using the semiconductor memory device 70, that is, when the power is turned on. It is detected whether the precharging of the bit lines of the cell array 24 and the dummy memory cell group 51 is completed. When the power-on detection circuit 71 detects the power-on of the semiconductor memory device 70, the power-on detection circuit 71 supplies a power-on detection signal (DCIN) to the pseudo precharge circuit 76. The pseudo precharge circuit 76 is connected to the bit lines B1, B
Precharge 2. Then, the pseudo precharge determination detection circuit 74 detects the voltage level of the bit line B2 and outputs a pseudo precharge detection signal (PPRC) (see FIG. 7C). The pseudo precharge detection signal (P
PRC) is high (that is, the precharge voltage level is equal to or higher than the detection voltage level (ICE)).
Indicates a low voltage operation state, and the first precharge circuit 25
Indicates that the precharge is not completed (FIG. 7C)
See solid line). Also, a pseudo precharge detection signal (PPR)
C) is at a low level (ie, when the precharge voltage level is lower than the detection voltage level (ICE)),
A high voltage operation state is shown, indicating that the precharge is completed in the first precharge circuit 25 (see a broken line in FIG. 7C).

Hereinafter, a read operation of semiconductor memory device 70 in a low voltage operation state will be described.

Address input terminal A of address input section 22
When a new address is input from 0 to An (see FIG. 7)
(A)), address transition detection circuits ATD0 to ATD
n outputs a high-level address transition signal (ATDS0 to ATDSn) indicating that an address has been input to the synchronization signal generation circuit 33 (see FIG. 7B).

When a high-level address transition signal (ATDS0 to ATDSn) is applied, the synchronization signal generation circuit 33 outputs a high-level first precharge control signal (PRC).
H1) is output to the first precharge circuit 25 and the precharge control circuit 77 (see FIG. 7D). As described above, in the low-voltage operation state, even if the first precharge circuit 25 is used to precharge the bit lines of the memory cell array 24, the precharge voltage level does not exceed the detection voltage level (ICE). . The pseudo precharge determination detection circuit 74 detects this in advance when the power is turned on, and outputs a high-level pseudo precharge detection signal (P
PRC) to the precharge control circuit 77.
The precharge control circuit 77 receives the high-level pseudo precharge detection signal (PPRC), and when the first precharge control signal (PRCH1) is further applied, immediately the low level second precharge control signal (PPRC) is input. P
RCH2) is output to the second precharge circuit 26 (see the solid line in FIG. 7E) to activate the second precharge circuit 26.

When a low-level second precharge control signal (PRCH2) is applied, the second precharge circuit 25 supplies the memory cell array 24 and the dummy memory cell group 5
Precharge each bit line of 1. At this time, the high-level first precharge control signal (PRCH1)
Is also precharged to each bit line of the memory cell array 24 and the dummy memory cell group 51.

The precharge end detection circuit 27 detects that the bit line B2 of the dummy memory cell group 51 has the detection voltage level (I
CE) or not, and outputs a precharge end detection signal (PRCEND) (see FIG. 7 (f)).

The precharge end detection signal (PRCE)
ND) is input to the synchronization signal generation circuit 33. The synchronization signal generation circuit 33 outputs a precharge end detection signal (P
RCEND), a high-level decode activation signal (DEN) is output to the data input / output unit 28, and the first precharge control signal (PRCH1) falls from a high level to a low level. The precharge operation in the precharge circuit 25 has been completed. (FIG. 7
(D) and FIG. 7 (g). Further, when the first precharge control signal (PRCH1) that has fallen to a low level is input, the precharge control circuit 77 raises the second precharge control signal (PRCH2) from a low level to a high level, and The precharge operation in the two precharge circuits 26 ends. (See the solid line in FIG. 7 (e))

Thus, as described in the first embodiment, the data input section 28 supplies the word line selection signal (WL) to the word line of the memory cell array 24 based on the input address (FIG. 7). (H)), the data stored in the memory cell array 24 corresponding to the address is read, and data D0 to Dm are output from the input / output terminal 44 (see FIG. 7 (i)).

The read operation of semiconductor memory device 70 in the high voltage operation state will be described below.

In this case, using the first precharge circuit 25, the memory cell array 24 and the dummy memory cell group 5 are used.
By performing precharge on each bit line of 1, the precharge voltage level becomes higher than or equal to the detection voltage level (ICE). The pseudo precharge determination detection circuit 74 detects this in advance when the power is turned on, and outputs a low-level pseudo precharge detection signal (PPRC) to the precharge control circuit 77 (see the broken line in FIG. 7C). . Therefore, the precharge control circuit 77 does not receive the high-level pseudo-precharge detection signal (PPRC) and receives the first precharge control signal (PRCH1). Signal (PRCH
2) is not output (see the broken line in FIG. 7E). As a result, only the first precharge circuit 25 to which the high-level first precharge control signal (PRCH1) is supplied from the synchronization signal generation circuit 33 precharges the bit lines of the memory cell array 24.

The semiconductor memory device 70 according to the third embodiment described above.
According to the method, since it is detected whether or not each bit line of the memory cell array 24 can be precharged by the first precharge circuit 25 when the power is turned on, there is no need to set a delay time, and the read operation can be performed. The operation speed can be improved without wasting time.

In the third embodiment, whether or not the precharge performed by the first precharge circuit 25 is completed when the power is turned on is detected. However, the present invention is not limited to the case where the power is turned on. It may be done at any time.

The power-on detection signal (DCIN) from the power-on detection circuit 71 is supplied to the first precharge circuit 2.
5, the precharge end detection circuit 27 detects whether or not the precharge of the bit line of the memory cell array 24 or the dummy memory cell group 51 is completed, and the same as the pseudo precharge detection signal (PPRC). A signal may be output.

In the above-described first to third embodiments, only the read operation has been described. However, the present invention is not limited to the above-described read operation, but is also applicable to the case where the pre-charge is performed in the write operation.

The first precharge circuit 25 and the second precharge circuit 26 are not limited to the configuration using MOS transistors, but may use other transistors or the like. Note that the configuration may be such that the first precharge circuit 25 is not activated when the bit line of the memory cell array 24 is precharged using the second precharge circuit 26.

The address transition detection circuits ATD0 to ATD0 to A
The input of an address is detected by using TDn, and the first precharge control signal (PRCH1) is output by the synchronization signal generation circuit 33 by the detection. The detection of the input of the address is detected by using a chip enable signal or the like. The configuration may be as follows.

[0071]

According to the structure of the semiconductor memory device of the present invention described above, the first precharge means and the second precharge means are selectively used depending on the operation state of the semiconductor memory device, so that the semiconductor memory device consumes power in the high voltage operation state. The current can be reduced, and the precharge can be reliably performed in the low voltage operation state. Further, by detecting in advance whether or not the precharge is completed by the first precharge means, if the precharge is not completed, the precharge is immediately performed using the second precharge means, thereby improving the operation speed of the semiconductor memory device. Can be planned.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an internal configuration of a semiconductor memory device according to a first embodiment;

FIG. 2 is a time chart for describing a read operation of the semiconductor memory device according to the first embodiment;

FIG. 3 is a block diagram showing an internal configuration of a semiconductor memory device according to a second embodiment;

FIG. 4 is a circuit diagram showing an internal configuration related to a dummy memory cell group and a precharge end detection circuit.

FIG. 5 is a block diagram showing an electrical internal configuration of a semiconductor memory device according to a third embodiment;

FIG. 6 is a circuit diagram showing an internal configuration of a pseudo precharge unit and a pseudo precharge determination detection circuit.

FIG. 7 is a time chart for explaining a read operation of the semiconductor memory device;

FIG. 8 is a block diagram showing an internal configuration of a conventional semiconductor memory device.

FIG. 9 is a time chart showing a data read operation of a conventional semiconductor memory device.

[Explanation of symbols]

 20, 50, 70 Semiconductor memory device 22 Address input unit 24 Memory cell array 25 First precharge circuit 26 Second precharge circuit 27 Precharge completion detection circuit 28 Data input / output unit 37, 77 Precharge control circuit 51 Dummy memory cell group 52, 52a Dummy memory cell 71 Power-on detection circuit 72 Pseudo precharge unit 74 Pseudo precharge determination detection circuit 76 Pseudo precharge circuit

Claims (5)

[Claims] A storage unit including a memory cell connected to a bit line and a word line; a first precharge unit for precharging the bit line; and a first precharge unit for the bit line. Second precharge means for performing precharge at a voltage level higher than the charge means, detection means for detecting completion of precharge for the bit line, and detection means for completing the precharge of the first precharge means Control means for causing the bit line to precharge by the second precharge means when the detection is not performed. 2. A storage unit comprising a memory cell connected to a bit line and a word line; a first precharge unit for precharging a bit line of the storage unit and a dummy memory cell; Second precharge means for precharging the bit line at a higher voltage level than the first precharge means; detection means for detecting completion of precharge of the bit line of the dummy memory cell; Control means for causing the bit line of the storage means to precharge by the second precharge means when the detection means does not detect the completion of the precharge of the first precharge means. Semiconductor storage device. 3. The apparatus according to claim 1, wherein the detection means detects whether the precharge is completed within a predetermined time after the precharge of the first precharge means is started. Semiconductor storage device. 4. The semiconductor memory device according to claim 1, wherein said detecting means detects in advance whether precharging of said first precharging means is completed. 5. A storage unit including a memory cell connected to a bit line and a word line; a first precharge unit for precharging the bit line; and a first precharge unit for the bit line. A second precharge means for precharging at a higher voltage level than the charging means; a pseudo precharge means for precharging the bit line of the pseudo dummy memory cell at the same voltage level as the first precharge means; Pseudo detection means for detecting whether or not precharging of the bit line of the pseudo dummy memory cell is completed; and when the pseudo detection means does not detect completion of precharge, the second precharge means Control means for causing a bit line to be precharged.