JPH10172150A - Disk, disk forming device, disk forming method, disk recording and reproducing device and disk recording and reproducing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form an exact clock signal from a reproducing FM carrier. SOLUTION: Channel data (Fig. (a)) is formed by phase modulation of bit data. If this channel data is in the state of a '1', the track (Fig. (c)) wobbled by 4+1/4 waves is formed at the optical disk. If the channel data is the state of a '0', the track (Fig. (d)) wobbled by 4-1/4 waves is formed at the optical disk. At the time or reproduction, the clock signal (Fig. (f)) is formed with the zero cross point of the wobbling signal (Fig. (d)), i.e., the boundary parts of the bit data as a reference.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a disk, a disk forming apparatus, a disk forming method, a disk recording and reproducing apparatus, and a disk recording and reproducing method. The present invention relates to a wobbling disk, a disk forming apparatus, a disk forming method, a disk recording and reproducing apparatus, and a disk recording and reproducing method.

[0002]

2. Description of the Related Art CD-R (Compact Disk-Recordable)
Address (or time) information is recorded in advance on a recordable optical disc such as a DVD or an MD (Mini Disk) so that data can be recorded at a predetermined position. This address information is recorded by wobbling (meandering) the pre-groove with a frequency modulation wave that has been frequency-modulated (Frequency Modulation) with the address information.

[0003] In this way, address information can be read from the wobbling information, and data can be recorded at a desired position based on the address information.

[0004] The address information recorded in this manner is extracted by the extracting device shown in FIG. Less than,
This conventional example will be described.

In FIG. 1, a buffer 10 amplifies a signal output from a light receiving section (not shown) for converting reflected light from an optical disk into an electric signal with a predetermined gain and outputs the amplified signal. Band Pass Filter
The BPF 11) extracts a wobble modulation component (reproduced frequency modulation wave) from the electric signal output from the light receiving unit and outputs it to the phase comparator 12. Phase comparator 12
Compares a phase of an FM clock signal output from a voltage control oscillator (hereinafter, abbreviated as VCO) 13 with a phase of a signal output from a BPF 11 and outputs a signal corresponding to a phase shift. .

The low frequency component of the signal output from the phase comparator 12 is extracted by a low pass filter (hereinafter abbreviated as LPF) 14 and the VCO 13
Is output to Since the VCO 13 increases and decreases the transmission frequency in accordance with the level of the output signal of the LPF 14, the transmission frequency of the VCO 13 is a signal (FM clock) that is averagely locked to a reproduction frequency modulation wave that is a wobble modulation component. ).

[0007] The phase comparator 12 compares the phase of the reproduction frequency modulated wave output from the BPF 11 with the phase of the FM clock output from the VCO 13 and outputs a signal corresponding to the phase difference. LP
F15 extracts a low-frequency component from the signal output from the phase comparator 12, and outputs the same to the comparator 16. The comparator 16 compares the output signal of the LPF 15 with a reference voltage. When the output level of the LPF 16 is higher than the reference voltage, the output of the comparator 16 is set to “1”.
The output is set to “0”. The signal output from the comparator 16 is input to the flip-flop 17 and the delay unit 18 as binary channel data.

The delay unit 18 delays the channel data output from the comparator 16 by a predetermined time and outputs the delayed data. The exclusive OR circuit 19 performs an exclusive OR operation between the channel data delayed by the delay unit 18 and the original (non-delayed) channel data, thereby forming an edge portion of the channel data. Extract,
Monostable Multivibrator
vibrator (hereinafter abbreviated as MM) 20.
The MM 20 generates a pulse signal in synchronization with the edge of the signal output from the exclusive OR circuit 19 and outputs the pulse signal to the phase comparator 21.

The phase comparator 21 compares the phase of the output signal from the VCO 23 with the phase of the pulse signal from the MM 20, and outputs a signal corresponding to the phase difference. The LPF 22 extracts a low frequency component from the output signal of the phase comparator 21 and
Output to O23. The VCO 23 changes the transmission frequency according to the level of the signal supplied from the LPF 22. V
The signal output from the CO 23 is ADIP (Address In).
-pregroove) Flip-flop 17 as clock signal
Clock terminal.

The flip-flop 17 is connected to the comparator 1
6 from the signal output from the VCO 23
Latch and output in synchronization with the DIP clock signal. The signal output from flip-flop 17 is supplied to AD (not shown).
The signal is supplied to the IP demodulation circuit, and based on this signal, the ADIP
The data is demodulated.

FIG. 20 is a timing chart showing signals of main parts of the ADIP clock signal generator of FIG.

The channel data (FIG. 20 (a)) output from the comparator 16 is delayed by a predetermined amount by the delay unit 18, and the output signal of the delay unit 18 (FIG. 20 (b))
Is supplied to one terminal of the exclusive OR circuit 19. Since the output signal (FIG. 20A) from the comparator 16 is directly supplied to the other terminal of the exclusive OR circuit 19, the exclusive OR circuit 19 performs an exclusive operation between these signals. The logical sum is calculated, and the calculation result (FIG. 20)
(C)) is output. The signal output from the exclusive OR circuit 19 is a signal that generates a pulse at the edge portion (rising or falling portion of the signal) of the channel data (FIG. 20A).

The MM 20 is triggered by a pulse included in the output signal from the exclusive OR circuit 19, and continues to maintain the state of "1" for a predetermined time (FIG. 20).
(D)) occurs. The phase comparator 21 outputs the output signal of the MM 20 (FIG. 20D) and the output signal of the VCO 23 (FIG. 2).
0 (e)), by performing an exclusive OR operation,
The phases of these two signals are compared, and the operation result is output as a phase comparator 21 output signal (FIG. 20 (f)).

Output signal of phase comparator 21 (FIG. 20 (f))
Is input to the VCO 23 through the LPF 22,
The VCO 23 supplies the phase comparator 21 with a VCO 23 output signal (FIG. 20 (e)) whose transmission frequency changes according to the level of the signal output from the LPF 22, and uses this signal as an ADIP clock signal to output the flip-flop 17 Also supply.

By the above operation, an ADIP clock signal is generated. In response to the ADIP clock signal, the flip-flop 17 extracts a predetermined portion of the channel data, and according to the extracted signal, outputs the ADIP data. Demodulation will be performed.

FIG. 21 is a diagram showing an example of a binarized wobbling modulation component (frequency modulation wave). The bit data (FIG. 21C) indicates the state of the bits of the address data (ADIP data) to be recorded.
The channel data (FIG. 21B) indicates the state of bits obtained when the bit data (FIG. 21C) is subjected to bi-phase modulation, that is, digital frequency modulation. The waveform (FIG. 21A) shows a pattern of channel data 1 and 0, where 1 is a high level signal and 0 is a low level signal.

The channel data (FIG. 21B)
When recording is performed, a predetermined carrier is subjected to analog frequency modulation by channel data, and a pregroove is wobbled by an obtained analog signal (frequency modulated wave). That is, when the channel data is "1", the wave number is modulated to a signal of (n + d), while when the channel data is "0", the wave number is modulated to a signal of (n-d). Then, the pregroove is wobbled according to the obtained signal.

Now, for the sake of simplicity, n = 4, d = 1/16
And At this time, the sync pattern data is Digita
l Since the Sum Value (DSV) is set to be “0”, the number of “1” s between P0 and P1 in the channel data (FIG. The number is four each. Therefore, when analog frequency modulation is performed using this channel data (FIG. 21B), the total wave number of the analog signal is

4 × (n + d) + 4 × (nd) = 2 × 4 × n = 32

And the wave number is an integer.

In P2, since two consecutive "1" exist between P1 and P2, the wave number in this portion is 2 × (4 + 1/16) = 8 + (1/8), and the phase Are shifted by 1/8. Further, in P3 to P5, since "1" and "0" are alternately continuous, no phase change occurs, and the 1/8 phase shift in P2 is maintained.

In P6, since "0" appears twice between P5 and P6, two "1" s appearing between P1 and P2 appear.
The phase shift due to is canceled. Therefore, the phase becomes zero.

[0023]

As described above, a reproduction frequency modulation wave (a signal in which channel data is frequency-modulated)
Causes a phase shift depending on the arrangement state of bit data "1" or "0". Accordingly, the PLL including the phase comparator 12, the LPF 14, and the VCO 13 shown in FIG.
When trying to extract the FM clock signal from the reproduction frequency modulated wave by (Phase Locked Loop), the phase does not become “0” depending on the recorded data (the boundary of the signal does not become the zero crossing point). However, there has been a problem that it is impossible to generate a simple clock signal.

The present invention has been made in view of the above situation, and makes it possible to accurately extract a clock signal from a reproduction frequency modulated wave.

[0025]

According to a first aspect of the present invention, in the disk, address data is phase-modulated, and frequency modulation is performed by channel data obtained as a result of the phase modulation.
The track is wobbled by the frequency modulation wave obtained as a result of the frequency modulation, and both the start point and the end point of the bit data of the address data are zero cross points of the frequency modulation wave.

According to a fifth aspect of the present invention, the start point and the end point of the bit data of the address data are determined by the phase modulation means for phase-modulating the address data and the channel data obtained as a result of the phase modulation by the phase modulation means. ,
Both are characterized by comprising frequency modulation means for performing frequency modulation so as to be a zero cross point of the frequency modulation wave, and wobbling means for wobbling a track by a frequency modulation wave obtained as a result of frequency modulation by the frequency modulation means. I do.

According to a sixth aspect of the present invention, the starting point and the ending point of the bit data of the address data are determined by the phase modulation step of phase-modulating the address data and the channel data obtained as a result of the phase modulation by the phase modulation step. And a wobbling step of wobbling a track with a frequency modulation wave obtained as a result of the frequency modulation by the frequency modulation step. And

According to a seventh aspect of the present invention, there is provided a disk recording / reproducing apparatus, comprising: a reading unit for reading address data recorded on a disk; and a detecting unit for detecting a boundary between bit data of the address data read by the reading unit. And a clock generating means for generating a clock signal based on a boundary portion of the bit data detected by the detecting means.

[0029] According to a ninth aspect of the present invention, there is provided a disk recording / reproducing method comprising: a reading step of reading address data recorded on a disk; and a detecting step of detecting a boundary between bit data of the address data read by the reading step. And a clock generating step of generating a clock signal based on a boundary portion of the bit data detected by the detecting step.

In the disk according to the first aspect, the address data is phase-modulated, the frequency is modulated by the channel data obtained as a result of the phase modulation, and the track is modulated by the frequency-modulated wave obtained as a result of the frequency modulation. While wobbling, the start point and the end point of the bit data of the address data are both set to the zero cross point of the frequency modulation wave. For example, the address data is phase-modulated, frequency-modulated so that the boundary of the generated bit data becomes the zero-crossing point of the signal, and the track is wobbled by the obtained signal.

In the disk forming apparatus according to the fifth aspect, the address data is phase-modulated by the phase modulating means, and the start point and the ending point of the bit data of the address data are determined by the channel data obtained as a result of the phase modulation by the phase modulating means. However, the frequency modulating means performs frequency modulation such that the zero-cross point of the frequency modulated wave is obtained, and the wobbling means wobble the track by the frequency modulated wave obtained as a result of the frequency modulation by the frequency modulating means. For example, the phase modulation means performs phase modulation on the address data to generate bit data. The frequency modulating means performs n + d or n + n so that a boundary portion of the bit data obtained as a result of the phase modulation becomes a zero crossing point of the signal.
The frequency modulation is performed on the frequency including the wave number of -d, and the wobbling means wobble the track according to the frequency-modulated signal.

In the disk forming method according to the sixth aspect, the address data is phase-modulated in the phase modulation step, and the start point and the end point of the bit data of the address data are obtained by the channel data obtained as a result of the phase modulation by the phase modulation step. However, in each case, the frequency modulation step performs frequency modulation so as to be a zero cross point of the frequency modulation wave, and the wobbling step causes the track to wobble with the frequency modulation wave obtained as a result of the frequency modulation by the frequency modulation step. For example, the phase modulation step performs phase modulation on the address data to generate bit data. The frequency modulation step performs frequency modulation on a frequency including n + d or n−d wave numbers so that the boundary portion of the bit data obtained as a result of the phase modulation becomes a zero cross point of the signal, and the wobbling step is performed. The track is wobbled according to the frequency-modulated signal.

In the disk recording / reproducing apparatus according to the seventh aspect, the reading means reads the address data recorded on the disk, and the detecting means detects the boundary portion of the bit data of the address data read by the reading means. Then, the clock generation means generates a clock signal based on the boundary of the bit data detected by the detection means. For example, the reading means reads the address data recorded by wobbling the track of the disk, and the detecting means detects the data by referring to the zero cross point at the boundary of the data of the read wobbling signal,
The clock generation unit generates a clock by generating a predetermined number of pulses in a period between two boundary portions of the bit data detected by the detection unit.

In the disk recording / reproducing method according to the ninth aspect, the reading step reads the address data recorded on the disk, and the detecting step detects the boundary portion of the bit data of the read address data in the reading step. Then, the clock generation step generates a clock signal based on the boundary of the bit data detected by the detection step. For example, the read step reads the address data recorded by wobbling the track of the disk, and the detection step detects by referring to the zero cross point at the boundary of the data of the read wobbling signal. The clock generation step generates a clock by generating a predetermined number of pulses during a period between two boundary portions of the generated bit data.

[0035]

FIG. 1 shows an example of the configuration of an optical disk to which the disk of the present invention is applied. As shown in FIG. 1, a pre-groove 2 is formed in a disk (optical disk) 1 in a spiral shape from an inner periphery to an outer periphery in advance. Of course, the pre-groove 2 can be formed concentrically.

The pre-groove 2 has its left and right side walls wobbled corresponding to the address information and meandered corresponding to the frequency modulation wave, as shown in a partially enlarged manner in FIG. ing. One track has a plurality of wobbling address frames.

In this embodiment, the tracks are formed on the pre-groove 2, but they may be formed on the lands.

FIG. 2 shows the structure (format) of a wobbling address frame. As shown in the figure, the wobbling address frame is composed of 48 bits, and the first 4 bits are a synchronization signal (Sync) indicating the start of the wobbling address frame. Next 4
The bit is a layer (Layer) indicating which of the plurality of recording layers it is. The next 20 bits are used as a track address (track number). The next 4 bits indicate the frame number of the address frame. The remaining 14 bits are used as an error correction code (CRC), and an error correction code excluding a synchronization signal (Sync) is recorded. Last two bits (Reserve
d) is reserved as a reserve for the future.

For example, eight wobbling address frames are recorded per track (one rotation). The recording form is a CAV disk shape in which the rotational angular velocity of the disk is constant. Therefore, for example, values of 0 to 7 are recorded as the frame numbers in FIG.

FIG. 3 shows an example of the configuration of a wobbling signal generating circuit for generating a wobbling signal for wobbling the pregroove 2 corresponding to the address frame of the format shown in FIG. The generation circuit 11
A signal having a frequency of 115.2 kHz is generated. The signal generated by the generation circuit 11 is supplied to the division circuit 12, and the value 8
After that, the signal is supplied to the phase modulation circuit 13 (phase modulation means, phase modulation step) as a phase modulation clock signal having a frequency of 14.4 kHz. The phase modulation circuit 13 is also supplied with the frame format ADIP data shown in FIG.

The phase modulation circuit 13 converts the phase clock supplied from the divider 12 into an A signal supplied from a circuit (not shown).
Phase modulation with DIP data (address data)
coding: PE) (digital phase modulation), and outputs the obtained phase modulation signal to the FM modulation circuit 15 (frequency modulation means, frequency modulation step). A carrier signal having a frequency of 57.6 kHz obtained by dividing a signal of 115.2 kHz generated by the generation circuit 11 by a value of 2 by the divider 14 is also input to the FM modulation circuit 15. FM
The modulation circuit 15 performs analog frequency modulation of the carrier input from the divider 14 with a phase signal input from the phase modulation circuit 13 and outputs a frequency modulation wave obtained as a result. The left and right side walls of the pregroove 2 of the disk 1 are formed (wobbled) corresponding to the frequency modulated wave.

FIG. 4 is a diagram showing the relationship between the address data and the modulation signal. In the bit data (Bit Data) of the address data (ADIP data) (FIG. 4C), “
“0” is phase-modulated and converted into “10” channel data (PE signal) (FIG. 4B), and “1” is converted into “01” channel data. That is, the signal is converted into a signal in which the position (phase) of the pulse changes in accordance with the bit data. The level 0 is represented as a low-level signal (that is, in NRZ).

The FM modulation circuit 15 performs analog frequency modulation on the carrier signal supplied from the divider 14 in accordance with the channel data (PE signal) (FIG. 12B) shown in FIG.

That is, as shown in FIG. 5, when the channel data (phase modulation signal) (FIG. 5A) is 1, the FM modulation circuit 15 corresponds to half the length of 1-bit bit data. For example, during the 1-bit channel data period, 4 + 1/4 wave carriers are output (FIG. 5).
(B)).

On the other hand, channel data (FIG. 5)
When (a)) is 0, a 4/4 wave carrier is output during a period corresponding to half the length of 1-bit bit data (see FIG. 5B).

Since the phase-modulated wave always includes one "0" and one "1" in a 1-bit data section, the number of waves included in this section is (4-1 / 4). ) +
(4 + 1/4) = 8, and the phase becomes 0 at the boundary of the bit data regardless of the contents of the address data (the boundary of the bit data becomes the zero cross point of the signal).

57.6k input to FM modulation circuit 15
The Hz carrier corresponds to four waves. The FM modulation circuit 15 adjusts the carrier of the four waves to ± 6.25% (= 1/4 /) in accordance with the phase modulation signal (channel data).
4) A shifted (4 + 1/4) or (4-1 / 4) frequency-modulated wave is generated.

FIG. 5 (b) shows an example of the frequency modulation wave generated by the FM modulation circuit 15 in this manner. In this example, the first channel data is "1" and the next channel data is "0". That is, bit data “0” is represented by these two channel data. For the first channel data “1”, 4 + 1/4 wave carriers starting from a positive half wave from the start point are generated, and subsequently, 4−1 / 4 wave carriers are generated. Then, channel data "1" which is a boundary of bit data
And the end point of the channel data “0” are set to zero cross points of the frequency modulation wave (the carrier phase is set to 0 at the start point and the end point of the bit data).

As described above, since the phase of the 2-bit channel data coincides with the phase of the frequency-modulated wave, the boundary of the bit data can be easily identified, and erroneous detection of the bit data can be prevented. As a result, it is possible to accurately reproduce the address information.

In this embodiment, the boundary (start point and end point) of the bit data corresponds to the edge (zero cross point) of the frequency modulation wave. Thereby, as described later, a clock signal can be generated with reference to the edge of the frequency modulation wave.

FIG. 6 shows a disc 1 having a pregroove.
1 shows a configuration example of a recording device (disc forming device) for forming an image. The wobbling signal generation circuit 21 has the configuration shown in FIG.
Are supplied to the recording circuit 24.

The recording circuit 24 controls the optical head 25 (wobbling means, wobbling step) according to the signal supplied from the wobbling signal generation circuit 21 to generate a laser beam for forming a pre-groove on the master 26. Let it. The spindle motor 27 rotates the master 26 at a constant angular velocity (CAV: Constant Angular Velocity) or a constant linear velocity (CLV: Constant Linear Velocity).

That is, the wobbling signal generation circuit 21
The frequency-modulated wave in which is generated is input to the recording circuit 24. The recording circuit 24 controls the optical head 25 according to the signal input from the wobbling signal generation circuit 21 to generate a laser beam. The laser light generated by the optical head 25 is applied to a master 26 rotated by a spindle motor 27 at a constant angular velocity or a constant linear velocity.

The master 26 is developed, a stamper is formed from the master 26, and the replica disk 1 is formed from the stamper. As a result, the disk 1 on which the pre-groove 2 is formed can be obtained.

FIG. 7 shows an example of the configuration of an optical disk recording / reproducing apparatus for recording or reproducing data on or from the disk 1 thus obtained. Spindle motor 3
Numeral 1 is for rotating the disk 1 at a constant angular velocity. The optical head 32 (reading means, reading step) records data by irradiating the disk 1 with laser light, and reproduces data from the reflected light. Recording / reproducing circuit 33
Is configured to modulate recording data input from a device (not shown) by a predetermined method, and output the recording data to the optical head 32. Further, the recording / reproducing circuit 33 demodulates data input from the optical head 32 and outputs the data to a device (not shown).

The address generating / reading circuit 35 includes the control circuit 3
In response to the control of No. 8, a data address (sector address) to be recorded in the track (pre-groove 2) is generated and output to the recording / reproducing circuit 33. The recording / reproducing circuit 33
This address is added to recording data supplied from a device (not shown) and output to the optical head 32. The recording / reproducing circuit 33 separates the address data from the reproduction data reproduced from the track of the disk 1 by the optical head 32 and outputs the address data to the address generation / read circuit 35. The address generating / reading circuit 35 outputs the read address to the control circuit 38.

The frame address detection circuit 37
Address information (track number and frame number in FIG. 2) included in the wobbling signal is read from the RF signal output by the optical head 32 and supplied to the control circuit 38.

The PLL circuit 40 extracts a wobbling signal (see FIG. 5D) included in the RF signal, generates a clock signal from the wobbling signal, and supplies the clock signal to the recording / reproducing circuit 33 and each unit of the apparatus. It has been made to be. The recording / reproducing circuit 33 detects a (user) data recording area with reference to the clock signal output from the PLL circuit 40 and the address data output from the address generating / reading circuit 35.

FIG. 8 shows an example of the detailed configuration of the PLL circuit 40.
Shown in In this figure, a buffer 60 is an amplifier having a gain of “1”. The BPF 61 outputs a wobbling signal (FIG. 5) among the signals output from the buffer 60.
(D)) is extracted. The comparator 62 generates a binary signal by comparing the output signal of the BPF 61 with a ground level. That is, BPF6
When the output signal of “1” is smaller than the ground level (= 0 V), the output signal is set to “0”, and when it is larger, it is set to “1”.

As will be described later, the gate signal generation circuit 63 generates a gate signal (FIG. 5) that generates a pulse at the boundary of bit data from the signal output from the comparator 62.
(E)) is generated and supplied to the gate circuit 64. The gate circuit 64 extracts a predetermined bit of the binarized signal in synchronization with the gate signal, and outputs the extracted bit to the phase comparator 65. The phase comparator 65 compares the signal output from the frequency divider 66 with the output signal from the gate circuit 64, and generates an output corresponding to the phase shift of these signals.

The LPF 67 extracts only low-frequency components from the signal output from the phase comparator 65, and
(Clock generation means, clock generation step). The VCO 68 changes the transmission frequency according to the signal output from the LPF 67, and the output signal is output as a clock signal (FIG. 5 (f)). The frequency divider 66 divides the frequency of the clock signal output from the VCO 68 to a predetermined value (1/16 in FIG. 5) and outputs the frequency to the phase comparator 65.

That is, the phase comparator 65, LPF 67, VC
O68, and a PLL composed of a frequency divider 66,
The control is performed so that the phase of the signal output from the gate circuit 64 and the frequency of the clock signal (FIG. 5F) divided by 1/16 are synchronized. As a result, a clock signal having a frequency 16 times that of the signal output from the gate circuit 64 is output.

Next, an example of a detailed configuration of the gate signal generation circuit 63 will be described with reference to FIG. In this figure,
After inverting the signal output from the comparator 62 (see FIG. 8), the inverter 80 converts the A / D converter 84, the triangular wave generation circuits 82 and 83, the flip-flops 89-1 to 89-8, and the flip-flops 103 and 104. , And the timing counter 105. Buffer 8
1 also supplies the output signal of the comparator 62 to the triangular wave generating circuits 82 and 83 and the A / D converter 85.

The triangular wave generating circuit 82 starts generating a triangular wave at the timing when the output signal of the buffer 81 rises, and ends when the output signal of the inverter 80 rises. Conversely, the triangular wave generation circuit 83 starts generating a triangular wave at the timing when the output signal of the inverter 80 rises, and ends when the output signal of the buffer 81 rises.

The A / D converters 84 and 85 convert the output signals of the triangular wave generation circuits 82 and 83 into digital data and output the digital data to the adder 86. The adder 86 has an A / D
Signals output from converters 84 and 85 are added and output to comparators 87 and 88. Comparator 87 compares the output of adder 86 with reference level “l” and outputs the result of the comparison as a binary signal. The comparator 88 includes an adder 86
Is compared with the reference level “s”, and the comparison result is similarly output as a binary signal.

The signals (2) output from the comparators 87 and 88
Bit parallel signal) is a flip-flop 89-1
To the shift register composed of the flip-flops 89-1 to 89-8 in synchronization with the output signal of the inverter 80.
The output signals of the comparators 87 and 88 and the flip-flops 89-1 to 89-8 are output to the operation gate 90 (detection means,
(Detection step). The operation gate 90 includes comparators 87 and 88 and a flip-flop 89 as described later.
1 → s / s → l detection signal, which becomes “1” when the output signals of −1 to 89-8 satisfy a predetermined condition, s
→ m → l detection signal or l → m → s detection signal is output.

The signal output from the operation gate 90 is input to a logical sum circuit 91 and a logical product circuit 98,
100 and 101 are input to one terminal. The output of the OR circuit 91 is supplied to the flip-flop circuits 103, 1 via the AND circuits 96, 97 and the OR circuit 92.
04 has been entered.

The output signal of the AND circuit 98 is input to one terminal of the AND circuit 99 and to the set terminal of the flip-flop 104. The output of the AND circuit 99 is input to one terminal of the OR circuit 94 and the s1 terminal of the selector 102. The selector 102 outputs predetermined data to the timing counter 105 according to the state of a signal input to the s0 and s1 terminals.

The output of the AND circuit 100 is output to the OR circuit 9
3 is input to one terminal. The output of the AND circuit 101 is input to the other terminal of the OR circuit 93, and is also input to the s0 terminal of the selector 102. The output of the OR circuit 93 is input to one terminal of the OR circuit 94 and to the set terminal of the flip-flop 103.

The timing counter 105 is an 8-bit counter, and reads (loads) the data output from the selector 102 as an initial value at the timing when the output signal of the OR circuit 94 rises, and counts up. The output signal of the flip-flop 105 is input to the encoder 107, where the output signal is encoded, and
The W1 signal, the WINDOW2 signal, and the gate signal are output.

The WINDOW 1 signal is input to one terminal of the AND circuit 98, and the WINDOW 2 signal is input to one terminal of the AND circuit 96.
Further, the gate signal is supplied to the gate circuit 64 shown in FIG.

The output signals of the flip-flops 103 and 104 are input to the encoder 106 as 2-bit data of lower bits and upper bits, respectively. The encoder 106 sets the output of the terminal corresponding to the input 2-bit data value to “1”. That is, when the input signal is, for example, “11” (binary number), the output of the terminal 3 is set to “1”, and the outputs of the other terminals are set to “0”.

The terminal 0 of the encoder 106 is input to one terminal of the AND circuits 100 and 101. Also,
The terminals 1 to 3 are input to one terminal of an AND circuit 99, an OR circuit 92, and an AND circuit 97, respectively.

Next, the operation of this embodiment will be described with reference to FIG.

FIG. 10 is a timing chart showing signal timings of main parts of the block diagram shown in FIG. In this figure, channel data (FIG. 10A) is "1",
This indicates the timing of the signal when it is output in the order of “0”, that is, when the bit data is “0”.

As shown in FIG. 8, when the channel data is "1", the output signal of the BPF 61 (FIG. 10B)
Contains 4 + 1/4 wave carriers, and
When the channel data is "0", a carrier of 4-1 / 4 wave is included. The output signal of the BPF 61 is input to the comparator 62, and is compared with the ground level to be a binary signal shown in FIG.
Then, this binarized signal is input to the gate circuit 64 and the gate signal generation circuit 63.

The binarized signal input to the gate signal generation circuit 63 is supplied to the triangular wave generation circuits 82 and 83 via the inverter 80 and the buffer 81. Triangular wave generation circuit 8
No. 2 starts generating a triangular wave at the timing when the output signal of the buffer 81 rises and ends at the timing when the output signal of the inverter 80 rises (FIG. 10D). That is, the generation of the triangular wave is started at the timing when the binarized signal rises, and the generation of the triangular wave is ended at the timing when the binarized signal falls. Further, the triangular wave generation circuit 83 starts generating a triangular wave at the timing when the binarized signal falls and ends at the timing when it rises (FIG. 10).
(E)). As a result, the ultimate voltage of the triangular wave output from the triangular wave generation circuit 82 is a voltage corresponding to the time of the positive portion of the wobbling signal for one cycle, and the ultimate voltage of the triangular wave output from the triangular wave generation circuit 83 is 1 The voltage corresponds to the time of the negative portion of the wobbling signal for the period.

The signals output from the triangular wave generating circuits 82 and 83 are supplied to A / D converters 84 and 85, where the reaching voltage of the triangular wave is A / D converted and digitized. Is output.

In the BPF 61 output signal (wobbling signal) (FIG. 10B), the channel data is "1".
, The cycle is short, and if the channel data is “0”, the cycle is long. Further, near the boundary of the channel data, the cycle has an intermediate length. Therefore, the ultimate voltage of the triangular wave output from the triangular wave generating circuits 82 and 83 is s ′ (lowest ultimate voltage) when the channel data is “1”, and l ′ when the channel data is “0”.
(Highest reached voltage), and m ′ (s ′ <m ′ <l ′) near the boundary between “1” and “0”.

The triangular wave reaching voltages s ′, m ′, and l ′ output from the triangular wave generating circuits 82 and 83 are converted into digital data by A / D converters 84 and 85, and then added by an adder 86. The signals are added and output to the comparators 87 and 88 as 2-bit data representing the length of one cycle of the binary signal. The comparator 87 compares the output data of the adder 86 with a reference value l (= l '+ l'), and when the output data of the adder 86 is larger than the reference value l or equal to each other, , The output signal is "1", otherwise, it is "0". The comparator 88 compares the output data of the adder 86 with the reference value s (= s ′ + s ′). If the output data of the adder 86 is smaller than or equal to the reference value s, , The output signal is set to a “1” state, otherwise, the output signal is set to a “0” state.

As a result, when the value of the output data of the adder 86 is s, the outputs of the comparators 87 and 88 are
When the output data of the adder 86 is “1”, the outputs of the comparators 87 and 88 are “1” and “0”, respectively. In other cases (when the output data value of the adder 86 is m), the comparator 87,
The outputs of 88 are "0" and "0", respectively. The output signals of the comparators 87 and 88 in FIG. 10F are output from the comparator 8 when the channel data is “1001”.
7 and 88 are shown in FIG.
The output signals of the comparators 87 and 88 in (g) show the states of the output signals of the comparators 87 and 88 when the channel data is “1010”.

The flip-flops 89-1 to 89-8
Latches the signals output from the comparators 87 and 88 as upper bits or lower bits, respectively, and sequentially shifts the signals in synchronization with the signal output from the inverter 80 (the signal obtained by inverting the binary signal). I will do it. Further, the output signals of the comparators 87 and 88 and each flip-flop 89-
The output signals of 1 to 89-8 are input to the operation gate 90.

1 → s / s output from operation gate 90
→ In the 1 detection signal, the output signals of the comparators 87 and 88 correspond to s (the state of the output signals of the comparators 87 and 88 is
"0", "1"), when the output signal of the flip-flop 89-1 corresponds to 1, or when the comparator 87,
The output signal of 88 corresponds to 1 and the flip-flop 89-
When the output signal of 1 corresponds to s, the state is set to "1", otherwise, it is set to "0". Then, the l → s / s → l detection signal is output to one terminal of the OR circuit 91 and one terminal of the AND circuit 98.

That is, the state where the l → s / s → l detection signal is “1” is at the boundary of the bit data (at the boundary of the channel data in the bit data, the state of m is inserted). This does not apply in this case), so that the boundary of the bit data can be detected by referring to this signal.

Further, s → output from the operation gate 90
In the m → l detection signal, the output signals of the comparators 87 and 88 correspond to l (the state of the output signals of the comparators 87 and 88 is “1”,
"0"), flip-flops 89-1 and 89-2
Are set to “1” when the output signals of “m” and “s” respectively correspond to “m” and “s”, and are set to “0” otherwise. The s → m → l detection signal is output from the OR circuit 91 at 1
And one terminal of the AND circuit 100.

That is, since the s → m → l detection signal becomes “1” at the boundary of the channel data in the bit data representing “0”, the signal is referred to as “1”. It is possible to detect the boundary of the bit data representing "0".

Further, l → output from the operation gate 90
The m → s detection signal is “1” when the output signals of the comparators 87 and 88 correspond to s and the output signals of the flip-flops 89-1 and 89-2 correspond to “m” and “l”, respectively. State, and in other cases, the state is "0". The l → m → s detection signal is output to one terminal of the OR circuit 91 and one terminal of the AND circuit 101.

That is, since the l → m → s detection signal becomes “1” at the boundary of the channel data in the bit data representing “1”, the signal is referred to as “1”. It is possible to detect the boundary of the bit data representing 1 ".

Next, the outline of the operation of the blocks after the operation gate 90 will be described with reference to the flowchart of FIG.

The flowchart shown in this figure shows the outline of the operation of the blocks after the operation gate 90. That is, in step S1, a portion where the cycle of the binarized signal is invariable for 6 cycles or more is detected (hunting processing). Since the position of the pulse (state of “1”) of the phase modulation signal is modulated according to the value of the bit data, the channel data always changes in the bit data. Therefore, if the period of the binarized signal does not change over six periods or more (six periods in case of 1 and eight periods in case of s), it is a boundary part of the bit data (YES), and In this case, the process proceeds to step S2.

For example, when the bit data is “10”, the channel data is “0110”, and at the boundary between the bit data (the boundary between “1” and “0”),
The state in which the outputs of the comparators 87 and 88 become s continues for eight periods, and then becomes the state of m and l. On the other hand, when the bit data is “01”, the channel data is “100”.
1 ", and at the boundary of the bit data, the comparator 87,
The state in which 88 is 1 continues for 6 cycles, and then m,
s state.

In step S1, the comparators 87, 88
Output signal continues the state of s for 8 periods, and then m,
When the state becomes 1, the count value of the timing counter 105 can be corrected by setting the value of the timing counter 105 to 5 when the state becomes the last 1. Similarly, in step S1, the comparator 8
When the output signals of 7, 88 continue the state of 1 for 6 cycles, and subsequently become the states of m and s, the value of the timing counter 105 is set to 4 at the time of the last state of s. Then, the count value of the timing counter 105 can be corrected. After the setting of the timing counter 105 is completed, the process proceeds to step S2. Step S1
In, if a state in which s or l continues for 6 cycles or more is not detected (NO), the process returns to step S1 and repeats the same processing.

In step S2, a boundary portion (zero cross point) of the bit data is observed, and it is determined whether or not a change in frequency can be detected (backward protection processing). That is, the frequency at which the binarized signal (FIG. 10C) changes at the zero-cross point is changed at the boundary between bit data (for example, “0” and “1” of the channel data in FIG. 10G). "A boundary portion of"), so that the value of the timing counter 105 set in step S1 is referred to,
A boundary portion of the bit data is detected, and it is determined whether a portion where the frequency of the binary signal changes in the detected boundary portion can be detected. If such a portion is not detected (NO), the process returns to step S2, and the same operation is repeated. If detected (YES), the value of the timing counter 105 is set to 0, and step S3 is performed. Proceed to.

In consideration of the case where there is an error in the detection in step S1, a certain error may be allowed for the detection of the boundary portion of the bit data in step S2. That is, when accurate detection is performed in step S1, the point in time when the value of the timing counter 105 changes from 7 to 0 corresponds to the boundary portion of the bit data. However, if an error occurs in step S1, the value of the timing counter 105 is not always accurate, and in consideration of such a case,
For example, when the value of the timing counter 105 changes from 6 to 7 or from 0 to 1, when a change in the cycle of the binarized signal is detected, YES is determined. Further, such processing may be repeatedly performed not only once but also plural times.

In step S3, it is determined whether or not the synchronization is normal (forward protection processing). That is, when the synchronization is normal, the following situations are unlikely to occur. Therefore, by detecting these states, it is determined whether the synchronization is normal. (A) The period of the binarized signal changes at a location other than the boundary of the bit data or near the center. (B) At the time when the value of the timing counter 105 changes from 1 to 2, the cycle of the binarized signal changes. (C) When the value of the timing counter 105 takes a value of 2 to 4, the state of the binarized signal causes a state change of s, m, l (usually, a state change of 1, m, s occurs) ). (D) When the value of the timing counter 105 takes a value of 3 to 5, the state of the binarized signal causes a state change of l, m, s (usually, a state change of s, m, l occurs) ).

Therefore, if the above state is detected (YES), it is determined that synchronization has been lost, and step S1 is performed.
And the same processing is repeated. Also,
If the above state is not detected (NO), the process returns to step S3 and the same processing is repeated.

Next, based on the above description, the operation of the block diagram of FIG. 9 will be described.

Now, it is assumed that the outputs of the flip-flops 103 and 104 are both "0". In that case, only the output of the terminal 0 of the encoder 106 is set to “1”. Note that, as described above, this encoder 106
According to the output signals of the flip-flops 103 and 104,
The output of any of the terminals 0 to 3 is set to “1”, and the current processing state (step 1 in the flowchart of FIG. 11) is set.
To S3). That is, if the output of the terminal 0 is “1” (the outputs of the flip-flops 103 and 104 are both “0”),
In which the output of the terminal 1 is "1" (the flip-flops 103 and 1).
04 (“1” and “0” respectively) indicates a state in which the process of step S2 is being executed. When the output of the terminal 3 is "1" (when the outputs of the flip-flops 103 and 104 are both "1"),
This shows a state where the process of step S3 is being executed.

It is not usually possible for the output of the terminal 2 to be "1", so that if the output of this terminal becomes "1", the process unconditionally returns to step S1 (flip-flop). The outputs of the loops 103 and 104 are both "0".)

Therefore, as described above, when the outputs of the flip-flops 103 and 104 are both "0", the output of the terminal 0 of the encoder 106 is "1", and the process of step S1 is executed. The status is indicated. At this time, the terminal 0 of the encoder 106 is connected to the logical product circuit 10
Since they are connected to one of the terminals 0 and 101, "1" is input to these terminals. Since the outputs of the terminals 1 to 3 are "0", the outputs of the AND circuit 99 to which the terminal 1 is connected and the output of the AND circuit 97 to which the output of the terminal 3 is supplied are "0". State.

In such a state, for example, if the s → m → l detection signal output from the operation gate 90 is “1”, the output of the AND circuit 100 becomes “1”.
As a result, the outputs of the OR circuits 93 and 94 also become "1".

The output of the OR circuit 94 is input to the load (LD) terminal of the timing counter 105, and "0" is output from the AND circuits 101 and 99 to the s0 and s1 terminals of the selector 102, respectively. Since it has been input, a terminal corresponding to the value of the input 2-bit data (the value (= s) when s0 is the lower bit and s1 is the upper bit) is selected and input to the selected terminal. The value (5 in this case because s = 0 in this case) is read and loaded into the timing counter 105 at the timing when the output of the OR circuit 94 rises. Therefore, encoder 1
When the output of the terminal 0 of 06 is in the state of “1”, s →
When the m → l detection signal becomes “1”, the value of the timing counter 105 is set to “5”.

Since the output of the OR circuit 93 is input to the set terminal of the flip-flop 103, the output of the flip-flop 103 outputs the timing at which the output signal of the inverter 80 rises (ie, the falling of the binarized signal). (Timing), the state becomes “1”. As described above, the output signal of the flip-flop 103 is input to the encoder 106 as lower bits. As a result, the 2-bit data input to the encoder 106 becomes “01”. Is in the state of "1" (that is, the process proceeds to step S2).

On the other hand, when the output of the terminal 0 of the encoder 106 is “1”, l
When the → m → s detection signal is set to “1” (l → m →
s is detected), the output of the AND circuit 101 becomes "1", and as a result, the OR circuits 93, 94
Is also in the state of "1".

The output of the OR circuit 94 is inputted to the load (LD) terminal of the timing counter 105, and the s0 and s1 terminals of the selector 102 are supplied from the AND circuit 101 and the AND circuit 99 respectively. Since "0" and "1" are input, data (= 4) is input from the terminal corresponding to the input 2-bit data value (= 1), and the timing is set at the timing when the output of the OR circuit 94 rises. It is loaded into the counter 105. Therefore, when the output of the terminal 0 of the encoder 106 is “1” and the l → m → s detection signal is “1”, the count value of the timing counter 105 is “4”. Will be set to

Further, since the output of the OR circuit 93 is input to the set terminal of the flip-flop 103, the output of the flip-flop 103 outputs the timing at which the output signal of the inverter 80 rises (ie, the falling of the binary signal). (Timing), the state becomes “1”. As described above, the output signal of the flip-flop 103 is input to the encoder 106 as lower bits. As a result, the 2-bit data input to the encoder 106 becomes “01”. Is in the state of "1" (that is, the process proceeds to step S2).

With the above operation, the flip-flop 10
Since the outputs of the terminals 3 and 104 are “1” and “0”, respectively, the output of the terminal 1 of the encoder 106 is “1”.
State. As a result, "1" is input to one terminal of the AND circuit 99.

Next, the processing of step S2 in the flowchart of FIG. 11 will be described.

From the terminal 1 of the encoder 107, the boundary portion of the bit data (when the value of the timing counter 105 is 7
In the portion where the signal changes from “0” to “0”, the WINDOW1 signal that is set to “1” is output. Terminal 2
Outputs a WINDOW2 signal that is in a state of “1” except at the boundary between the bit data and the center of the bit data (that is, when the value of the timing counter 105 is 1 to 3 or 6, 7). . Further, the terminal O
The UT outputs a gate signal that generates a pulse when the value of the timing counter 105 becomes 6, and is supplied to the gate circuit 64.

Now, suppose that the count value of the timing counter 105 becomes 0. In that case, the encoder 107
The signal WINDOW1 output from the terminal 1 of the logical AND circuit 98 is set to “1”.
“1” will be input. At this time, if the l → s / s → l detection signal output from the operation gate 90 is “1” (when the period of the binarized signal changes at the boundary of the bit data), the logic The output of the product circuit 98 becomes "1".

The output of the logical product circuit 98 is
Is input to the flip-flop 104 and the output of the AND circuit 99 is set to "1" (because the terminal of the encoder 106 is set to "1").

The output of the AND circuit 99 is output to the OR circuit 94.
And also input to the s1 terminal of the selector 102,
The selector 102 selects a terminal corresponding to a value (= 2) input from the s0 and s1 terminals, reads and outputs data (= 0). As a result, the timing counter 10
5 loads data 0 output from the selector 102 at the timing when the output of the OR circuit 94 rises.

Since the output of the AND circuit 98 is also supplied to the set terminal of the flip-flop 104, the output of the flip-flop 104 is set to "1". The data is "11". Then, the encoder 106 is connected to the terminal 3
Is set to the state of "1" (that is, the process proceeds to step S3).

That is, when the output of the terminal 1 of the encoder 106 is in the state of "1" (the state in which the processing of step S2 is being executed) and the WINDOW1 signal is in the state of "1" (the boundary of the bit data). If the l → s / s → l detection signal output from the operation gate 90 becomes “1” (when the period of the binarized signal changes), Terminal 3 output is "1"
, And the count value of the timing counter 105 is reset to 0.

Next, the processing in step S3 of the flowchart in FIG. 11 will be described.

The output of the terminal 3 of the encoder 106 is "1"
(When the process of step S3 is executed), "1" is input to one terminal of the AND circuit 97. Since the output signal of the AND circuit 96 is input to the other terminal of the AND circuit 97,
When the state of the signal input to the two input terminals of the AND circuit 96 becomes “1”, the output of the AND circuit 97 becomes “1”. That is, when the WINDOW2 signal is "1" and the output of the OR circuit 91 is "1", the output of the AND circuit 97 is "1".

The WINDOW2 signal becomes "1" when the count value of the timing counter 105 is 1 to 3, or 6,7. Also, the OR circuit 9
1 becomes “1” when any of the l → s / s → l detection signal, s → m → l detection signal, or l → m → s detection signal output from the operation gate 90 is output. This is the case when the state becomes “1”.

When the WINDOW2 signal is "1", the l → s / s → l detection signal, the s → m → l detection signal, and the l → m → s detection signal all become “0”. Is usually the case. Therefore, the case where the signals input to the AND circuit 96 both become "1" is when the synchronization is lost. In this case, the output of the AND circuit 97 is set to "1", and as a result, "1" is output from the OR circuit 92 and input to the reset (reset) terminals of the flip-flops 103 and 104, Step 10
The outputs of 3104 are both "0". Then, since the 2-bit data input to the encoder 106 is in the state of “00”, the encoder 106 sets the output of the terminal 0 to the state of “1” (return to the processing in step S1).

The output states of the flip-flops 103 and 104 are not normally "0" and "1", respectively. However, in such a state, the output of the terminal 2 of the encoder 106 is output. Becomes "1", as a result, the output of the OR circuit 92 becomes "1", and the flip-flops 103 and 104 are reset (return to the process of step S1).

With the above processing, the timing counter 105 is counted in synchronization with the binarized signal accurately. As described above, the encoder 107 generates a gate signal (FIG. 10 (j)) that generates a pulse when the count value of the timing counter 105 becomes 6, and supplies the gate signal to the gate circuit 64 (see FIG. 8).

The gate circuit 64 outputs the PLL edge signal (FIG. 10) when the gate signal becomes "1" (when the count value of the timing counter 105 becomes 6).
(K)) is output. As a result, the phase comparator 65, LP
F67, VCO 68, and PLL constituted by a frequency divider 66 provide a PLL output from gate circuit 64.
A clock signal that generates N pulses in one cycle of the edge signal (FIG. 10 (k)) is generated and output.

In the above embodiment, when the count value of the timing counter 105 is 6, a pulse of the gate signal is generated. This is because the delay in each element and the time required for the operation are considered.

According to the above-described embodiment, since the phase-modulated ADIP data is recorded on the disk as a pre-groove and is reproduced, it is possible to generate an accurate clock signal.

In the above embodiment, when the channel data (phase modulation signal) is 1, the FM modulation circuit 15 transmits 4 + 1/4 wave carriers during a period corresponding to half the length of the bit data. When the channel data is 0, a 4-1 / 4 carrier is output during a period corresponding to half the length of 1-bit data. However, it goes without saying that the invention is not limited to such a number of carriers. Generally, an n + d-wave carrier and an n-d-wave carrier signal may be generated according to the value of the channel data.

FIG. 12 is a block diagram showing an example of another configuration of a recording apparatus to which the present invention is applied. In this figure, the same parts as those in FIG. 6 are denoted by the same reference numerals, and the description thereof will be omitted.

In this figure, a synthesizing circuit 22 and a fine clock signal generating circuit 23 are newly added. Other configurations are the same as those in FIG. Further, the wobbling signal generation circuit 21 has the configuration shown in FIG. 3, as in the case described above.

As shown in FIG. 13, fine clock signal generating circuit 23 has a fine clock mark at the boundary (zero crossing) of bit data.
(A synchronization mark (hereinafter, referred to as a fine clock)) and supplies it to the synthesizing circuit 22. The synthesizing circuit 22 includes the fine clock signal generating circuit 2
3 is superimposed on the wobbling signal supplied from the wobbling signal generation circuit 21 and output to the recording circuit 24.

According to the configuration described above, the fine clock signal is superimposed on the boundary between the bit data in the ADIP data recorded on the master 26, so that the fine clock signal is detected during reproduction. As a result, the boundary portion of the bit data can be detected more accurately, so that a more accurate clock signal can be generated.

FIG. 14 is a block diagram showing an example of the configuration of a reproducing apparatus for reproducing ADIP data recorded by the recording apparatus shown in FIG. In this figure, the same parts as those in FIG. 7 are denoted by the same reference numerals, and the description thereof will be omitted.

In this drawing, a fine clock detection circuit 50 and a fine clock cycle detection circuit 51 are newly added. Other configurations are the same as those in FIG.

The fine clock detection circuit 50 detects a component corresponding to the fine clock signal from the RF signal reproduced and output by the optical head 32.

The fine clock cycle detection circuit 51 determines the periodicity of a detection pulse output when the fine clock detection circuit 50 detects a fine clock. That is, since the fine clock signal is generated at a fixed cycle, it is determined whether or not the detection pulse input from the fine clock detection circuit 50 is the detection pulse generated at the fixed cycle. If it is a detection pulse generated in, a pulse synchronized with the detection pulse is generated,
Output to the PLL circuit 40 at the subsequent stage. Further, the fine clock cycle detection circuit 51 generates a pseudo pulse at a predetermined timing so that the PLL circuit 40 at the subsequent stage does not lock to an incorrect phase when a detection pulse is not input at a fixed cycle. ing.

The PLL circuit 40 generates a clock signal based on the pulse signal output from the fine clock cycle detection circuit 51, supplies the clock signal to each unit of the device, and supplies it to the recording / reproducing circuit 33. The recording / reproducing circuit 33
With reference to the clock signal output from the L circuit 40 and the address data output from the address generation / read circuit 35, a (user) data recording area is detected.

As described above, by inserting the fine clock signal at the zero-cross point of the frequency modulation wave corresponding to the boundary of the bit data, the fluctuation of the amplitude of the fine clock signal is reduced, and the detection is facilitated.

In the above example, the case where the sync pattern (synchronous pattern) is not used has been described.
However, the present invention can also be applied to data using a sync pattern.

FIG. 15 is a diagram showing data when a sync pattern is inserted. In this embodiment, sync
“1100” is inserted as a pattern. In such a sync pattern, the channel data “11”
A phase shift occurs at the boundary between "00" and "00". However, by making the number of channel bits "1" and "0" constituting the sync pattern the same, the phase shift can be canceled at the end of the sync pattern. Therefore, syn
Accurate synchronization can be achieved in places other than the c-pattern, and if synchronization is achieved in other parts, an accurate clock signal can be generated.

However, when such a sync pattern is inserted, when the channel data is converted into bit data for some reason and there is a shift of one channel data, it becomes difficult to reproduce the original data. There are cases. An example of such a case is shown in FIGS. In FIGS. 16 and 17, a shift of one channel data occurs when the channel data is converted into the bit data. In such a case, as apparent from the examples of FIGS. 16 and 17, the bit data to be reproduced is completely different.

FIG. 18 shows another sync to which the present invention is applied.
It is a figure showing an example of a pattern.

In this embodiment, the first two bits of the sync pattern have the same value as the immediately preceding channel data. That is, in the example shown in FIG. 18, since the value of the channel data immediately before the sync pattern is “0”, “0011” in which the first two bits are “0” is inserted as the sync pattern. As a result, a portion where "0" continues over 3 bits is formed in the channel data. Therefore, when reproducing bit data from the channel data, it is possible to reproduce the bit data based on this portion. A shift in bit data can be prevented.

When the bit immediately before the sync pattern is “1”, “110” is set as the sync pattern.
If "0" is inserted, a portion where "1" is continuous over three bits is formed in the channel bit, so that data can be accurately written on the basis of this portion as described above. It becomes possible to reproduce.

According to such a sync pattern,
At the time of reproduction, no shift of channel data occurs, so that data can be reproduced accurately.

In the above embodiment, the pregroove 2 of the disk 1 is wobbled in accordance with the ADIP data. For example, ATIP (Absolute
Of course, the pregroove 2 may be wobbled according to time information such as Time in Pregroove.

[0143]

According to the first aspect of the present invention, the address data is phase-modulated, the bit data obtained as a result of the phase modulation is frequency-modulated, and the frequency modulation wave obtained as a result of the frequency modulation is used for pre-processing. Since the groove is wobbled and the start point and the end point of the bit data are set to the zero cross point of the frequency modulation wave, an accurate clock can be easily generated by detecting the zero cross point. . Further, the user data recording area can be accurately obtained from the accurate clock and address data.

According to the disk forming apparatus of the fifth aspect and the disk forming method of the sixth aspect, the address data is phase-modulated, and the start point and the end point of the bit data obtained as a result of the phase modulation are frequency-modulated. Pre-grooves are wobbled with the frequency-modulated wave obtained as a result of frequency modulation so that the zero-cross point of the wave is obtained.This makes it possible to easily and accurately generate a clock from address data. At the same time, it is possible to play the disc stably.

According to the disk recording / reproducing apparatus of the seventh aspect and the disk recording / reproducing method of the ninth aspect,
Read the address data recorded on the disc,
Since the boundary portion of the bit data constituting the read address data is detected and the clock signal is generated based on the detected boundary portion of the bit data,
An accurate clock signal is generated, and various controls can be accurately performed based on the clock signal. Also,
When data is randomly recorded on a write-once disc or a rewritable disc, a decrease in recording capacity can be prevented.

[Brief description of the drawings]

FIG. 1 is a diagram showing an example of the configuration of a disk to which the present invention has been applied.

FIG. 2 is a diagram showing an example of a data format of a wobbling signal recorded on the disc shown in FIG.

FIG. 3 is a block diagram illustrating an example of a configuration of a circuit that generates a wobbling signal.

4 is a diagram showing a signal generated by a phase modulation circuit 13 shown in FIG.

FIG. 5 is a timing chart showing a relationship between channel data and a clock signal generated based on the channel data.

FIG. 6 is a block diagram showing an example of a configuration of a recording apparatus for forming a pre-groove on a master 26;

FIG. 7 is a block diagram illustrating an example of a configuration of a playback device that plays back information recorded by the recording device illustrated in FIG. 6;

8 is a block diagram showing an example of a detailed configuration of a PLL circuit 40 shown in FIG.

9 is a block diagram showing an example of a detailed configuration of a gate signal generation circuit 63 shown in FIG.

10 is a timing chart showing signal timings of main parts of the block diagram shown in FIG. 9;

FIG. 11 is a flowchart illustrating an outline of processing executed in the block diagram shown in FIG. 9;

FIG. 12 is a block diagram showing an example of another configuration of a recording apparatus for forming a pre-groove on a master 26;

FIG. 13 is a diagram illustrating a fine clock mark inserted according to the block diagram shown in FIG. 12;

14 is a diagram showing an example of the configuration of a playback device for playing back information recorded according to the block diagram shown in FIG.

FIG. 15 is a diagram illustrating an example of insertion of a sync pattern.

FIG. 16 is a diagram showing an example of reproduced data when the sync pattern shown in FIG. 15 is inserted.

17 is a diagram showing another example of the reproduction data when the sync pattern shown in FIG. 15 is inserted.

FIG. 18 is a diagram showing another example of the insertion of the sync pattern.

FIG. 19 is a diagram illustrating an example of a configuration of a conventional clock generation device.

20 is a timing chart showing signal timings of main parts of the block diagram of FIG. 19;

FIG. 21 is a diagram showing a relationship between channel data and bit data modulated by a conventional modulation method.

[Explanation of symbols]

13 phase modulation circuit (phase modulation means, phase modulation step), 15 FM modulation circuit (frequency modulation means, frequency modulation step), 25 optical head (wobbling means, wobbling step), 32 optical head (reading means, reading step), 68 VCO (clock generation means, clock generation step), 90 operation gate (detection means, detection step)

Claims (9)

[Claims] 1. A disk in which tracks for recording data are formed in advance and wobbled in correspondence with address data, the address data is phase-modulated, and the frequency is determined by the channel data obtained as a result of the phase modulation. The modulation is performed, the track is wobbled by the frequency modulation wave obtained as a result of the frequency modulation, and the start point and the end point of the bit data of the address data are both zero cross points of the frequency modulation wave. A disk characterized by the above-mentioned. 2. The disk according to claim 1, wherein a synchronization mark is recorded near a zero cross point of the frequency modulation wave corresponding to a boundary portion of the bit data. 3. The disk according to claim 1, wherein a synchronization pattern for synchronizing is inserted in the address data. 4. The disk according to claim 3, wherein at least the first two-channel data of the synchronization pattern has the same value as the immediately preceding channel data. 5. A disk forming apparatus for forming a disk in which tracks for recording data are formed in advance and wobbled in accordance with address data, a phase modulating means for phase modulating the address data, Frequency modulation means for performing frequency modulation so that the start point and the end point of the bit data of the address data are both zero cross points of the frequency modulation wave, based on the channel data obtained as a result of the phase modulation by the phase modulation means; A wobbling means for wobbling the track with a frequency modulated wave obtained as a result of frequency modulation by the modulation means. 6. A disk forming method for forming a disk in which tracks for recording data are formed in advance and wobbled in accordance with address data, wherein: a phase modulation step of phase-modulating the address data; A frequency modulation step of performing frequency modulation so that a start point and an end point of the bit data of the address data are both zero-cross points of a frequency modulation wave by the channel data obtained as a result of the phase modulation by the phase modulation step; A wobbling step of wobbling the track with a frequency modulated wave obtained as a result of frequency modulation by the modulation step. 7. A disk in which tracks for recording data are formed in advance and wobbled corresponding to address data, wherein the address data is phase-modulated, and channel data obtained as a result of the phase modulation is provided. The track is wobbled by the frequency modulation wave obtained as a result of the frequency modulation, and the start point and the end point of the bit data of the address data are both set to the zero cross points of the frequency modulation wave. A disk recording / reproducing apparatus for recording or reproducing information on / from a disk, comprising: reading means for reading the address data recorded on the disk; and detecting a boundary portion of bit data of the address data read by the reading means. Detecting means, and the detecting means Disk recording and reproducing apparatus in which the boundary portion of the bit data issued based on the characterized in that it comprises a clock generation means for generating a clock signal. 8. The disk recording / reproducing apparatus according to claim 7, wherein said detecting means detects a boundary portion of said bit data based on regularity of said phase-modulated address data. 9. A disk in which tracks for recording data are formed in advance and wobbled in correspondence with address data, wherein the address data is phase-modulated, and channel data obtained as a result of the phase modulation is provided. The track is wobbled by the frequency modulation wave obtained as a result of the frequency modulation, and the start point and the end point of the bit data of the address data are both set to the zero cross points of the frequency modulation wave. A disc recording / reproducing method for recording / reproducing information on / from a disc, comprising: a reading step of reading address data recorded on the disc; and detecting a boundary portion of bit data of the address data read in the reading step. A detecting step; Disk recording and reproducing method characterized by Tsu based on the boundary of the detected bit data by flop and a clock generation step of generating a clock signal.