JPH10164458A - Video signal processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suitably control the level of input composite video signal by shortening the time constant of a peak automatic gain control(AGC) loop system, including a data-generating means for peak AGC rather than the time constant of sync AGC loop system, including a data generating means for sync AGC. SOLUTION: A timing control circuit 26 generates respective timing signals, corresponding to a synchronization signal input (VBLANK, HD) from a synchronizing separator circuit 6 and the time constant from a time constant control circuit 27. The time constant of a peak AGC loop is set to the time constant control circuit 27 rather than the time constant of sync AGC loop system, in order to make the peak AGC more preferential rather than the sync AGC, when a real peak value is larger than a reference peak value. Thus, the level of input composite video signal can be suitably controlled by operating the peak AGC during the sync AGC loop with a sync chip as a reference.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a video signal processing apparatus for maintaining a level of an input composite video signal constant.

[0002]

2. Description of the Related Art Conventionally, as a configuration for maintaining a level of an input composite video signal constant, a sync (Sync) AGC (auto gain control) for maintaining a level between a sync tip and a pedestal of the signal is fixed. , Peak AGC for keeping the overall level of the composite video signal constant
It is common to control by combining the above.

[0003]

When all the level values are determined with reference to the sync chip, the relationship between the pedestal value of the input composite video signal and the peak value of the video signal is shown in FIG. As shown, when the actual pedestal value is lower than the pedestal reference value and the actual peak value is higher than the peak reference value, the peak AGC causes
As shown in (b), the operation of lowering the actual peak value to the peak reference value as shown by the arrow X occurs, while the sink AG
C causes an operation to increase the actual pedestal value to the pedestal reference value as shown by an arrow Y as shown in FIG. 1C, and these two operations are repeated. Therefore, there is a problem that the level control becomes unstable and oscillates in such a combination of the two AGC operations.

Accordingly, an object of the present invention is to provide a video signal processing device capable of appropriately controlling the level of an input composite video signal.

[0005]

A video signal processing apparatus according to the present invention comprises an analog amplifying means for amplifying an input analog composite video signal, and an A / D converting means for digitizing an output signal of the analog amplifying means. A Y / C separating means for separating and extracting a luminance signal and a chrominance signal from the composite video signal digitized by the A / D converting means, and according to the pedestal value so that the pedestal value of the luminance signal is controlled to the pedestal reference value. AGC data generating means for generating the sync AGC data, and a peak AGC data generating means for generating peak AGC data according to the peak value so that the peak value of the luminance signal is controlled to the peak reference value. , Sink AGC data and peak AG
A control means for controlling a gain of an analog amplifying means in accordance with C data, wherein a time constant of a peak AGC loop system including a peak AGC data generating means has a sink AGC data generating means. , Which is shorter than the time constant of the sink AGC loop system.

[0006]

Embodiments of the present invention will be described below in detail with reference to the drawings. In the video signal processing device shown in FIG. 2, an input analog composite video signal is supplied to an analog control amplifier 1. The analog control amplifier 1 amplifies the input analog composite video signal with the gain selected by the gain control switch 2. An analog / digital converter (ADC) is provided at the output of the analog control amplifier 1.
3 are connected, and the amplified analog composite video signal is digitized. The output of the analog / digital converter 3 is connected to a sync tip clamp 4, a Y / C separation circuit 5, and a synchronization separation circuit 6. The sync tip clamp 4 keeps the sync tip value, which is the bottom level of the composite video signal, constant. The Y / C separation circuit 5 converts a luminance signal component Y and a chrominance signal component C from the digitized video signal.
And is extracted separately. The sync separation circuit 6 separates and extracts a sync signal component from the digitized video signal.

The luminance signal component Y output from the Y / C separation circuit 5 is level-converted by a luminance level conversion circuit 7 and output as a luminance signal. The color signal component C output from the Y / C separation circuit 5 is converted by a color decoder 8 into an RY signal and a BY signal, which are digital color difference signals, and output. Further, each line pedestal average value detector 11 and each line peak average value detector 12 are connected to the luminance signal component output of the Y / C separation circuit 5.
The pedestal average value detector 11 extracts 16 pedestal value data for each line of the luminance signal and takes the average value. The output of the pedestal average detector 11 is further connected to a 256 line pedestal average detector 13 where each line pedestal average detector 11 is connected.
The average value of 256 lines of the pedestal average value for each line obtained in the above is obtained. This is to remove low frequency noise in the video signal. The average value of the 256 line pedestal average value detector 13 is calculated by the data extractor 14.
Is extracted by The extraction timing is controlled according to a timing signal output from a timing control circuit 26 described later so that the timing is an integral multiple of the vertical blanking period signal VBLANK. The output of the data extractor 14 is connected to a comparator 15 and a difference detector 16. The comparator 15 compares the value extracted by the data extractor 14 with the pedestal reference value, and supplies the comparison result to the control direction detector 17. The control direction detector 17 is a comparator 15
The current control direction is detected from the output state of. That is,
The output value of the comparator 15 is classified into three types of values, an upward value, an intermediate value, and a downward value, and a signal indicating a classification result is generated.
A horizontal filter 18 is connected to the control direction detector 17. The horizontal filter 18 accumulates the output signal values of the control direction detector 17 in the horizontal direction five times, determines the control direction if the value is the same five times in succession, and generates the control direction data when the determination is made. .

The difference detector 16 holds the value extracted by the data extractor 14 and detects the magnitude (absolute value) of the difference between the current extracted value and the previous extracted value. The output signal of the difference detector 16 is supplied to the gain amplifier control signal generator 19 together with the output signals of the control direction detector 17 and the horizontal filter 18. The data extractor 14 is connected to a synchronous slicer data generator 21. The synchronization slicer data generator 21 holds the data value obtained in the data extractor 14 and generates slice data of the synchronization signal of the synchronization separation circuit 6. The output of the data extractor 14 is connected to a luminance signal slicer data generator 22. The luminance signal slicer data generator 22 holds the extracted value obtained by the data extractor 14 and creates a slice signal for the luminance signal by passing the extracted value through a filter for each of the four extracted values. The slice data for the luminance signal is supplied to the luminance level conversion circuit 7.

The line peak average detector 12 samples the luminance signal level from the Y / C separation circuit 5 in synchronism with the master clock for each line of the luminance signal, and the sampled value is continuously sampled for three or more samples. When the value is exceeded, a signal indicating "1" is output. The reason for confirming that the peak reference value is continuously exceeded for three or more samplings is that high frequency noise in the video signal is considered. The output signal of the line peak average value detector 12 is supplied to a peak integrated value detector 23. Peak integrated value detector 2
Numeral 3 integrates the output values of the line peak average detector 12 to detect the integrated value. This detection timing is controlled in accordance with the timing signal output from the timing control circuit 26 so that the timing becomes an integral multiple of the vertical blanking period signal VBLANK. If the detected integrated value exceeds the reference value, the peak integrated value detector 23 outputs a signal indicating “1”, and otherwise outputs a signal indicating 0. The difference detector 24 is connected to the peak integrated value detector 23. The difference detector 24 is a peak integrated value detector 2
3, a signal indicating "1" when the previous detection result is "0" and the current detection result is "1" by comparing the previous detection result with the current detection result. (Peak lowering data), and outputs a signal indicating 0 otherwise. That is, when there was a peak in the previous time, but it disappeared this time, it is detected. Each detection signal of the peak integrated value detector 23 and the difference detector 24 is supplied to a gain amplifier control signal generator 19.

The gain amplifier control signal generator 19 provides a gain to the gain control switch 2 according to each output signal of the difference detectors 16 and 24, the control direction detector 17, the horizontal filter 18 and the peak integrated value detector 23. It outputs control data and outputs an enable signal to the luminance signal slicer data generator 22 for controlling whether or not to output slice data.

Each line pedestal average value detector 11,
Each line peak average detector 12, 256 line pedestal average detector 13, data extractor 14, and peak integrated value detector 23 include the above-described timing control circuit 26.
Supplies timing signals individually. The timing control circuit 26 generates each timing signal according to the time constant set by the time constant control circuit 27 together with the vertical blanking period signal VBLANK and the horizontal synchronization signal HD output from the synchronization separation circuit 6. Time constant information for the sink AGC and the peak AGC is externally input to the time constant control circuit 27, and an appropriate time constant is set in the time constant control circuit 27 according to the input time constant information. Is done.

Further, a video signal detector 28 for detecting the start of supply of a video signal is connected to the sync separation circuit 6. The video signal detector 28 generates a video signal detection signal when a video signal is detected in the sync separation operation by the sync separation circuit 6. An output of the video signal detector 28 is connected to an initial control circuit 29. Initial control circuit 2
Reference numeral 9 sets an initial value to the output level of each circuit according to a video signal detection signal or an external master reset. This is to enable a stable control operation immediately after the start of input of the composite video signal.

Next, the operation of such an apparatus will be described with reference to waveform diagrams. The input composite video signal is first supplied to the analog control amplifier 1, where it is amplified by the analog control amplifier 1 with a gain corresponding to the selected state of the gain control switch 2. The video signal passed through the analog control amplifier 1 is digitized by an analog / digital converter 3. The digitized composite video signal is supplied to a Y / C separation circuit 5 and a synchronization separation circuit 6 and is clamped by a sync tip clamp 4 so that the sync tip position of the composite video signal becomes constant. In the Y / C separation circuit 5, a luminance signal Y and a chrominance signal C are converted from the digitized composite video signal.
Are separated and extracted, and the synchronization separation circuit 6 separates and extracts the synchronization signal from the digitized video signal.

When the digital luminance signal Y output from the Y / C separation circuit 5 has a waveform as shown in FIG. 3A, each line pedestal average detector 11 detects a line (horizontal scanning period). ), 16 pedestal values are sampled and the average value is calculated. Once the average pedestal is obtained for each line,
In the 256-line pedestal average detector 13, FIG.
As shown in (b), the pedestal average value for each line is added for 256 lines, and the addition result is divided by 256 to calculate the pedestal average value for 256 lines. Therefore, as shown in FIG.
The pedestal average value for 56 lines is output in the next 256 line period.

The data extractor 14 extracts the pedestal average value of 256 lines at a timing that is an integral multiple of the vertical blanking period signal VBLANK as shown in FIG. This is because it is desired to perform a gain control operation during the vertical blanking period. The extracted average value is compared with the pedestal reference value by the comparator 15. In this comparison, the average value is 8-bit data, and the lower 2 bits are each set to 0. As shown in FIG. 3 (e), the comparison result is an upward value in which the extracted average value is larger than the pedestal reference value, an intermediate value in which the extracted average value is the same as the pedestal reference value, and an extracted average value in which the extracted average value is the pedestal reference value. Control direction detector 1 which is obtained as any of the smaller downward values.
7 outputs the control direction data of 3 bits to the gate amplifier control signal generator 19 at the timing shown in FIG. 3F, that is, every period T1 according to the comparison result.

The output signal of the control direction detector 17 is supplied to a horizontal filter 18. The horizontal filter 18 integrates the output signal value of the control direction detector 17 in the horizontal direction five times as shown in FIG. If the same value is obtained five times in a row, the control direction is determined. When the control direction is determined, 3-bit control direction data is supplied to the gate amplifier control signal generator 19 at the timing shown in FIG. Output to

The data value obtained by the data extractor 14 is converted by a synchronous slicer data generator 21 as shown in FIG.
The data is held only for the period shown in (i), and the held data is supplied to the synchronization separation circuit 6 as slice data. Therefore, the sync separation circuit 6 separates the sync signal from the digitized video signal according to the supplied slice data. This makes it possible to reliably extract a synchronization signal from a received video signal having a low electric field strength or a video signal containing noise in a television receiver. FIGS. 4C and 4D correspond to the waveforms shown in FIGS. 3C and 3D, respectively.

The value extracted by the data extractor 14 is held by the difference detector 16 as the current extracted value and the previous extracted value, as shown in FIG. The absolute value of the difference is calculated. As shown in FIG. 4K, when the absolute value of the difference is larger than the reference value, a signal indicating “1” is output from the difference detector 16. Further, the value extracted by the data extractor 14 is held by the luminance signal slicer data generator 22 as shown in FIG.
Each of the four extracted values is integrated by passing through a filter, and the slice data for the luminance signal as the integration result is obtained as shown in FIG.
It is created as shown in FIG. The slice data is supplied to the luminance level conversion circuit 7 when the gain amplifier control signal generator 19 supplies the enable signal shown in FIG. As will be described later, the luminance level conversion circuit 7 sets a value determined by the supplied slice data as a pedestal value, and adjusts the level so that the black level of the luminance signal is adjusted to the pedestal value.

In the line peak average value detector 12, the luminance signal level from the Y / C separation circuit 5 is
As shown in (o), only three points are sampled for each line in synchronization with the master clock. As shown in FIG. 5 (p), if the sample value of each line exceeds the peak reference value for three consecutive samplings, each line is
A signal indicating 1 is output at the timing indicated by hatching in (q).

The output value of the line peak average detector 12 is integrated by a peak integrated detector 23. The integrated value is detected at a timing that is an integral multiple of the vertical blanking period signal VBLANK. Therefore, the vertical blanking period signal VBL
If the timing of the integral multiple of ANK is a timing (hatched portion) as shown in FIG. 5 (s), the integration of the output values of the line peak average detector 12 is repeated every period shown in FIG. 5 (r). . When the integrated value exceeds the reference value, the peak integrated value detector 23 immediately outputs a detection value indicating "1" as shown in FIG. 5 (t).

The detection value of the peak integrated value detector 23 is held by the difference detector 24 as the current detection value and the previous detection value as shown in FIG. Is compared with As shown in FIG. 5 (v), when the previous detection value is 0 and the current detection value is “1”, that is, when there was a peak in the previous time but it has disappeared this time, FIG. Is output, and otherwise, a signal indicating 0 is output.

The gain amplifier control signal generator 19 uses the 3-bit control direction data output from the control direction detector 17 and the data output timing t as shown in FIG. Read 24 output signals,
As shown in FIG. 5 (y), every time reading is performed, the difference detector 2
4 is used as a peak prediction signal. Specifically, the control operation is performed as shown in Table 1 below.

Here, the signal A is 3-bit peak gain prediction data output from the control direction detector 17, and is "10" when the pedestal value is higher than the reference value.
The value is “010” for an intermediate value and “001” for a downward value. The signal B is 3-bit data output from the horizontal filter 18. The direction determined from the integrated value is “100” in the upward direction, “010” in the middle, and “00” in the downward direction.
1 '. The signal C is a difference detector 16 for the pedestal.
Is 1-bit data, and indicates '1' when the absolute value of the difference between the current value and the previous value is larger than the reference value. The signal D is 1-bit data output from the peak integrated value detector 23, and indicates “1” if the peak value is larger than the reference value. The signal E is 1-bit data output from the peak difference detector 24, and indicates "1" when the previous value is "1" and the current value is 0. The signal F is a one-bit enable signal output from the gain amplifier control signal generator 19, and enables the output of slice data from the luminance signal slicer data generator 22 when indicating "1". The signal G is a gain amplifier control signal generator 1
9 is gain control data of 6 bits outputted from
It is supplied to the gain control switch 2. 'X' in Table 1 means ignored.

[0024]

[Table 1]

By lowering the gain of the analog control amplifier 1 via the gain control switch 2, the level of the composite video signal output from the analog control amplifier 1 is lowered, and by increasing the gain of the analog control amplifier 1, analog control is performed. The level of the composite video signal output from the amplifier 1 rises. When the signal D = 1, the signal E = 1, and the signal A = 001, the gain of the analog control amplifier 1 is not controlled.

According to the control operation shown in Table 1, when the actual peak value is larger than the peak reference value based on the output signal D of the peak integrated value detector 23, the peak AGC has priority over the sink AGC, and the analog control is performed. The gain of the amplifier 1 is reduced. In order to give priority to the peak AGC, the time constant of the peak AGC loop is set shorter (for example, 1/6 of the time constant of the sink AGC loop) than the time constant of the sink AGC loop. This is because the horizontal filter 18 is inserted and the output signal B is monitored. As shown in FIG. 6, the sink AGC operates while the actual peak value does not exceed the peak reference value, and when the actual peak value exceeds the peak reference value, the peak AGC operates immediately to control the peak value to the reference value. Then, the peak value is maintained at the reference value with reference to the output signal A of the control direction detector 17 (that is, peak hold).

When the operation of the peak AGC is prioritized and the peak hold state is established, according to this device, the pedestal value becomes lower than the pedestal reference value as shown in FIG. Will not match. Therefore, the enable signal F is set to “1”.
As shown in FIG. 7C, control is performed such that the pedestal value of the input video signal is set to the black level. That is, the pedestal reference value is reduced by an amount indicated by hatching H. As a result, it is possible to appropriately display an image in the black level portion. It should be noted that a constant time constant and a dead zone are provided as in a period T2 shown in FIG. 7B so that the black level does not frequently move due to the execution of this control and noise does not occur. That is, if the time constant is set so as to decrease by one step for each field in accordance with the actual pedestal value, and if the difference between the actual pedestal value and the pedestal reference value is within ± 4 codes, no operation is performed.

If the resolution (each step in FIG. 8) of the analog / digital converter 3 is smaller than the gain step setting of the analog control amplifier 1 (gain step a in FIG. 8), it is shown by a solid line in FIG. As described above, the gain of the analog control amplifier rises and falls, the gain control loop becomes unstable, and the video signal oscillates. However, according to such a device according to the invention, the comparator 15
Since the gain of the analog control amplifier 1 is controlled according to the value obtained by reducing the pedestal average value for every six lines to 1/4,
As shown in FIG. 9, it is prevented that the gain of the analog control amplifier 1 fluctuates stably. Also, horizontal filter 1
8, if the control direction is the same in the horizontal direction five times in a row,
A signal B for determining a new gain direction is obtained. Therefore, as shown in FIG. 10, even if a video signal whose gain changes suddenly arrives, it does not respond to the signal, so that it is possible to prevent the video signal output from the apparatus from suddenly fluctuating.

As described above, according to the present invention, the peak AGC is performed in the loop of the sink AGC based on the sync chip.
Operates so that the level of the input composite video signal can be appropriately controlled. The present invention relates to a television receiver, a video tape recorder (VTR), an NTS
The present invention can be applied to a device such as a C / PAL decoder.

[Brief description of the drawings]

FIG. 1 is a waveform chart showing the operation of a conventional device.

FIG. 2 is a block diagram showing an embodiment of the present invention.

FIG. 3 is a waveform and timing chart for explaining the operation of the device of FIG. 2;

FIG. 4 is a waveform and timing diagram subsequent to FIG. 3 for explaining the operation of the device of FIG. 2;

5 is a waveform and timing chart subsequent to FIG. 4 for explaining the operation of the apparatus of FIG. 2;

FIG. 6 is a waveform diagram illustrating a case where peak AGC operates.

FIG. 7 is a waveform diagram illustrating control for setting a pedestal value to a black level.

FIG. 8 is a diagram showing an example of a conventional gain change of an analog control amplifier.

9 is a diagram illustrating an example of a change in gain of an analog control amplifier by the device of FIG. 2;

10 is a diagram illustrating an example of a change in gain of an analog control amplifier by the device of FIG. 2;

[Description of Signs of Main Parts]

 DESCRIPTION OF SYMBOLS 1 Analog control amplifier 2 Gain control switch 3 Analog / digital converter 4 Sync tip clamp 5 Y / C separation circuit 6 Synchronization separation circuit 7 Brightness level conversion circuit 16, 24 Difference detector 17 Control direction detector 18 Horizontal filter 19 Gain amplifier Control signal generator 21 Data generator for synchronous slicer 22 Data generator for luminance signal slicer 23 Peak integrated value detector 26 Timing control circuit 27 Time constant control circuit

Claims (6)

[Claims] 1. An analog amplifying means for amplifying an inputted analog composite video signal, and an A for digitizing an output signal of the analog amplifying means.
/ D (analog / digital) conversion means; Y / C for separating and extracting a luminance signal and a chrominance signal from the composite video signal digitized by the A / D conversion means
Separating means, and a sink A corresponding to the pedestal value such that the pedestal value of the luminance signal is controlled to a pedestal reference value.
A sync AGC data generating means for generating data for an automatic gain control (GC); and a peak AGC for generating peak AGC data corresponding to the peak value so that the peak value of the luminance signal is controlled to a peak reference value. A video signal processing device comprising: data generating means for controlling the gain of the analog amplifying means according to the data for sink AGC and the data for peak AGC; Peak AGC including means
A video signal processing apparatus, wherein a time constant of a loop system is shorter than a time constant of a sync AGC loop system including the sync AGC data generating means. 2. A data generator for sink AGC detects a pedestal average value by averaging the pedestal value of the luminance signal for each line, and further averages the pedestal average value of the plurality of lines for each of a plurality of lines. Pedestal averaging means for detecting the average value of the plurality of lines pedestal, extracting means for extracting the average value of the plurality of pedestals at a predetermined timing, and comparing means for comparing the extracted value of the extracting means with the pedestal reference value. A difference detection unit that outputs difference data indicating whether an absolute value of a difference between a previous value and a current value of the extraction value of the extraction unit at each of the predetermined timings is greater than a reference value, Control direction detecting means for detecting a control direction of the sink AGC according to a result and outputting first control direction data; And C means for outputting second control direction data indicating the direction when the control direction of C is the same direction continuously for a plurality of times, wherein the difference data and the first and second control direction data are synchronized by AGC. The peak AGC data generation means, a peak averaging means for averaging a peak value of the luminance signal for each line to detect a peak average value, and a predetermined timing by integrating the peak average value. An integration comparing means for comparing an integrated value of each of the peaks with the peak reference value and outputting a result of the comparison, and calculating the integrated value from a state where the comparison result of the integration comparing means is larger than the peak reference value. Means for outputting peak reduction data when detecting a change to a state below the peak reference value, wherein a comparison result of the integration comparing means and the peak reduction data are provided. The peak AGC data, and the control means, when the comparison result of the integration comparison means is equal to or less than the peak reference value, the analog amplification in accordance with the control direction data output from the filter means. Means for controlling the gain of the analog amplifying means according to the first and second control direction data and the peak drop data when the result of the integration by the integration comparing means is greater than the integrated value by the peak reference value. The video signal processing device according to claim 1, wherein the video signal processing device controls a gain. 3. The control means, wherein the first control direction data indicates a downward direction, a comparison result of the integration comparison means indicates that the integrated value is greater than the peak reference value, and the peak decrease Means for generating an enable signal when data is output, wherein the video signal processing device further holds a slice value for synchronization for holding an extraction value of the extraction means and outputting it as slice data for synchronization signal Means and the A / D
Synchronization separating means for separating and extracting a synchronizing signal from the composite video signal digitized by the converting means in accordance with the level indicated by the synchronizing signal slice data; and holding the extracted value of the extracting means and integrating every four values. Luminance signal slice data generating means for outputting it as luminance signal slice data when generating the enable signal; luminance level converting means for converting the luminance signal level according to the level indicated by the luminance signal slice data;
The video signal processing device according to claim 1, further comprising: 4. The video signal processing apparatus according to claim 1, wherein said predetermined timing is a timing which is an integral multiple of a vertical blanking period signal of said analog composite video signal. 5. The video signal processing apparatus according to claim 1, further comprising a sync tip clamping means for holding a sync tip value of the composite video signal digitized by said A / D conversion means constant. 6. The video signal processing apparatus according to claim 1, further comprising an initial setting means for setting an initial value to each means in the apparatus when the analog composite video signal is input.