JPH10164385A - Vertical output circuit - Google Patents

Vertical output circuit

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Publication number
JPH10164385A
JPH10164385A JP32036096A JP32036096A JPH10164385A JP H10164385 A JPH10164385 A JP H10164385A JP 32036096 A JP32036096 A JP 32036096A JP 32036096 A JP32036096 A JP 32036096A JP H10164385 A JPH10164385 A JP H10164385A
Authority
JP
Japan
Prior art keywords
vertical
output signal
push
transistor
pull amplifier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP32036096A
Other languages
Japanese (ja)
Other versions
JP3439055B2 (en
Inventor
Norio Imaizumi
教男 今泉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP32036096A priority Critical patent/JP3439055B2/en
Publication of JPH10164385A publication Critical patent/JPH10164385A/en
Application granted granted Critical
Publication of JP3439055B2 publication Critical patent/JP3439055B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Abstract

PROBLEM TO BE SOLVED: To reduce power consumption by D-class operating a push-pull amplifier. SOLUTION: In order to lower the power consumption, the push-pull amplifier for driving a vertical deflection coil is D-class operated. Vertical sawtooth- shaped waves are converted into pulse signals by a PWM modulator 10 and impressed to the push-pull amplifier. The vertical sawtooth-shaped waves formed based on vertical synchronizing signals are impressed to a terminal 12, PWM- modulated, turned to the pulse signals and impressed to a window comparator 13. First and second comparators 14 and 15 for constituting the window comparator 13 respectively perform the comparison of two input signal levels and impress the compared results to a first transistor 18 and a second transistor 19 as 'H' and 'L.' In this case, so as to prevent the two transistors from being simultaneously turned ON, when the ON/OFF of the transistors are inverted, the two transistors are temporarily turned OFF altogether and then, turned ON.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、ブラウン管を使用
するTV受像機や、モニター機器の垂直出力回路に関す
るもので、特に低消費電力であるとともに出力トランジ
スタの破壊が防止できる垂直出力回路に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vertical output circuit of a TV receiver or a monitor using a cathode ray tube, and more particularly to a vertical output circuit which consumes low power and can prevent destruction of an output transistor.

【0002】[0002]

【従来の技術】TV受像機やモニター機器のブラウン管
に垂直方向の偏向を行わせる垂直出力回路が使用されて
いる。図2は、そのような垂直出力回路の原理図を示し
ている。図2の端子(1)には垂直同期信号に基づいて
作られたノコギリ波が印加される。ノコギリ波は、トラ
ンジスタ(2)を介してトランジスタ(3)及び(4)
を駆動する。トランジスタ(3)の出力信号に応じてト
ランジスタ(5)がオンオフ動作し、トランジスタ
(4)の出力信号に応じてトランジスタ(6)がオンオ
フ動作する。
2. Description of the Related Art A vertical output circuit is used to cause a cathode ray tube of a TV receiver or a monitor to deflect vertically. FIG. 2 shows a principle diagram of such a vertical output circuit. A sawtooth wave generated based on the vertical synchronization signal is applied to the terminal (1) in FIG. The sawtooth wave is applied to the transistors (3) and (4) via the transistor (2).
Drive. The transistor (5) turns on and off according to the output signal of the transistor (3), and the transistor (6) turns on and off according to the output signal of the transistor (4).

【0003】トランジスタ(5)(6)で増幅されたノ
コギリ波は、垂直偏向電流として垂直偏向コイル
(7)、コンデンサ(8)及び抵抗(9)に流れる。垂
直偏向コイル(7)は、ブラウン管(図示せず)に取り
付けられており、電子ビームの垂直偏向を行う。アイド
リング回路(10)は、トランジスタ(5)(6)のベ
ース・ベース間の電圧差が2VBE(VBEは、トランジス
タの立ち上がり電圧)程度となるように確保するもので
ある。アイドリング回路(10)の存在により、トラン
ジスタ(5)(6)のコレクタ・エミッタ路にアイドリ
ング電流が流れスイッチング時のクロスオーバー歪みが
低減される。
The sawtooth wave amplified by the transistors (5) and (6) flows as a vertical deflection current to a vertical deflection coil (7), a capacitor (8), and a resistor (9). The vertical deflection coil (7) is attached to a cathode ray tube (not shown) and performs vertical deflection of the electron beam. The idling circuit (10) ensures that the voltage difference between the bases of the transistors (5) and (6) is about 2 VBE (VBE is the rising voltage of the transistor). Due to the presence of the idling circuit (10), an idling current flows through the collector-emitter paths of the transistors (5) and (6) to reduce crossover distortion during switching.

【0004】尚、図2の(10)はICを示す。従っ
て、図2の回路によれば、ブラウン管における垂直方向
の偏向を直線性良く行わせることができる。
FIG. 2 (10) shows an IC. Therefore, according to the circuit shown in FIG. 2, the vertical deflection in the cathode ray tube can be performed with good linearity.

【0005】[0005]

【発明が解決しようとする課題】しかしながら、図2の
装置ではトランジスタ(5)(6)がノコギリ波をリニ
アに増幅するB級動作を行っているので消費電力量が多
くなってしまう、という問題があった。
However, in the device shown in FIG. 2, the transistors (5) and (6) perform the class B operation of linearly amplifying the sawtooth wave, so that the power consumption increases. was there.

【0006】[0006]

【課題を解決するための手段】本発明は、上述の点に鑑
みなされたもので、垂直ノコギリ波のレベルに応じたP
WM波を発生するPWM変調器と、該PWM変調器の出
力信号が印加されるウインドーコンパレータと、該ウイ
ンドーコンパレータの出力信号に応じて動作するプシュ
プル増幅器と、該プシュプル増幅器の出力信号からキャ
リア成分を除去する積分回路と、該積分回路の出力信号
により駆動される垂直偏向コイルとを備え、前記ウイン
ドーコンパレータの出力信号に応じて前記プシュプル増
幅器に貫通電流が流れるのを防止したことを特徴とす
る。
SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and has been described in detail with reference to the drawings showing the preferred embodiments of the present invention.
A PWM modulator that generates a WM wave, a window comparator to which an output signal of the PWM modulator is applied, a push-pull amplifier that operates according to the output signal of the window comparator, and a carrier from the output signal of the push-pull amplifier An integration circuit for removing the component; and a vertical deflection coil driven by an output signal of the integration circuit, wherein a through current is prevented from flowing through the push-pull amplifier according to an output signal of the window comparator. And

【0007】[0007]

【発明の実施の形態】図1は、本発明の垂直出力回路を
示すもので、(10)は端子(11)からの水平同期信
号周波数の信号をキャリアとして端子(12)からの垂
直ノコギリ波をPWM変調し、前記垂直ノコギリ波のレ
ベルに応じたPWM波を発生するPWM変調器、(1
3)はPWM変調器(10)の出力信号が印加される第
1及び第2コンパレータ(14)(15)を備えるウイ
ンドーコンパレータ、(16)は第1コンパレータ(1
4)に基準電圧V1を、第2コンパレータ(15)に基
準電圧V2を印加する基準電圧源、(17)は第1コン
パレータ(14)の出力信号に応じて駆動される第1ト
ランジスタ(18)と前記第2コンパレータ(15)の
出力信号に応じて駆動される第2トランジスタ(19)
とを含むプシュプル増幅器、(20)はプシュプル増幅
器(17)の出力信号からキャリア成分を除去する積分
回路である。
FIG. 1 shows a vertical output circuit of the present invention. (10) is a vertical sawtooth wave from a terminal (12) using a signal of a horizontal synchronizing signal frequency from a terminal (11) as a carrier. A PWM modulator that PWM-modulates (1) and generates a PWM wave corresponding to the level of the vertical sawtooth wave.
3) is a window comparator including first and second comparators (14) and (15) to which an output signal of the PWM modulator (10) is applied, and (16) is a first comparator (1).
4) a reference voltage source for applying the reference voltage V1 to the second comparator (15), and (17) a first transistor (18) driven in accordance with an output signal of the first comparator (14). And a second transistor (19) driven according to an output signal of the second comparator (15).
And (20) is an integrating circuit for removing a carrier component from the output signal of the push-pull amplifier (17).

【0008】図1において、図2と同一の部品について
は同一の符号を付し、説明を省略する。本発明では消費
電力を低下させるために、垂直偏向コイルをドライブす
るプシュプル増幅器をD級動作させる。D級動作させる
ために本発明では、垂直ノコギリ波をPWM変調器(1
0)によりパルス信号に変換し、プシュプル増幅器に印
加している。しかし、図2に示されるようなB級増幅回
路構成のままD級動作を行わせると、プシュプル増幅器
を構成する2つのトランジスタが同時にオン(貫通電流
が発生)する際に多大なパワー損失を発生させたり、時
にはトランジスタの破壊までに至ってしまう。
In FIG. 1, the same components as those in FIG. 2 are denoted by the same reference numerals, and the description will be omitted. In the present invention, a push-pull amplifier that drives a vertical deflection coil is operated in class D in order to reduce power consumption. According to the present invention, a vertical sawtooth wave is converted to a PWM modulator (1) for class D operation.
0) is converted to a pulse signal and applied to the push-pull amplifier. However, if the class D operation is performed with the class B amplifier circuit configuration as shown in FIG. 2, a large power loss occurs when the two transistors constituting the push-pull amplifier are turned on simultaneously (through current is generated). And sometimes even the breakdown of the transistor.

【0009】そこで、本発明では、前記2つのトランジ
スタが同時にオンしないように、トランジスタのオンオ
フが反転する際に前記2つのトランジスタを共に一旦オ
フさせてからオンさせている。これにより、前記2つの
トランジスタに貫通電流が流れることがなくなる。端子
(12)には垂直同期信号に基づいて作られた垂直ノコ
ギリ波が印加される。該ノコギリ波は、PWM変調され
パルス信号となりウインドーコンパレータ(13)に印
加される。ウインドーコンパレータ(13)を構成する
第1及び第2コンパレータ(14)(15)は、それぞ
れ2つの入力信号のレベル比較を行い、その比較結果を
「H」「L」として第1トランジスタ(18)と第2ト
ランジスタ(19)に印加する。
Therefore, in the present invention, when the on / off of the transistors is reversed, the two transistors are once turned off and then turned on so that the two transistors are not turned on at the same time. Thus, a through current does not flow through the two transistors. A vertical sawtooth wave generated based on the vertical synchronization signal is applied to the terminal (12). The sawtooth wave is PWM-modulated and becomes a pulse signal, which is applied to the window comparator (13). The first and second comparators (14) and (15) constituting the window comparator (13) compare the levels of two input signals, and determine the comparison result as "H" and "L", and set the first transistor (18 ) And the second transistor (19).

【0010】その様子を図3に示す。今、図3(a)に
実線で示す垂直ノコギリ波が発生しており、第1コンパ
レータ(14)の基準電圧V1と、第2コンパレータ
(15)の基準電圧V2とが点線のレベルであったとす
る。そして、今時刻t1以前であり、垂直ノコギリ波の
レベルがV1及びV2より低かったとする。すると、第
1コンパレータ(14)が「L」レベル、第2コンパレ
ータ(15)が「H」レベルを発生し第1トランジスタ
(18)がオフ、第2トランジスタ(19)がオンす
る。第2トランジスタ(19)がオンすると、垂直偏向
コイル(7)から電流が第2トランジスタ(19)のコ
レクタに流れる。
FIG. 3 shows this state. Now, it is assumed that a vertical sawtooth wave indicated by a solid line in FIG. 3A is generated, and the reference voltage V1 of the first comparator (14) and the reference voltage V2 of the second comparator (15) are at the levels indicated by the dotted lines. I do. Assume that the time is before time t1 and the level of the vertical sawtooth wave is lower than V1 and V2. Then, the first comparator (14) generates an “L” level and the second comparator (15) generates an “H” level, turning off the first transistor (18) and turning on the second transistor (19). When the second transistor (19) is turned on, current flows from the vertical deflection coil (7) to the collector of the second transistor (19).

【0011】次に、時刻t1から時刻t2の間となり、
垂直ノコギリ波のレベルがV1とV2の間になったとす
ると、第1コンパレータ(14)が「L」レベル、第2
コンパレータ(15)が「L」レベルを発生し第1トラ
ンジスタ(18)がオフ、第2トランジスタ(19)が
オフする。このため、第2トランジスタ(19)がオフ
し、第1トランジスタ(18)がオンし始める切り替わ
りタイミングの中間において、両トランジスタがオフす
る状態が設定されることとなる。これにより貫通電流の
発生が防止でき、パワー損失や破壊が防止できる。
Next, between time t1 and time t2,
Assuming that the level of the vertical sawtooth wave is between V1 and V2, the first comparator (14) sets the “L” level,
The comparator (15) generates an "L" level, the first transistor (18) turns off, and the second transistor (19) turns off. For this reason, the state where both transistors are turned off is set in the middle of the switching timing when the second transistor (19) turns off and the first transistor (18) starts to turn on. Thereby, generation of a through current can be prevented, and power loss and destruction can be prevented.

【0012】次に、時刻t2から時刻t3の間となり、
垂直ノコギリ波のレベルがV1以上となったとすると、
第1コンパレータ(14)が「H」レベル、第2コンパ
レータ(15)が「L」レベルを発生し第1トランジス
タ(18)がオン、第2トランジスタ(19)がオフす
る。このため、第1トランジスタ(18)のエミッタか
ら垂直偏向コイル(7)に電流が流れる。
Next, between time t2 and time t3,
If the level of the vertical sawtooth wave is V1 or higher,
The first comparator (14) generates an "H" level and the second comparator (15) generates an "L" level, turning on the first transistor (18) and turning off the second transistor (19). Therefore, current flows from the emitter of the first transistor (18) to the vertical deflection coil (7).

【0013】更に、時刻t3から時刻t4の間となる
と、この場合は時刻t2から時刻t3の間と同じ状態に
ウインドーコンパレータ(13)がなる。図3(b)の
斜線部分は、第1トランジスタ(18)がオンしている
期間を示しており、図3(c)の斜線部分は、第2トラ
ンジスタ(19)がオンしている期間を示している。
Further, when the time period is between time t3 and time t4, in this case, the window comparator (13) is in the same state as between time t2 and time t3. The shaded portion in FIG. 3B indicates a period in which the first transistor (18) is on, and the shaded portion in FIG. 3C indicates a period in which the second transistor (19) is on. Is shown.

【0014】積分回路(20)は、プシュプル増幅器
(17)からのPWM信号中に含まれるキャリア成分を
除去するのに配置されている。積分回路(20)は、コ
イルとコンデンサで構成されているが、積分作用を呈す
るものならどのようなものでもよい。又、ダイオード
(21)(22)は、第1トランジスタ(18)と第2
トランジスタ(19)がオフ時、積分回路(20)に連
続電流を流すためのフライホイールダイオードである。
The integration circuit (20) is arranged to remove a carrier component contained in the PWM signal from the push-pull amplifier (17). The integrating circuit (20) is composed of a coil and a capacitor, but may be of any type that exhibits an integrating action. The diodes (21) and (22) are connected to the first transistor (18) and the second transistor (18).
When the transistor (19) is off, it is a flywheel diode for allowing a continuous current to flow through the integration circuit (20).

【0015】[0015]

【発明の効果】以上述べた如く、本発明によれば、プシ
ュプル増幅器をD級動作させているので、消費電力の低
減が計れる。特に本発明によれば、プシュプル増幅器を
D級動作させる際に、プシュプル増幅器に貫通電流が流
れないようにトランジスタをオフしているので、パワー
損失や破壊が防止できる。
As described above, according to the present invention, since the push-pull amplifier is operated in class D, the power consumption can be reduced. In particular, according to the present invention, when the push-pull amplifier is operated in class D, the transistor is turned off so that a through current does not flow through the push-pull amplifier, so that power loss and destruction can be prevented.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の垂直出力回路を示す回路図である。FIG. 1 is a circuit diagram showing a vertical output circuit of the present invention.

【図2】従来の垂直出力回路を示す回路図である。FIG. 2 is a circuit diagram showing a conventional vertical output circuit.

【図3】図1の説明に供するための波形図である。FIG. 3 is a waveform diagram for explaining FIG. 1;

【符号の説明】[Explanation of symbols]

(10) PWM変調器 (13) ウインドーコンパレータ (17) プシュプル増幅器 (20) 積分回路 (10) PWM modulator (13) Window comparator (17) Push-pull amplifier (20) Integration circuit

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 垂直ノコギリ波のレベルに応じたPWM
波を発生するPWM変調器と、 該PWM変調器の出力信号が印加されるウインドーコン
パレータと、 該ウインドーコンパレータの出力信号に応じてD級動作
するプシュプル増幅器と、 該プシュプル増幅器の出力信号からキャリア成分を除去
する積分回路と、 該積分回路の出力信号により駆動される垂直偏向コイル
とを備え、前記ウインドーコンパレータの出力信号に応
じて前記プシュプル増幅器に貫通電流が流れるのを防止
したことを特徴とする垂直出力回路。
1. A PWM according to a level of a vertical sawtooth wave.
A PWM modulator that generates a wave, a window comparator to which an output signal of the PWM modulator is applied, a push-pull amplifier that operates in class D according to an output signal of the window comparator, and an output signal of the push-pull amplifier An integration circuit for removing a carrier component; and a vertical deflection coil driven by an output signal of the integration circuit, wherein a through current is prevented from flowing through the push-pull amplifier in accordance with an output signal of the window comparator. Characteristic vertical output circuit.
【請求項2】 垂直ノコギリ波のレベルに応じたPWM
波を発生するPWM変調器と、 該PWM変調器の出力信号が印加される第1及び第2コ
ンパレータを備えるウインドーコンパレータと、 前記第1コンパレータの出力信号に応じて駆動される第
1トランジスタと前記第2コンパレータの出力信号に応
じて駆動される第2トランジスタとを含むプシュプル増
幅器と、 該プシュプル増幅器の出力信号からキャリア成分を除去
する積分回路と、 該積分回路の出力信号により駆動される垂直偏向コイル
とを備え、前記第1及び第2コンパレータの出力信号に
応じて前記第1及び第2トランジスタに貫通電流が流れ
るのを防止したことを特徴とする垂直出力回路。
2. PWM according to the level of a vertical sawtooth wave
A PWM modulator for generating a wave; a window comparator including first and second comparators to which an output signal of the PWM modulator is applied; a first transistor driven according to an output signal of the first comparator; A push-pull amplifier including a second transistor driven in accordance with an output signal of the second comparator; an integration circuit for removing a carrier component from the output signal of the push-pull amplifier; and a vertical driver driven by the output signal of the integration circuit. A vertical output circuit, comprising: a deflection coil, wherein a through current is prevented from flowing through the first and second transistors according to output signals of the first and second comparators.
【請求項3】前記積分回路はチョークコイルとコンデン
サを含むことを特徴とする請求項1記載の垂直出力回
路。
3. The vertical output circuit according to claim 1, wherein said integration circuit includes a choke coil and a capacitor.
JP32036096A 1996-11-29 1996-11-29 Vertical output circuit Expired - Fee Related JP3439055B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP32036096A JP3439055B2 (en) 1996-11-29 1996-11-29 Vertical output circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP32036096A JP3439055B2 (en) 1996-11-29 1996-11-29 Vertical output circuit

Publications (2)

Publication Number Publication Date
JPH10164385A true JPH10164385A (en) 1998-06-19
JP3439055B2 JP3439055B2 (en) 2003-08-25

Family

ID=18120614

Family Applications (1)

Application Number Title Priority Date Filing Date
JP32036096A Expired - Fee Related JP3439055B2 (en) 1996-11-29 1996-11-29 Vertical output circuit

Country Status (1)

Country Link
JP (1) JP3439055B2 (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1022855A1 (en) * 1999-01-22 2000-07-26 STMicroelectronics SA Control device and method for a vertical deflection circuit of a spot scanning a screen, in particular for television or computer monitor
FR2788920A1 (en) * 1999-01-22 2000-07-28 St Microelectronics Sa Control method for vertical deflection screen sweep circuit, involves using output amplifier stage, principal and auxiliary voltage supplies, and two bidirectional interrupters
KR100465321B1 (en) * 2002-05-02 2005-01-13 삼성전자주식회사 Apparatus capable of correcting for misconvergence using the D class amplifier
KR100465163B1 (en) * 2002-07-15 2005-01-13 삼성전자주식회사 Apparatus for compansation convergence with low switching delay
CN105450211A (en) * 2014-06-05 2016-03-30 无锡华润矽科微电子有限公司 Signal detection circuit

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1022855A1 (en) * 1999-01-22 2000-07-26 STMicroelectronics SA Control device and method for a vertical deflection circuit of a spot scanning a screen, in particular for television or computer monitor
FR2788921A1 (en) * 1999-01-22 2000-07-28 St Microelectronics Sa METHOD AND DEVICE FOR CONTROLLING A VERTICAL DEVIATION CIRCUIT OF A SPOT SCANNING A SCREEN, PARTICULARLY FOR A TELEVISION OR COMPUTER MONITOR
FR2788920A1 (en) * 1999-01-22 2000-07-28 St Microelectronics Sa Control method for vertical deflection screen sweep circuit, involves using output amplifier stage, principal and auxiliary voltage supplies, and two bidirectional interrupters
KR100465321B1 (en) * 2002-05-02 2005-01-13 삼성전자주식회사 Apparatus capable of correcting for misconvergence using the D class amplifier
KR100465163B1 (en) * 2002-07-15 2005-01-13 삼성전자주식회사 Apparatus for compansation convergence with low switching delay
US6853157B2 (en) * 2002-07-15 2005-02-08 Samsung Electronics Co., Ltd. Image distortion compensating apparatus with low switching delay
CN105450211A (en) * 2014-06-05 2016-03-30 无锡华润矽科微电子有限公司 Signal detection circuit

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