JPH10163868A - Frequency synthesizer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make a step size small without being influenced by oscillation frequency fluctuation and also to make a noise characteristic satisfactory. SOLUTION: An analog PLL(phase-locked loop) circuit 8 and a digital PLL circuit 19 are provided so that a voltage controlled oscillator 1 may be common for them, gain of the circuit 19 is made high at the time of switching a frequency setting signals, also a cutoff frequency of the loop filter 18 is made high. Gain of the circuit 19 is made low after switching the frequency setting signals and also a cutoff frequency of the filter 18 is made high.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for minimizing a step size of a lock frequency of a frequency synthesizer and reducing noise.

[0002]

2. Description of the Related Art Analog frequency synthesizers
An offset voltage addition type is known. FIG. 3 shows the configuration. This means that a voltage corresponding to a frequency band near which a PLL (Phase Locked Loop) circuit can be locked is converted to a DAC (Digital / Analog / Analog).
A converter 51 is used to generate an offset voltage Vof, and the oscillation frequency of a VCO (voltage controlled oscillator) 52 is moved near a frequency to be set, that is, within a lockable frequency range. . The application of the offset voltage Vof is performed in the operational amplifier 531 of the active loop filter 53.

A condition for locking the PLL circuit is one of N times (integer multiple) of the input reference frequency Fr, and VC
It is within the oscillation frequency range of O52. The SPD (sampling phase detector) 54 has a function of multiplying the reference frequency Fr by N and a phase comparison function. Reference numerals 55 and 56 denote buffers, reference numeral 57 denotes an input terminal for a signal having a reference frequency Fr, and reference numeral 58 denotes an output terminal for a lock frequency signal.

For example, when the oscillation frequency range of the VCO 52 is 1
GHz to 2 GHz, and the control voltage range is 0 V to 10 V
In the case where the reference frequency Fr is 100 MHz, by selecting the offset voltage Vof applied from the DAC 51, 1 GHz, 1.1 GHz, 1.2 GHz
.., 1.9 GHz, 2.0 GHz, etc.
L can be locked.

That is, the frequency setting data Dc is
51, the VCO 52 has the aforementioned 100
When a voltage corresponding to the oscillation frequency divided in MHz steps is added from the DAC 51 to the operational amplifier 53, the PLL is locked corresponding to the voltage and the locked frequency is obtained.

Therefore, it is possible to manufacture a frequency synthesizer that generates a frequency signal divided in steps of the reference frequency Fr in a frequency range of 1 GHz to 2 GHz. Frequency setting data D applied to the DAC 51
By inputting data in consideration of the temperature characteristics of the VCO 52 into c, a more stable frequency synthesizer can be obtained.

[0007]

However, the VCO
The oscillation frequency characteristic of the reference voltage 52 varies as shown in FIG. 4 depending on the temperature. Therefore, if the step size is reduced, even if the offset voltage Vof is the same, the frequency is locked to a different frequency if the temperature is different.

That is, in this method, the step size is V
This can be realized only when the oscillation frequency fluctuation value due to the temperature of the CO 52 is larger, and there is a problem that the step size cannot be made smaller than the oscillation frequency fluctuation value.

An object of the present invention is to solve such a problem and to provide a frequency synthesizer in which the step size can be made smaller than the oscillation frequency fluctuation value and the noise characteristics are good.

[0010]

According to a first aspect of the present invention, there is provided a voltage controlled oscillator, a sampling phase detector for comparing the phase of an output signal of the voltage controlled oscillator with a frequency signal of an integral multiple of a reference frequency signal, and a sampling phase detector. The first loop filter that removes a high-frequency component from an output signal of a phase detector and inputs the same to the voltage-controlled oscillator;
An analog PLL circuit that locks to one of integer multiples of the reference frequency signal; and a programmable circuit that sets a frequency division ratio according to a frequency setting signal corresponding to one of integer multiples of the reference frequency signal. A frequency divider, a phase comparator that compares the phase of the output signal of the programmable frequency divider with the reference frequency signal, and a second loop filter that removes a high-frequency component from the output signal of the phase comparator. A digital PLL circuit configured to add an output signal of the second loop filter to an input signal to the voltage controlled oscillator and to input an output signal of the voltage controlled oscillator to the programmable frequency divider; By locking the digital PLL circuit when the setting signal is switched, the analog PLL circuit is locked to the same frequency. It is allowed to configure the digital PLL circuit after the switching of the frequency setting signal to substantially decouple.

According to a second aspect, in the first aspect, the gain of the second loop filter is set to be high for a predetermined time after the unlock signal is output from the phase comparator.

In a third aspect based on the second aspect, the cutoff frequency of the second loop filter is set high for a predetermined time after the unlock signal is output from the phase comparator. .

[0013]

FIG. 1 is a diagram showing one embodiment of the present invention. Reference numeral 1 denotes a VCO, which is an analog PL from a buffer amplifier 2, a loop filter 3, a preamplifier 4, an SPD 5, a buffer amplifier 6, and a signal separation circuit 7.
An L circuit 8 is formed. 9 is an input terminal for the reference frequency signal Fr, 10 is a driver buffer, 11 is an output buffer, and 12 is an output terminal.

Reference numeral 13 denotes a prefix variable frequency divider, 14 denotes a synthesizer IC (integrated circuit), 15 denotes a frequency setting terminal 16
Is a ROM (read only memory) that retrieves data from a table set in advance based on the frequency setting signal applied to the IC and supplies the data to the synthesizer IC 14. 17
Is a timer circuit that outputs an output signal only until a predetermined time elapses after the input of the unlock signal output from the synthesizer IC 14. 18 is a loop filter. The above VCO 1, buffer amplifier 2, loop filters 3, 18, synthesizer IC 14, timer circuit 1
7. Digital P by pre-variable frequency divider 13 and ROM 15
An LL circuit 19 is formed.

The preamplifier 4 comprises an amplifier 41 and a resistor R1, and the loop filter 3 comprises an operational amplifier 3
1, a resistor R2 and a capacitor C1, and a signal separating circuit 7
Is composed of resistors R3 to R5. The output signal of the loop filter 18 is applied to the operational amplifier 31 of the loop filter 3.

The above-mentioned synthesizer IC 14 comprises:
A frequency divider 1 that inputs data from the ROM 15 and sets its own frequency division ratio, and also sets the frequency division ratio of the preceding variable frequency divider 13
41, 142, reference frequency signal F input to input terminal 9
a frequency divider 143 for fixedly dividing r and a frequency divider 142;
Phase detector 14 for comparing the phase of the output frequency signal at 143
4. The frequency dividers 13, 141, 142 constitute a program frequency divider.

The loop filter 18 includes an amplifier 18
1, analog switches 182 and 183, resistors R6 to R1
0, capacitors C2 and C3, and transistor Q1. When the output of the timer circuit 17 is output, the transistor Q1 is turned on, and the analog switches 182 and 183 are switched to the illustrated contacts, where a large gain is set. When the cutoff frequency is set high while the output of the timer circuit 17 is not output, the above situation is reversed, the gain is set to a small value, and the cutoff frequency is set to a low frequency. .

Next, the operation will be described. When the frequency setting signal input to the terminal 16 is switched, the frequency dividers 13, 141, 142 are set to the frequency division ratio corresponding to the signal after the switching, and the phase detector 144 as shown in FIG.
Momentarily, an unlock signal is output, and a signal of a predetermined time width is output from the timer circuit 17. As a result, filter 1
8 is set to a high gain and the cutoff frequency is set to a high value as described above, and the digital PLL circuit 19 is strongly pulled into a frequency corresponding to the frequency setting signal input to the terminal 16, and the PLL circuit 19 Lock to frequency.

At this time, if the lock frequency is determined in advance so as to be any one of N times the reference frequency Fr of the analog PLL circuit 8, that is, if the frequency setting signal is determined in advance as such, The analog PLL circuit 8 is also locked at that frequency. Therefore, if the reference frequency Fr is set to a low frequency (for example, 1
0 MHz), the two PLL circuits 8 and 19 can be locked to the frequency divided by the step size of that frequency.

Thereafter, when the signal output from the timer circuit 17 stops, the gain of the loop filter 18 decreases, and the digital PLL circuit 19 is substantially disconnected from the VCO 1, and The cutoff frequency is switched to a lower frequency to reduce the influence of noise.

As described above, in this embodiment, the digital PLL circuit 19 pulls in and locks the target frequency.
The frequency locked state is reflected on the analog PLL circuit 8, the analog PLL circuit 8 is also locked at the same frequency, and thereafter, the digital PLL circuit 19 is substantially disconnected.

In general, a synthesizer of a digital PLL circuit is basically used by increasing the frequency division ratio, that is, by reducing the step size. In this case, the noise characteristics deteriorate as the frequency division ratio increases. Assuming that the dividing ratio is S, the noise amount is determined by 20 logS. On the other hand, in the synthesizer of the analog PLL circuit, the step size becomes large instead of making the multiplication number N small.

This example takes advantage of both of these characteristics, and uses a digital PLL circuit only when the frequency is set to enable the frequency (Fr.
Then, the digital PLL circuit is substantially separated from the voltage-controlled oscillator 1 to reduce noise. In this way, even if the step size in the analog PLL circuit is reduced, the temperature characteristics of the voltage controlled oscillator 1 are not affected.

[0024]

As described above, according to the frequency synthesizer of the present invention, the step size can be made smaller than the oscillation frequency fluctuation value, and the noise characteristics are also improved.

[Brief description of the drawings]

FIG. 1 is a functional block diagram showing an embodiment of a frequency synthesizer of the present invention.

FIG. 2 is a time chart for explaining the frequency synthesizer of FIG. 1;

FIG. 3 is a functional block diagram of a conventional frequency synthesizer.

FIG. 4 is a characteristic diagram of a voltage controlled oscillator.

[Explanation of symbols]

1: VCO (voltage controlled oscillator), 2: buffer, 3: loop filter, 4: preamplifier, 5: SPD (sampling phase detector), 6: buffer, 7: signal separation circuit, 8: analog PLL circuit , 9: reference frequency signal input terminal, 10: driver buffer, 11: output buffer, 12: output terminal, 13: variable frequency divider, 14: synthesizer IC, 15: ROM (read only memory), 16 : Frequency setting terminal, 17: timer circuit, 1
8: Loop filter, 19: Digital PLL circuit.

Claims (3)

[Claims] 1. A voltage controlled oscillator, a sampling phase detector for comparing phases of an output signal of the voltage controlled oscillator and a frequency signal having an integral multiple of the frequency of a reference frequency signal,
An analog PLL that includes the first loop filter that removes a high-frequency component from an output signal of the sampling phase detector and inputs the signal to the voltage-controlled oscillator, and locks to any one of integer multiples of the reference frequency signal Circuit, a programmable frequency divider for setting a frequency division ratio according to a frequency setting signal corresponding to any one of integer multiples of the frequency of the reference frequency signal, an output signal of the programmable frequency divider, and the reference frequency signal And a second loop filter for removing a high-frequency component from an output signal of the phase comparator. An output signal of the second loop filter is input to the voltage-controlled oscillator. And a digital PL configured to input the output signal of the voltage controlled oscillator to the programmable frequency divider.
An L circuit, wherein the digital PLL is used when the frequency setting signal is switched.
A frequency synthesizer wherein the analog PLL circuit is locked to the same frequency by locking a circuit, and the digital PLL circuit is substantially disconnected after switching the frequency setting signal. 2. The frequency synthesizer according to claim 1, wherein the gain of the second loop filter is set high for a predetermined time after the output of the unlock signal from the phase comparator. 3. The frequency synthesizer according to claim 2, wherein a cutoff frequency of said second loop filter is set high for a predetermined time after an unlock signal is output from said phase comparator.