JPH10163857A - Superconducting integrated circuit and its driving method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To unnecessitate the generation of two-phase pulsating flow power current that has overlaps in the same pulsating flow power, then, to reduce a current amount to flow to a current clamper and to suppress wasteful power consumption extremely about the operation of a superconductive integrated circuit. SOLUTION: One of 1st phase and 2nd phase pulsating flow power current P1 and P2 whose phases are different by 180 deg. is supplied to a combining logic circuit 21 that is a preceding stage of a latch circuit 11, and the other is supplied to a combining logic circuit 21 that is a subsequent stage of the circuit 11. Pulsating flow power current P1' or P2' whose phase rises earlier than the current P1 or P2 that is supplied to the circuit 21 of the subsequent stage is supplied to the circuit 11. A delay circuit 12 is provided between the circuit 11 and the circuit 21 of the subsequent stage. A latch output of the circuit 11 is controlled to reach a combining logic circuit of a corresponding subsequent stage after the pulsating flow power current is supplied to the circuit 21 of the subsequent stage by adjusting a signal propagation delay time of the circuit 12.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a superconducting integrated circuit including a combinational logic circuit and a latch circuit using a Josephson junction element as the most basic active element, and a driving method thereof. Regarding improvement.

[0002]

2. Description of the Related Art In a superconducting integrated circuit (a so-called Josephson integrated circuit) composed of a set of direct-coupling (current injection type) superconducting gate circuits constructed using a Josephson junction element on a substrate chip, Due to the characteristics of the circuit, it is necessary to take some measures to supply the power supply current. That is, the gate circuit can normally transition between the zero voltage state and the resistance state (voltage state), but once the state transition occurs, the state is maintained in a “latching mode” unless the power is turned off. Operate.

Therefore, in order to make such a gate circuit repeat its operation with time, the power supply current waveform must be set to a unipolar pulsating waveform in principle so that the gate circuit can be reset at a predetermined cycle. The frequency of the pulsating power supply current is set to a considerably high frequency of, for example, 1 GHz or more so as not to impair the essential high-speed operability of the gate circuit. Further, when a combinational logic circuit of a unit for performing a predetermined logical operation is formed by using one or a plurality of gate circuits, the combinational logic circuit also naturally operates in the latching mode. In order to transfer the current to the combinational logic circuit of the next stage, the next stage of the combinational logic circuit has a pulse having a predetermined phase difference, generally 180 °, with respect to the pulsating power supply current supplied to the preceding stage of the combinational logic circuit. Power supply current must be supplied. In addition, in the combinational logic circuit configured using this type of gate circuit, as is well known, the existence of a "dead zone" means that when the pulsating power supply current rises after an input signal is supplied first, a predetermined operation is performed. No, the pulsating power supply current must be supplied before the input signal arrives.

[0004] First, even if the rising phase difference is 180 ° as described above, the pulsating power supply currents of the first and second phases overlap each other as described later with reference to FIG. It is made to have the wrapping part To. Rather, the supply of the pulsating power supply current to the preceding combinational logic circuit stops (falling timing) and the supply of the pulsating power supply current to the subsequent combinational logic circuit (rising timing) occurs simultaneously. In this case, no operation margin can be expected, and if the timing of signal propagation is slightly deviated, the logical operation result may be lost.

However, if there is an overlap portion where both the first-phase and second-phase pulsating power supply currents are on, in other words, this is driven by these first-phase pulsating power supply currents. This means that the combinational logic circuit group and the combinational logic circuit group driven by the second-phase pulsating power supply current are all in an operable state. Therefore, the so-called "punch-through phenomenon" in which interstage signals propagate in a shogi manner. The fear of causing

Therefore, in order to prevent this, between the stages of the cascade-connected combinational logic circuits, the result of the logical operation performed by the preceding combinational logic circuit is latched. Requires a latch circuit that passes only the latched signal to the subsequent combinational logic circuit without following. However, this type of latch circuit also has a special characteristic due to the direct coupling type superconducting circuit configuration. When it comes to the relationship between the input signal and the application timing of the pulsating power supply current, the aforementioned combinational logic circuit is Conversely, the input signal is latched at the supply timing of the pulsating power supply current only when the pulsating power supply current is supplied later while the input signal is applied.
If this relationship is reversed, the operation is still in the "dead zone", and a normal latch operation cannot be caused. This is a positive latch circuit that outputs a signal with the same logical value as the input signal,
This is a fact that the latch circuit does not change even if the type of the latch circuit changes, such as a negative latch circuit that outputs an inverted logical value signal, and a positive / negative latch circuit applicable to a so-called dual-rail system that can represent both outputs.

[0007] Of course, the above is well known to those skilled in this field, but just in case, with reference to FIG. 3, a simple operational model of a conventional superconducting integrated circuit is given. To help.

[0010] The circuit example shown in FIG. 3 has a loop configuration for explaining the basic operation, and serves as a temporary signal storage circuit. That is, there are two latch circuits 11 each having the same configuration, and one of them is denoted by A for convenience.
The other is denoted by the symbol B. Similarly, each of them may have the same configuration, or may be different from each other in order to perform a predetermined logical operation. The logic circuit 21 located downstream of the first latch circuit A is denoted by the symbol A, and the logic circuit 21 located downstream of the second latch circuit B is denoted by the symbol B. is there.

The latch circuits 11, 11 have terminals Ta, Tb, respectively.
However, the terminal Ta is a power supply terminal supplied to an amplification gate provided at an input portion of the latch circuit, and at this gate, when an input signal Si is supplied when power is supplied in advance, a predetermined value is provided. The input signal is amplified according to the current amplification factor. Generally, this kind of amplification gate is provided to increase the fan-in, and may be omitted in principle if it is limited to only performing sequential operation. Here, it is assumed that such an amplification gate is provided in accordance with the actual situation.

A power supply terminal Tb provided at the subsequent stage of the latch circuit 11 is a power supply terminal involved in the latch operation, and is a state in which the input signal Si amplified from the previous amplification gate has arrived first. Only when a current is supplied to the power supply terminal Tb, the input signal Si amplified at the current supply timing is latched. However, as for the output of the output signal So, as is generally well known, in order to increase the fan-out and to provide the latch circuit itself with a predetermined operation delay time, an appropriate value such as, for example, about three stages is used. Since a number of stages of amplification gates are provided, the operation is slightly delayed from the latch operation.

A power supply terminal Tc provided in the logic circuit 21
Is a terminal for supplying a power supply current necessary for the logic circuit to perform a predetermined logic operation.As is well known, in such a logic circuit, a power supply current is first supplied to the power supply terminal Tc. Unless an output signal So (input signal as viewed from a logic circuit) is received from the latch circuit, a predetermined logic operation cannot be performed.

In the case shown in the drawing, as shown in the center of the drawing, a symbol P1 is assigned to one of the two-phase pulsating currents, and a symbol P1 is assigned to the other.
P2 and follow them in this area of practice, simply P1
The P1 phase current and the P2 phase current are referred to as a power supply terminal Tb for causing a latch operation of the latch circuit A, a power supply terminal Tc for the logic circuit A, and a power supply terminal Ta of a pre-amplification part of the latch circuit B. On the other hand, a current is supplied, while a power supply terminal Ta of the pre-amplification part of the latch circuit A, a power supply terminal Tb for causing a latch operation of the latch circuit B to occur, and a power supply terminal of the logic circuit B
The P2 phase current is supplied to Tc.

A rising phase difference τ is given between the P1 phase current and the P2 phase current, both of which are pulsating power supply currents, and both are turned on (flowing,
(Or rising) overlap time To has occurred. However, each frequency is the same, and the rising period is also the same.

Now, as shown at time t1 in the waveform diagram, P1
In the state where only the phase current is on, the P1 phase current is supplied only to the terminal circled in FIG.
The logic circuit A can perform a predetermined logic operation, and its output is given as an input signal Si to the input of the subsequent latch circuit B with a delay from the rise of the P1 phase current. The signal Si is amplified by the above-described amplification gate provided at the input portion and is on standby.

Hereinafter, similarly, the circled code P1 or
P2 indicates that the corresponding P1 phase current or P2 phase current is on. When the P2 phase current rises next at time t2, the power supply state becomes as shown in FIG. At the rising timing t2, the latch circuit B receives the input signal Si.
(Amplified). However, as described above, since the signal propagation delay time is expected to be longer than a certain level in the latch circuit itself, even if the P2 phase current is supplied to the subsequent logic circuit B, the latch circuit output signal is still generated at the rising timing t2. Since So does not reach the input of the logic circuit B, the operation in the dead zone does not start. That is, after elapse of the signal propagation delay time expected in the latch circuit B in advance, the logic circuit B already supplied with power is
After the output So of the latch circuit B is supplied to the logic circuit B, the logic circuit B can perform a predetermined logical operation.

This state continues as long as the P2 phase current remains on even when the P1 phase current falls, as shown at time t3 and FIG. 3 (C), while the P2 phase current is supplied. During this period, power is also supplied to the above-described amplification gate provided in the input portion of the latch circuit A, and when the logic operation in the logic circuit B is completed, this is amplified as an input signal Si. However, it is possible to wait for the input of the latch unit, which is the latter part of the latch circuit A.

Here, when the P1 phase current rises again as shown at time t4, the state shown in FIG.
Can latch the amplified input signal Si, and the logic circuit A can perform a predetermined logic operation. After a predetermined signal propagation delay time in the latch circuit A, the latch circuit When the latch output So of A is received, the predetermined logical operation is started based on this.

Thereafter, when the P2 phase current falls, it returns to the initial state described above, that is, the state of FIG. 3A, and thereafter, the predetermined frequency set to the P1 phase current and the P2 phase current And the above operation is repeated. Of course, the actual superconducting integrated circuit has a much more complicated circuit configuration, and the number of internal gate stages forming the logic circuit 21 greatly differs depending on the logic operation to be achieved, but at least the preceding logic circuit 21 and its logic operation result A latch circuit 11, which latches
The sequential operation relationship between the latch circuit 11 and the subsequent logic circuit 21 that performs a predetermined logical operation in response to the output is basically as described above.

On the other hand, the first-phase and second-phase pulsating power supply currents P1 and P2 which overlap each other as described above are actually obtained by a power supply device configuration as shown in FIG.

First, a suitable substrate chip such as a semiconductor substrate
On the 31, a group of a plurality of latch circuits 11 and a group of logic circuits 21 are arranged in a predetermined pattern according to a circuit function to be realized,
A superconducting integrated circuit is constructed by being connected. Of course, in an actual circuit, these may be nested in a complicated manner, but the present invention does not show any interest in the internal structure of the superconducting integrated circuit itself. The latch circuit group described above is simply enclosed in one frame and shown as a latch circuit 11, and similarly, a group of a plurality of logic circuits 21 is simply enclosed in one frame and shown as a logic circuit 21. Furthermore, small square symbols are shown dotted around the four sides of the substrate chip, which are so-called bonding pads, and wiring and the like are not shown, but are mounted on the substrate chip through this. The connection between the superconducting integrated circuit and the external circuit is adopted.

On a chip carrier (not shown because it is well known) for supporting the substrate chip 31, or on the substrate chip 31 as shown, as a component of a high-frequency two-phase pulsating power supply, In order to obtain impedance matching between the provided high-frequency power source (not shown) and the superconducting integrated circuit mounted on the substrate chip 31, an impedance conversion transformer 32 is first mounted. Generally, the impedance as a load of a superconducting integrated circuit viewed from a high-frequency power source is quite low, and the use of such an impedance conversion transformer is almost essential. For example, the turn ratio of the primary winding to the secondary winding is 4 : 1 is selected, and the impedance ratio is 1
Equal to 6: 1. That is, the impedance conversion transformer 32 relates to impedance conversion and is used as a so-called down converter.

The primary winding of the impedance conversion transformer 32 has a midpoint terminal, which is connected to a ground plane (not shown) provided on the substrate chip 31, as indicated by a ground symbol. At both ends of the primary winding, a balanced high-frequency power source (not shown)
Alternating currents φ1 and φ2 whose phases are different from each other by 180 ° are supplied via the shield line 33, whereby current waveforms φ1s and φ2s having corresponding frequencies appear at both ends of the secondary winding.

However, the midpoint terminal of the secondary winding is not grounded as it is, but is supplied with a DC bias current Ib, and as shown in FIG. Each of the secondary output waveforms φ1s and φ2s appearing at both ends is shifted in the positive direction by that amount, and is in principle a single-phase pulsating power supply current. However, in practice, as also shown in the figure, the magnitude of the DC bias current Ib is often determined so that a current portion entering the negative region by a small amount dI remains.
This is to prevent the phase rotation from being immediately reduced to zero even when the current flowing through the Josephson junction element used in each circuit becomes zero, thereby preventing punch-through. The reason why the balanced power supply method is adopted is that the ground plane potential for establishing the ground potential of the superconducting integrated circuit is not changed. In this type of superconducting integrated circuit that handles a very small voltage, even a slight change in the ground potential or the ground plane potential may cause a serious problem. If a balanced power supply system is adopted, this fear is considerably reduced.

Voltage regulators 34, 34 are inserted in parallel with respect to the winding between each end of the secondary winding of the impedance conversion transformer 32 and the midpoint terminal.
This is generally composed of a plurality of n Josephson junctions connected in series, thereby stabilizing the voltage at both ends to a voltage nVg which is n times the gap voltage Vg of one Josephson junction. However, after all, it works as a current clamper, and as a result, the power supply currents supplied to the latch circuit 11 and the logic circuit 21 are the pulsating power supply currents P1, P2 of the first phase and the second phase, respectively.
Formatted as P2. Note that the current component dI that enters the negative region described above
Is selected within a value range smaller than the critical current value of the Josephson junction used in each of the voltage regulators 34, 34.

[0025]

However, in the above-described conventional example, only a pair of AC waveforms φ1 and φ2, which are supplied from an external high-frequency power source and are 180 ° out of phase with each other, are shaped and overlap each other. Only one set of the first and second phase pulsating power supply currents P1 and P2 having the portion To is obtained, and as described with reference to FIG.
~ Tc. However, in order to reduce the size of the impedance conversion transformer itself, for example, two or more M transformers are provided, each of which is configured to serve one of the M divided regions of the superconducting integrated circuit. However, also in this case, considering the phases, the phase relations handled by the M impedance conversion transformers are exactly the same, and the first and second phase pulsating power supply currents P1 and P2 having exactly the same waveform are used together. Output.
Therefore, such a power supply can be considered as a power supply for sequential operation after all, converging to the structure of FIG. 4 having one transformer.

As described above, when constructing a superconducting integrated circuit including a logic circuit that operates sequentially with a latch circuit interposed therebetween, as described above, the relationship between the P1 phase current and the P2 phase current in FIG. As shown, a time domain To overlap between them is required. In order to satisfy the operation margin, it is preferable that the total overlap time To × 2 of the rising edge side and the falling edge side is designed to be about 50% of the total rising time. Therefore, the current value Ic clamped by the current clamper 34 is, as also shown in FIG. 4, the peak-to-peak value (so-called pp value) Ia of the current appearing on the secondary side of the impedance conversion transformer. Must be reduced to about one part (Ic ≒ Ia / 3).

This is one of the major problems in the conventional pulsating power supply. In other words, in other words, in the output pulsating power supply current waveforms φ1s and φ2s appearing on the secondary side output of the impedance conversion transformer, the clamp current value
Since the two-thirds amplitude portion above Ic is absorbed by the voltage regulator (current clamper) 34, it can be said that it is a useless current component that is not involved in the operation of the superconducting integrated circuit at all.

The present invention has been made in view of this point.
By reducing the amount of current absorbed by the current clamper, the power supply is made more efficient or smaller.

[0029]

According to the present invention, in order to achieve the above object, the first-phase and second-phase pulsating power supply currents P1 and P2 for driving the above-described logic circuit are supplied from a first two-phase pulsating power supply. If it is the first set of two-phase pulsating power source current to be supplied, prepare a second two-phase pulsating power source that outputs the second set of two-phase pulsating power source currents P1 'and P2' separately And this second set of two-phase pulsating power supply current
The latch circuit is driven by the second pair of pulsating power supply currents so that P1 'and P2' have a phase difference with respect to the first pair of two-phase pulsating power supply currents P1 and P2. Then, between the latch circuit and the logic circuit at the subsequent stage, it is configured using a Josephson junction element, and is provided between the first set of two-phase pulsating power supply currents and the second set of two-phase pulsating power supply currents. A delay circuit for delaying a latch output from the latch circuit according to a predetermined phase difference is provided.

Thus, the phase difference between the first set of first and second phase pulsating power supply currents P1 and P2 supplied from the first two-phase pulsating power supply, and the second two-phase pulsating power supply The phase difference between the first and second phase pulsating power supply currents P1 'and P2' of the second set supplied from the P1 'and P2' may be simply set to 180 °, and those P1 and P2 and P1 'and P2' There is no need to create overlapping parts between each other. Therefore, even if each pulsating power supply current has a portion that slightly enters the negative region, the first and second two-phase pulsating power sources each have a peak-to-peak AC current waveform supplied from an external high-frequency power source. The current can be clamped at approximately half the value, and the amount of current flowing through the current clamper can be considerably reduced as compared with the conventional case.

Further, according to the present invention, the above-described delay circuit not only delays signal propagation (although it may be so), but the circuit itself has some predetermined logical operation function. It may be a single-stage or combinational logic circuit. The signal propagation delay time in this delay circuit can be set as the total signal propagation delay time of each logic gate by determining the number of a plurality of serial logic gates constituting the delay circuit.

Further, from a method perspective, the present invention provides a logic circuit provided in the preceding stage of the latch circuit in which the first-phase and second-phase pulsating power supply currents whose phases are different from each other by 180 °. And a pulsating power supply having a phase that rises earlier than a pulsating power supply current supplied to the subsequent logic circuit to the latch circuit. A current is supplied, and a delay circuit configured using a Josephson junction element is provided between the latch circuit and the subsequent logic circuit, and a signal propagation delay time of the delay circuit is adjusted, and the delay circuit is provided to the subsequent logic circuit. A method for driving a superconducting integrated circuit, characterized in that a latch output of a latch circuit reaches a logic circuit at a subsequent stage after supply of a supplied pulsating power supply current, is proposed.

[0033]

FIG. 1 shows a preferred embodiment of a superconducting integrated circuit constructed according to the present invention. The circuit configuration is similar to the circuit configuration shown in FIG. 3 for convenience in comparison with the conventional example, and is a circuit example for temporarily storing signals in a loop configuration. . Characteristic features of the present invention are that the supply form of the pulsating power supply current substantially as shown in FIG. 2F and the latch output So output from the latch circuit 11 are further intentionally delayed by a necessary time. There is a delay circuit 12 that causes the delay.

First, looking at the pulsating power supply current to be supplied to the superconducting integrated circuit shown in the figure, according to the present invention, the first two-phase pulsating power supply (not shown in the figure) supplied from the first two-phase pulsating power supply. A pair of two-phase pulsating power supply currents P1 and P2 and a second two-phase pulsating power supply (also not shown in the drawing) provided separately from the first two-phase pulsating power supply Two sets of two-phase pulsating power supply current P
1 'and P2' are used. In the following, as in the description of the prior art, the first set of two-phase pulsating power supply currents P1 and P2 are simply referred to as P1 phase current, P2 phase current, and the second set of two-phase pulsating power supply currents P1 'and P2, respectively. 'Are simply called P1' phase current and P2 'phase current, respectively. However, in the present invention, the P1 phase current and the P1 'phase current, and
A predetermined phase difference τ is set between the P2 phase current and the P2 ′ phase current.
The P1'-phase current and the P2'-phase current may have a phase relationship of exactly 180 ° and have a waveform relationship with no overlapping portion (a slight overlap is acceptable). Such features result in higher efficiency and smaller size of the power supply, as described later.

The output So of the latch circuit 11, which may have the same configuration as that shown in FIG. 3, is supplied to a delay circuit 12 added according to the present invention, and the latch output So delayed through this circuit 12 is output. It is provided to the input of a combinational logic circuit (hereinafter simply referred to as “logic circuit”) 21 in the subsequent stage. A power supply terminal Td for supplying a pulsating power supply current for newly driving the circuit is added to the delay circuit 12, but the other terminals Ta to Tc are those in the conventional example described with reference to FIG. Corresponding to Therefore, also in this embodiment, it is assumed that an amplification gate, which is not necessary in principle, but is often provided, is provided in the input section of the latch circuit 11.

Now, this also corresponds to the description of the prior art example, and one of the two latch circuits 11 has a symbol A
And a delay circuit 12 and a logic circuit 21 connected to the latter stage of each of the latch circuits, respectively.
B, first, in the present invention, one of the P1 phase current and the P2 phase current is supplied to the logic circuits A and B and the preceding signal amplification portion (amplification gate) of the latch circuits A and B. , B and one of the P1'-phase current and the P2'-phase current shaped from another power source are supplied to the power supply terminal of the part involved in the latch operation and the subsequent delay circuits A and B.

In the following, description will be given while following the sequential operation.
As shown at time t1 in FIG. 1 (F), the P1 phase current in the first set of two-phase pulsating power supply currents P1 and P2 is on, and the second set of two-phase pulsating power supply current When it has been a while since the P1 'phase current in P1' and P2 'has risen, as shown in FIG. 1A, power is supplied to the logic circuit A, and the logic circuit A Perform a predetermined logical operation.
The input terminals of other input variables for each of the logic circuits A and B have been omitted from the drawings so far. In addition, the rising edge of the P1 'phase current functions effectively as described later, and then the delay circuit A supplies the latch output So of the latch circuit A to the logic circuit A with a predetermined delay time. Therefore, after the logic circuit A can start a predetermined logical operation after the rise, the power supply current is a power supply current that does not need to be considered.

When the logic circuit A completes a predetermined logic operation,
This logical operation result signal is supplied as an input signal Si of the latch circuit B to an amplification gate provided at the input portion thereof, and this gate is already supplied with a first set of P1 phase currents via a terminal Ta. Therefore, the signal is amplified and made to wait for the input of the subsequent latch unit.

Next, at time t2, when the P1 'phase current, which has been on, falls in the second set of two-phase pulsating power supply currents, the state shown in FIG. The P2'-phase current, which may rise almost simultaneously with the fall of the P1'-phase current and belongs to the same second set of two-phase pulsating power supply currents, rises, which is the power supply terminal at which the latch operation of the second latch circuit B should occur. Input signal (logic operation result signal of logic circuit A) Si that has already been amplified and is on standby because it is supplied to Tb.
Are latched at this point. Further, the delay circuit B is also in an operable state, and the second set of P
The operation of delaying and outputting the latch output So with respect to the input signal applied after the signal propagation delay time of the latch circuit B itself has elapsed while the 2′-phase current is being supplied is started.

Then, while the delay circuit B has not yet output the latch output So, as shown at time t3 in FIG. 1 (F), the delay circuit B generates the first set of two-phase pulsating current according to the predetermined phase difference τ. Belong
When the P2 phase current rises, the state is as shown in FIG. 1C, and the power is supplied in advance from the latch circuit B to the logic circuit B connected to the subsequent stage via the delay circuit B. Therefore, after this time, when the delay circuit B outputs the latch output So, the logic circuit B that has received the latch output So can start a predetermined logical operation using the latch output So as an input variable. As can be seen from this, the delay circuit 12 is located between the two-phase pulsating power supply currents P2 'and P2 (and thus P1' and P1) with a predetermined phase difference .tau. Performs the function of delaying signal propagation. However, since this delay time includes the delay time of the latch circuit 11 itself, the delay circuit
The delay time set to 12 may be obtained by subtracting the delay time in the latch circuit 11 from the necessary delay time.

The rising P2 phase current is also supplied to the above-described amplification gate provided at the input of the first latch circuit A via the terminal Ta. When the operation is completed and the output is applied as an input signal Si, the input signal Si is amplified, and the amplified signal Si is put on standby at the input of the latch unit at the subsequent stage of the latch circuit A.

Next, as shown at time t4 in FIG.
When the phase current falls, this means the rise of the P1 'phase current of the same set. Therefore, as shown in FIG. The input signal is latched, and the subsequent delay circuit A also becomes operable.
, The delay output operation of the latch output So is started in response to the input signal applied after the signal propagation delay time of the latch circuit A itself has passed while the P1 ′ phase current is being supplied via the P1 ′ phase current.

Then, the delay circuit A still outputs the latch output.
While the So is not output, as shown at time t5 in FIG. 1 (F), when the P1 phase current belonging to the first set of two-phase pulsating current sources rises, the state shown in FIG. Power is supplied to the logic circuit A connected to the subsequent stage in advance. When the delay circuit A outputs the latch output So after this time, the logic circuit A can perform a predetermined logic operation. And returns to the state shown in FIG. After that, of course, according to the frequency of each pulsating power supply current of the first set and the second set,
The above operation is repeated. As described above, the circuit example shown in FIG. 1 constitutes a signal storage circuit having a loop configuration, which is composed of two sets of cascade circuit sets A and B, which are basic sequential operations related to the present invention. This is an example for simply describing, and as is recognized in an actual superconducting integrated circuit, an open loop configuration, a latch circuit 11, a delay circuit
12. The cascade connection of the logic circuits 21 can be expanded to circuits connected in any number of stages.

Although the delay time of signal propagation to be set in the delay circuit 12 has been described above, this delay circuit 12 is a single-stage or several-stage cascade-connected logic gate having a predetermined logical operation function. It is possible to have a configuration (although input terminals for other input variables are not shown in the figure, as in the case of the logic circuits A and B). The necessary delay time to be set in the delay circuit 12 is, for example, when the delay circuit 12 is configured as a set of a plurality of serial logic gates, by adjusting and determining the number of the logic gates, Can be set as the sum of the signal propagation delay times of

On the other hand, when the present invention is developed as an apparatus configuration, for example, the apparatus structure illustrated in FIG. 2 can be used. Here also, the corresponding reference numerals indicate constituent elements which may be the same as or similar to those in the device structure already described with reference to FIG. 4, and in the case where the description thereof is repeated, this will be avoided.

On the chip carrier (not shown) for supporting the substrate chip 31 or, as shown in the figure, on the substrate chip 31, a component of a high-frequency two-phase pulsating power supply, which is provided outside The first and second two impedance conversion transformers (signs 32 and 32 ') for impedance matching between a high-frequency power source (not shown) and a superconducting integrated circuit mounted on the substrate chip 31 are mounted. ing.

The primary windings of the first and second impedance conversion transformers 32, 32 'each have a midpoint terminal, which is provided on the substrate chip 31 as shown by the ground symbol (not shown). Connected to ground plane. At both ends of the primary winding of the first impedance conversion transformer 32, alternating currents φ1 and φ2 having phases different from each other by 180 ° through a shielded line 33 from a first high-frequency power source (not shown) provided outside through a shielded line 33. φ2 (generally a sinusoidal alternating current) is supplied, whereby an alternating current waveform having a corresponding frequency appears at both ends of the secondary winding of the first impedance conversion transformer 32.

Similarly, the second impedance conversion transformer
At both ends of the primary winding 32 ', a second high-frequency power source (not shown) provided outside via a shielded line 33' by a balanced power feeding system also has a phase difference of 180 ° which is also a sine wave alternating current. Different alternating currents φ1 ′ and φ2 ′ are supplied, whereby an alternating current waveform having a corresponding frequency appears at both ends of the secondary winding. However, note that
In the case of the present invention, between a first set of alternating currents φ1 and φ2 output from the first high-frequency power source and a second set of alternating currents φ1 ′ and φ2 ′ output from the second high-frequency power source. Means that a phase difference τ corresponding to the phase difference τ already described with reference to FIG. 1 is generated. In the case shown, the second set of AC currents φ1 ′, φ2 ′ rises earlier by τ than the first set of AC currents φ1, φ2.

First and second impedance conversion transformers
The midpoint terminal of each of the secondary windings 32 and 32 'is not grounded as it is, but it is connected to the DC bias currents Ib and Ib.
Since each of b ′ is supplied, as shown in FIG. 2, each of the secondary output alternating waveforms φ1s and φ2s appearing at both ends of the secondary winding of the first impedance conversion transformer 32, and the second impedance Each of the secondary output alternating waveforms φ1s ′ and φ2s ′ appearing at both ends of the secondary winding of the conversion transformer 32 ′ is shifted in the positive direction by that amount, and is in principle a single-phase pulsating power supply current. However, as described above, even if the current flowing through the Josephson junction element used in the driven load circuit becomes zero, the phase rotation does not immediately become zero, and punch-through may occur. In order to prevent the presence of
The magnitudes of the DC bias currents Ib and Ib 'are determined so that a current portion that enters the negative region by I and d1' remains.

A voltage regulator 34, 34; 34 ', 34', is connected in parallel to a winding portion between each end of the secondary winding of each of the impedance conversion transformers 32, 32 'and the midpoint terminal.
34 'is inserted. This function has already been described in accordance with the conventional example, and eventually functions as a current clamper, so that the first set and the second set, which are finally selectively supplied to the latch circuit 11, the delay circuit 12, and the logic circuit 21, are provided. The two-phase pulsating power supply currents of the set are the first-phase and second-phase pulsating power supply currents P1, P2; P1 ',
Formatted as P2 '. It should be noted that the current component entering the negative region described above
As described above, the magnitude of dI depends on each voltage regulator.
The value is selected within a range smaller than the critical current value of the Josephson junction used in 34, 34.

However, according to the present invention, a superconducting integrated circuit driven by such a power supply device is a latch circuit.
11 followed by a delay circuit 12, followed by a logic circuit
Although there are a large number of 21 sets, as shown in FIG. 2 together with terminal symbols corresponding to those in FIG. 1, a circuit serving as a load of the first two-phase pulsating power supply and a second two-phase pulsating power source are provided. The equivalent impedances of the circuits serving as the load of the power supply are different. Generally, the number of the logic circuits 21 is larger, and the equivalent impedance tends to be low because the equivalent impedance of each circuit is a combined value.

Therefore, as shown in the figure, power is supplied to the logic circuit 21 via the terminal Tc, or power is supplied to the amplification gate of the input portion via the terminal Ta even in the latch circuit 11. In the first power supply, when the impedance conversion ratio in the impedance conversion transformer 32 is set to, for example, about 2: 1, the power supply to the portion that causes the latch operation of the latch circuit 11 via the terminal Tb, The impedance conversion transformer 32 'that supplies power to the delay circuit via the terminal Td can have a voltage of about 8: 1. Of course, in this case, although the same peak-to-peak value is shown in the figure, that of the first input AC waveforms φ1 and φ2
Ia and Ia ′ of the second input AC waveforms φ1 ′ and φ2 ′ may be different from each other, and it is possible to reduce a case where a small overcurrent is required.
First of all, from the above, in the case of the present invention, since the number of circuits (the number of logic gates) borne by each transformer decreases, power is supplied to all circuit parts by a single impedance conversion transformer as before. As compared with the case, a small transformer can be used individually.

However, what is more characteristic of the present invention is that the phase difference between the first set of two-phase pulsating power supply currents P1 and P2 and the second set of two-phase pulsating power supply currents P1 'and P2'. The first set of two-phase pulsating power supply currents P1, P2 and the second set of two-phase pulsating power supply currents P1 ', P
There is no need to provide an overlap between the 2's. Therefore, as shown in FIG. 2, the current clamp values Ic and Ic 'by the current clampers 34 and 34' are
As described above, even if the existence of the offset currents d1 and d1 'for slightly putting the two-phase pulsating power supply current into the negative region is considered, it appears on the secondary side of the respective impedance transforming transformers 32 and 32'. The peak-to-peak value Ia, Ia 'of the current waveform is increased to approximately one half (Ic, Ic' ≒ Ia / 2, Ia '/ 2). That is, since the amount of current absorbed by the current clampers 34 and 34 'can be reduced as compared with the case of the conventional example described with reference to FIG. 4, the efficiency can be reliably improved with respect to energy consumption. In other words, it is possible to use a smaller impedance conversion transformer.

Although the preferred embodiments of the present invention have been described in detail above, any modifications can be freely made as long as the present invention is based on the gist.

[0055]

According to the present invention, a two-phase pulsating power source current shaped from another power source is used, and a pulsating power source having a phase which rises earlier than a pulsating power source current supplied to a subsequent logic circuit is used for a latch circuit. A current is supplied, and a delay circuit configured using a Josephson junction element is provided between the latch circuit and the subsequent logic circuit, and a signal propagation delay time of the delay circuit is adjusted, and the delay circuit is provided to the subsequent logic circuit. Since the latch output from the latch circuit reaches the subsequent logic circuit after the supply of the supplied pulsating power supply current, generation of a two-phase pulsating power supply current having an overlap in the same pulsating power supply Do not need. Therefore, the amount of current flowing to the current clamper can be reduced, and wasteful power consumption of the operation of the superconducting integrated circuit can be considerably reduced. As a result, the power supply itself can be downsized.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating an operation example of a superconducting integrated circuit configured according to the present invention.

FIG. 2 is an explanatory diagram of an example of a device configuration satisfying the present invention.

FIG. 3 is an explanatory diagram relating to an operation example of a conventional superconducting integrated circuit.

FIG. 4 is a schematic configuration diagram relating to a device configuration example of a conventional superconducting integrated circuit.

[Explanation of symbols]

 11 latch circuit, 12 delay circuit, 21 combinational logic circuit, 31 substrate chip, 32, 32 'impedance conversion transformer, 34, 34' voltage regulator (voltage clamper), P1, P2 First set of two-phase pulsating current P1 ', P2' Second set of two-phase pulsating power supply current.

Claims (9)

[Claims] A plurality of combinational logic circuits and a plurality of latch circuits each using a Josephson junction element, wherein the plurality of combinational logic circuits have the same frequency but a predetermined phase difference from each other. And a group driven by one of the first and second phase pulsating power supply currents, and each of the combinational logic circuits is supplied with the pulsating power supply current respectively. After the input signal is applied, a predetermined logical operation is performed, a logical operation result signal is output, and the plurality of latch circuits also have a first phase having the same frequency and a predetermined phase difference from each other. , A group driven by one of the second-phase pulsating power supply currents, and a group driven by the other.
In the state where the logical operation result signal output by the combinational logic circuit provided in the preceding stage of the latch circuit among the plurality of combinational logic circuits reaches the input of the latch circuit first, Only when the pulsating power supply current is supplied, the logical operation result signal is latched at the timing when the pulsating power supply current is supplied, and the logical operation result signal is provided at a subsequent stage as an output of the latch circuit. A superconducting integrated circuit that is a direct-coupled latch circuit configured to pass to a combinational logic circuit; the first and second phase pulsating power supply currents driving the combinational logic circuit. Supplying a first set of two-phase pulsating power supply currents from the first two-phase pulsating power supply; and supplying the first and second phase pulsating power supply currents for driving the latch circuit to a second set of two-phase pulsating power supply currents. The second as pulsating power supply current Providing a predetermined phase difference between the first set of two-phase pulsating power supply currents and the second set of two-phase pulsating power supply currents; A predetermined circuit between the first set of two-phase pulsating power supply currents and the second set of two-phase pulsating power supply currents is configured using a Josephson junction element between the combinational logic circuits at the subsequent stage of the latch circuit. A delay circuit for delaying a latch output from the latch circuit in accordance with a phase difference; 2. The superconducting integrated circuit of claim 1, wherein the first set of the first phase, the phase difference between the second phase pulsating power supply currents, and the second set of the first phase, The phase difference between the second-phase pulsating power supply currents is 180 °; 3. The superconducting integrated circuit according to claim 1, wherein said delay circuit is a single-stage or combinational logic circuit having a logical operation function. 4. The superconducting integrated circuit according to claim 1, wherein said first and second sets of two-phase pulsating power supplies are:
Each including an impedance conversion transformer having a primary winding having a midpoint terminal and a secondary winding also having a midpoint terminal; the midpoint terminal of each of the primary windings of each impedance conversion transformer is a superconducting integrated Connected to a ground plane that establishes the ground potential of the circuit, and to both ends of the primary winding are supplied alternating currents 180 ° out of phase with each other, which are supplied from the outside by a balanced power supply system; A DC bias current is externally supplied to the midpoint terminals of the respective secondary windings; and a voltage regulator is interposed between both ends of the secondary windings and the midpoint terminal of the secondary windings. Thereby, the alternating current output appearing at both ends of the secondary winding is shaped into the first-phase and second-phase pulsating power supply currents; 5. The superconducting integrated circuit according to claim 4, wherein the impedance conversion transformer is provided on a substrate chip on which the combinational logic circuit and the latch circuit are constructed. Superconducting integrated circuits. 6. The superconducting integrated circuit according to claim 4, wherein said impedance conversion transformer is provided on a chip carrier that supports a substrate chip on which said combinational logic circuit and said latch circuit are constructed. thing;
A superconducting integrated circuit characterized by the following. 7. A plurality of combinational logic circuits configured using a Josephson junction element and performing a predetermined logical operation by applying an input signal after a pulsating power supply current is supplied, and a Josephson junction element The logic operation result signal calculated by the combinational logic circuit provided in the preceding stage is latched at the timing when the pulsating power supply current is supplied, and is passed to the combinational logic circuit provided in the subsequent stage. A method of driving a superconducting integrated circuit having a latch circuit of a direct coupling type, wherein the combinational logic circuit provided at the preceding stage of the latch circuit has a phase of 180 °.
One of the different first-phase and second-phase pulsating power supply currents and the other to the combinational logic circuit provided at the latter stage of the latch circuit; And a pulsating power supply current having a phase rising faster than the pulsating power supply current supplied to the combinational logic circuit; and a Josephson junction element is provided between the latch circuit and the subsequent combinational logic circuit. Adjusting the signal propagation delay time of the delay circuit;
The latch output of the latch circuit reaching the subsequent combinational logic circuit after the supply of the pulsating power supply current supplied to the subsequent combinational logic circuit; Drive method. 8. The method according to claim 7, wherein said delay circuit is configured using a combinational logic circuit having a logical operation function. 9. The method according to claim 7 or 8, wherein:
The signal propagation delay time of the delay circuit is set as the total signal propagation delay time of each logic gate by determining the number of the plurality of serial logic gates constituting the delay circuit. how to.