CN100433021C - Pipelined buffer - Google Patents
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- CN100433021C CN100433021C CNB2005100554840A CN200510055484A CN100433021C CN 100433021 C CN100433021 C CN 100433021C CN B2005100554840 A CNB2005100554840 A CN B2005100554840A CN 200510055484 A CN200510055484 A CN 200510055484A CN 100433021 C CN100433021 C CN 100433021C
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- 239000000872 buffer Substances 0.000 title claims abstract description 33
- 238000012546 transfer Methods 0.000 claims description 21
- 230000004087 circulation Effects 0.000 description 7
- 238000000034 method Methods 0.000 description 7
- 238000006243 chemical reaction Methods 0.000 description 5
- 238000013461 design Methods 0.000 description 4
- 230000001360 synchronised effect Effects 0.000 description 4
- 230000004913 activation Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000003139 buffering effect Effects 0.000 description 2
- 238000005265 energy consumption Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000000644 propagated effect Effects 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 230000008901 benefit Effects 0.000 description 1
- 230000008033 biological extinction Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000011960 computer-aided design Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 230000037361 pathway Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 230000010349 pulsation Effects 0.000 description 1
- 238000010079 rubber tapping Methods 0.000 description 1
- 238000002922 simulated annealing Methods 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 235000013599 spices Nutrition 0.000 description 1
- 238000012421 spiking Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
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Abstract
The invention relates to a pipeline buffer provided with a logical one routing separated form a logical zero routing. Each routing includes plural levels, and each level comprises an output which is connected with an input of the next level to form a chain. Each level in each routing comprises a connection to a polyphase rotary clock, wherein, adjacent levels have the rotary clock with different phase positions. In an embodiment, each level has a structure similar to a moving point generator. The logical one routing transmits logical one from the input thereof in the phase positions of the rotary clock through the output to the pipeline buffer of all levels thereof. The logical zero routing (which is an opposite phase of the input in the logical one routing) transmits logical one to each phase position on the rotary clock through the output of all levels thereof; however, the output of the last level is the opposite phase before connecting to the output of the pipeline buffer.
Description
The cross reference of related application
The application's case is the part of No. 03/000719 international application of PCT/GB of submission on February 14th, 2003; The right of priority of the GB 0218834.0 that it requires to submit on February 15th, 2002 GB submitted at June 6 in 0203605.1,2002 GB submitted at June 27 in 0212869.2,2002 GB submitted at August 14 in 0214850.0,2002 and the GB 0225814.3 of submission on November 6th, 2002.The theme of No. 03/000719 international application of PCT/GB is incorporated in this division by reference.
The cross reference of related application
Patent application case PCT/GB00/00175 and GB 0203605.1 (pipelined buffer clocked) are incorporated herein with way of reference.
This application case is the part of PCT/GB 03/000719.
Technical field
High temporary degree of accuracy, high-energy, multistage pipeline cmos buffer device
Background technology
VLSI CMOS logical unit adopt usually impact damper (current amplifier) with allow the control signal fast driving such as those by interconnection or capacity load that transistor capacitance was produced.
Traditionally, thus the CMOS chain of inverters with progressive big level will be cascaded in low drive signal and the effective impact damper of formation between such as the high capacitance load of clock load.More multistagely provide more powerful output of power and conversion (lifting/lowering number of times) faster, but cause the propagation delay of increase between input conversion and output conversion.In addition, described time delay is non-constant, but depends on the variation of CMOS processing/temperature and supply voltage (PVT).
Described variation is the time delay that is used to modulate any impact damper, and for example the variation of 10% supply voltage can produce variation 10% time delay in impact damper.
In the application that distributes such as clock, the temporary degree of accuracy of signal is most important.For the classification of clock system, the variation that is known as " time lag " and time delay time delay is known as " shake ".
Figure 1A/D29 shows the common structure of the multistage inverter buffer of standard CMOS.
So far, the lithographic plate convergent-divergent of CMOS (lithographic scaling) has produced the useful performance from impact damper gradually.When each the generation, shrink process produces transistor faster, it will imply the time lag of reduction, but present transistorized variation (length variations that for example has the device of 0.13u or following grid length) can produce the impact damper of the time delay that has relative to each other (even on same die) serious mismatch.Another problem of installing convergent-divergent is the supply voltage of reduction and higher source current, and it causes and will modulate and the direct power supply noise that exert an influence to shake by delay.
For timing was used, wherein impact damper was placed on the entire wafer, and the matching delay time very crucial (definite delay is really unimportant), buffering become be difficult to solve and can cause according to reports up to+/-uncertainty of 1000pS.
Except that postponing variation, impact damper commonly used shows unwanted proterties more than two.
Too much input capacitance
Each grade has P and the N transistor that typical total capacitance is the 2.5+1=3.5 relative unit.For any conversion of impact damper, all these electric capacity must be charged to another polarity.This has reduced the performance of impact damper, because before next stage activates, each level must make a transistor charging close and make another transistor charging to open.
Connect or cross-conduction spiking (spike)
When the conversion input voltage, each P passage/N passage inverter stage then shows a direct current path at the S-D of P passage between the D-S on the N passage.In the transition period, the clock energy up to 10% is wasted in conduction simultaneously.
The problem list of cmos buffer device
Generally, the standard CMOS impact damper shows following passive attribute:
The long time delay (in the clock distribution applications, producing up to 20 distribution levels) that needs long chain of inverters by CTS (clock trees synthetics).
Because the delay that deep sub-micron processes control problem causes changes (time lag).
Crossed the shake of the supply voltage noise introducing of long delay by modulation.
By adjusting the excess energy consumption (substantially exceeding Cload*V2*F) that the excessive impact damper of size causes for reaching acceptable delay.
1 and 2 s' effect can be by using such as the feedback technique of PLL (phase-lock loop) and DLL (delay-locked loop) and greatly offset, but these technology will increase problem 3 and 4 and the influence of increase chip area.
Summary of the invention
An impact damper according to the present invention is a pipeline buffers.Described pipeline buffers comprises one first path and one second path.Logic one of described first propagated and comprise a plurality of transfer point levels that include the last level of a first order and.The described data output of a level is connected to a data input of next stage to form a chain.Each grade also has an input that is connected to a tap of a rotary clock, but the adjacent levels in the described chain is connected to different rotary clock taps.The described input of the described first order receives a positive logic data-signal, and the described output of described afterbody is the described output of described pipeline buffers.Each level in described first path comprises plurality of transistors, and in each level except the described first order, at least one described transistor is bigger than a transistor in the first prime.Logical zero of described second propagated, and it comprises a plurality of transfer point levels that include one first and one last level, and the described data output of a level is connected to a data input of next stage to form a chain.Each grade has an input that is connected to a tap of described rotary clock, but the adjacent levels in the described chain is connected to different rotary clock taps.The described input of the described first order receives a negative logic data-signal and described last level comprises a phase inverter that is connected to described last grade the described output in described first path.Each grade in described second path comprises plurality of transistors and in each level except the described first order, at least one described transistor is bigger than a transistor in the first prime.
Description of drawings
Figure 1A shows the single phase inverter of CMOS of a standard;
Figure 1B shows a standard CMOS buffer chain;
Fig. 2 shows a transfer point generator;
Fig. 3 shows the output of a transfer point generator;
Fig. 4 shows pipeline of the present invention, sub-path impact damper;
Fig. 5 A shows the timing indicator in pipeline buffers chain " 1 " path; With
Fig. 5 B shows the timing indicator in pipeline buffers chain " 0 " path.
Embodiment
The pipeline method of buffered clock signal
For alleviating the problems referred to above 1,2,3, should make impact damper have minimum possible delay.This will point out the minimum number of existing level in the chain, only be a level ideally.Yet this is also infeasible, is generally a weak signal because drive the circuit of impact damper--as, the impossible logical signal that directly drives huge single impact damper.
For the periodicity clock generating is used, known if postpone between impact damper coupling and therefore clock signal be synchronous fully, the bulk delay of impact damper is unimportant so.
This knowledge allows to use the pipeline method to cushion.Logical pipeline is known by people, and wherein finishing its logic evaluation before next event clock, so it is delivered to next pipe level with the result to each logic level by clock signal control.Logical pipeline can be consistent with the overall stand-by period of height (many circulations), but with the throughput consistent (in case described pipe is full of) of an operation of each clock circulation.The pipeline buffers of creating simple form with make the logical pipeline equivalence, but described logical pipeline does not have in related actual logic at different levels, only identical input state (or inverse state of input state) is delivered to the next stage synchronous with the clock edge.
In-line can add logic to allow the logical timer gating.If impact damper pipeline at different levels becomes (aspect transistor width) greatly progressively, it becomes stronger (as aspect its driving force) when pipeline moves down when signal so, and it can be amplified to any desired intensity by adding pipeline stages new, that progressively increase.Because the house-keeping (overhead) of clock, so may be longer than the conventional cmos buffer chain time delay of pipeline method usually, but the key point that should note is to be controlled to be time delay N clock circulation (N is a length of pipeline)+1 buffer delay time (final impact damper).Uncertain is the time delay of single-stage impact damper--the N circulation delay time is also uncorrelated with the cyclical signal such as clock.
The applied clock gating is to be used for not containing the operation of glitch in pipeline.
The separation path method of buffered clock signal
The standard cmos buffer utensil of Figure 1A/D29 has the path that can be described as " combination " path, it is used to amplify the signal of opposed polarity, and promptly to pass P passage/N passage identical to the circuit paths of inverter stage for the logical one input signal circuit paths that advances to output institute edge and logical zero.This causes separating too much delay that path design compares (previous mentioning) with following.
Be the time delay of quickening impact damper, it can be divided into path, two paths (only at two separation circuits exporting and/or make up the input) " 1 drives " and " 0 drives ".
Because each circuit has only in order to specific output polarity is carried out the megacryst pipe in " unlatching " path, so each path can (still need small transistor to make the path be reset to " off-line " on the non-activation output cycle, but these not influence speed) very soon.Lack huge device to be closed and conventional cmos chain of inverters and form contrast, wherein non-activation polar transistor can slow down the carrying out that any state changes in the impact damper.
" 1 " and " 0 " path of separating is made up at outgoing side, and for the subsidiary benefit of independent pathway system for when reasonable in design, can eliminate the cross-conduction current spike signal.By the signal timing of controlling two paths final N passage and P lane device are activated never simultaneously.
One exemplary embodiment
Fig. 2/D29 is the structural drawing of the illustrative example of system of global timing, incorporates in the system of described global timing to be useful on pipeline, the sub-path impact damper that drives final clock load.
The high frequency 4 phase 3.125GHz rotary clock network coverages have an entire wafer of phase locking clock.Local frequency division or more complicated waveform logic (BWB is referring to application GB 0203605.1) have produced the required clock signal that is used to supply to impact damper.In this example, used a 1mm * 1mm grid of BWB and impact damper, and needed each impact damper in the area of its 1mm2, to drive to reach 50pF.
The transfer point generator
(Fig. 2/D29) is provided for frequency division and/or produces the timing sequence signal of random waveform to be driven into " transfer point " pattern generator of high speed 3.125GHz rotary clock from tap.Show two-stage.For more than 2 grades, with CLK 90 and then CLK 270 (or 180 degree clocks of other out of phase) the alternation level is carried out timing.Circuit is at " height " time durations of each self-clock, operates by will " 1 " on OUTN being sent to OUTN+1.
This circuit can replace those circuit in [application GB 0203605.1] and have and the similar output waveform of Fig. 3/D 30 those output waveforms that is used for 6 grades of designs.
Sequence on each edge of 3.125 GHz clocks, advance (6.25GHz speed, i.e. 160 pS at interval).When reaching new " point " position, feedback transistor nclr and pclr are reduced to static state with first prime.Offset transistor (not shown) be as nch and the pch transistor through being connected, but its grid is connected respectively to Vdd and 0v, and adjusts size and absorb leakage current so that the slight shift electric current to be provided.
Transfer point generator (with typical rotary clock electronic equipment) is positioned at the node place of rotary clock grid.When tap was told in the correct selection one of in to 4 local phase, the global clock phasing between any two corners was on the 3.125GHz mostly+/-30pS.May designing the impact damper with slightly different time delay, to offset the known phase of source clock poor.
A plurality of for making " transfer point " generator is synchronous, the final output of a generator is connected to the input of next generator on the wafer.These links are configured so that main generator (it is a unique generator that is configured to produce circular pattern (output at last is fed back to first input))) can force all other generators moved further same with it.Synchronization consumes many " (wrap-around) unrolls " with pulsation around entire wafer.Fig. 2/D29 shows this.
For the chip area that is taken by transfer point sequencer (it can be long up to 100) is minimized, will adjust transistor size and make it near minimum feature size.Little circuit like this has more weak output driving force and can drive at it to be needed before may being equivalent to the load of 50pF local clock through buffering.
The pipeline buffers circuit
Show sub-path pipeline buffers (split path pipelined buffer) among Fig. 4.
Upper path finishes " 1 " outgoing route with the P lane device.
Lower path finishes " 0 " outgoing route with the N lane device.
Because signal moves with each 1/2 clock circulation, so each path and transfer point generator circuit have some similar part, but in these buffer chain, transistor size may increase gradually with the amplitude of 5 times of each increases at different levels.For " 1 " path, begin with 8 microns wide first order input N passages, finish with the P passage output buffer that is enough to after driving 2150 microns of 50pF 4 grades under the 200pS.
The input that to arrive each path first order sends in an output of transfer point sequencer (or using in a plurality of outputs of OR-gate).
In the example simulation, may be to the input in " 1 " path from the Q0 output of transfer point generator, the input of wherein arriving " 0 " impact damper path may be from the Q 4 (it is for after two recycle to extinctions of 3.125GHz clock) of transfer point generator.The result of this configuration is illustrated in the Spice result of Fig. 5 A and Fig. 5 B.
Pipeline from IN and IN_N postpones--and RNTO Q0 and Q4 are unimportant for the circulation Generation of Clock Signal.
But because the recycle of capacitive character energy, so when using the rotary clock tap, the high frequency clock energy consumption that drives this pipeline is very low.
Eliminate perforation electric current (Shoot-through current)
What show on " 1 " path of Fig. 4 is the transistor that grid is reset on final P passage (w=2143u) transistor.By driving this circuit from " early " output of " 0 " path chain " except that 1 then go out advanced person (out_lastbut 1) ".Activation signal provides the early stage indication that will be switched about " 0 " output transistor herein, thereby to allow big P passage in time to turn-off the perforation conduction current of avoiding in the output stage.Do not show by the circuit of closing " 0 " output transistor from the early stage indication of " 1 " pipeline, but can easily from previous example, derive.
Logic gate and the programmable tapping point of use from the transfer point sequencer to two impact damper paths can be created the random waveform with 160pS resolution.Select other two-phase in 4 phase clocks can make the sequence biasing+/-80pS.Because the transfer point sequence is round-robin (unrolling), so will produce continuous wave with the frequency lower in the OUT port than global clock speed.
Because the transfer point generator on the wafer is synchronous operation, thus any local clock can be created, but other clock has accurate phase place and frequency relation on itself and the wafer.This helps the SOC of many IP block integrated.
Other selection (transfer point+able to programme decoding) IN and the IN_N signal to be provided for branch pipeline buffers of existence except using AWG (Arbitrary Waveform Generator).A kind of technology is to use from the overall situation distribution IN of external pin and IN_N signal.IN through distributing and IN_N signal self can be by pipelineization (that is, periodically resample on the upper frequency rotary clock edge in distributing and emission again) to keep aligning.Use this configuration to allow to carry out external control for internal clocking impact damper from (for example) external testing clock generator.With regard to/V circulation, will have the stand-by period (latency), but the random variation of last several buffer level is still very little.
Other reference:
[Lui] Retiming and Clock Scheduling for Digital CircuitOptimization, IEEE transactions on Computer Design and IntegratedCircuits and Systems the 21st volume, No.2, in February, 2002 [Lui] Xun Liu, MariosC.Papaefthymiou, Eby.G.Friedman.
[TIM] M.C.Papaefthymiou and K.H.Randall " TIM:Atiming package fortwo-phase, level clocked circuity " Proc.30th ACM/IEEE DesignAutomation Conf.1993 June.
[Timberwolf] C.S echen and K.-W.Lee.An improved simulatedannealing algorithm for row-based placement.In Digest of Papers, International Conference on ComputerAided Design, the 478-481 page or leaf, Santa Clara, CA, in November, 1987.
Although described in detail the present invention with reference to some preferred version of the present invention, other version This also is possible. Therefore, the spirit of the claims book and category should not be defined in institute herein The description of the preferred version that contains.
Claims (6)
1. pipeline buffers, it comprises:
First path that is used to propagate a logic one, described first path comprise a plurality of transfer point levels that include a first order and a last level,
The data input that data output of one of them grade is connected to next level to be forming a chain,
Wherein each grade has an input that is connected to a tap of a rotary clock, adjacent levels in the described chain is connected to different rotary clock taps, the described input of the described first order is used for receiving a positive logic data-signal, described last level described be output as described pipeline buffers described output and
Wherein each level comprises plurality of transistors, and in each level except the described first order, at least one described transistor is bigger than the transistor in a first prime; With
Second path that is used to propagate a logical zero, described second path comprise a plurality of transfer point levels that include one first and one last level,
The data input that data output of one of them grade is connected to described next level to be forming a chain,
Wherein each grade has an input that is connected to a tap of described rotary clock, adjacent levels in the described chain is connected to the tap of different rotary clock, the described input of the described first order is used to receive a negative logic data-signal, described last level comprise a described last level that is connected to described first path described output phase inverter and
Wherein each level comprises plurality of transistors, and at least one described transistor is bigger than the transistor in a first prime in each grade except the described first order.
2. pipeline buffers according to claim 1, wherein the described rotary clock tap of adjacent levels has the phase place that differs 180 degree.
3. pipeline buffers according to claim 1,
Wherein each transfer point level comprises one first and second n channel transistor and a p channel transistor, wherein each transistor have a grid and one between a source electrode and drain electrode passage and
The wherein said first and second n channel transistors are connected in series between the described grid of described p channel transistor and ground connection reference mode its passage, described p channel transistor is connected between the described output of a power supply reference mode and described level its passage, and the described grid that the described grid of a described n channel transistor receives a clock input and described the 2nd n channel transistor receives a data input.
4. pipeline buffers according to claim 3, wherein each transfer point level comprises a p passage and a n passage feedback transistor, described p passage feedback transistor is used for the described grid of the described p channel transistor of precharge, and described n channel transistor is used for pre-arcing and receives the described grid of the described n channel transistor of described data input.
5. pipeline buffers according to claim 4,
The described p passage feedback transistor of one of them current stage has a grid and one passage between a source electrode and drain electrode, described grid is connected to the described grid of the described p channel transistor of described next stage, described passage be connected between the described grid of described p channel transistor of described power supply reference mode and described current stage and
The n passage feedback transistor of one of them current stage has a grid and one passage between a source electrode and drain electrode, described grid is connected to the described input of described next stage, and described passage is connected between the described data input and described ground connection reference mode of described current stage.
6. pipeline buffers according to claim 1, wherein, in described first and second paths, a transistorized size in a current stage is 5 times of a transistorized size in a first prime.
Applications Claiming Priority (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB0203605A GB0203605D0 (en) | 2002-02-15 | 2002-02-15 | Hierarchical clocking system |
| GB0203605.1 | 2002-02-15 | ||
| GB0212869.2 | 2002-06-06 | ||
| GB0214850.0 | 2002-06-07 | ||
| GB0218834.0 | 2002-08-14 | ||
| GB0225814.3 | 2002-11-06 |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA03808371XA Division CN1647012A (en) | 2002-02-15 | 2003-02-14 | Electronic circuits |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1776691A CN1776691A (en) | 2006-05-24 |
| CN100433021C true CN100433021C (en) | 2008-11-12 |
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ID=9931139
Family Applications (5)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200510055487 Pending CN1808448A (en) | 2002-02-15 | 2003-02-14 | Rotary clock logic |
| CN 200510055488 Pending CN1818911A (en) | 2002-02-15 | 2003-02-14 | Rotary clock designing flow |
| CN 200510055486 Pending CN1808328A (en) | 2002-02-15 | 2003-02-14 | Pipelined buffer clocked with different phases of a rotary clock |
| CNB2005100554840A Expired - Lifetime CN100433021C (en) | 2002-02-15 | 2003-02-14 | Pipelined buffer |
| CN 200510055485 Pending CN1808447A (en) | 2002-02-15 | 2003-02-14 | Tagged mode driver |
Family Applications Before (3)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200510055487 Pending CN1808448A (en) | 2002-02-15 | 2003-02-14 | Rotary clock logic |
| CN 200510055488 Pending CN1818911A (en) | 2002-02-15 | 2003-02-14 | Rotary clock designing flow |
| CN 200510055486 Pending CN1808328A (en) | 2002-02-15 | 2003-02-14 | Pipelined buffer clocked with different phases of a rotary clock |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200510055485 Pending CN1808447A (en) | 2002-02-15 | 2003-02-14 | Tagged mode driver |
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| CN (5) | CN1808448A (en) |
| GB (1) | GB0203605D0 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106505990A (en) * | 2015-09-08 | 2017-03-15 | 飞思卡尔半导体公司 | There is the input buffer of optional delayed and speed |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8581668B2 (en) * | 2011-12-20 | 2013-11-12 | Analog Devices, Inc. | Oscillator regeneration device |
| CN104240753B (en) * | 2013-06-10 | 2018-08-28 | 三星电子株式会社 | Cynapse array, pulse shaper and neuromorphic system |
| CN104348450B (en) * | 2014-10-16 | 2016-11-30 | 新港海岸(北京)科技有限公司 | A kind of clock jitter eliminates circuit |
| US9552456B2 (en) * | 2015-05-29 | 2017-01-24 | Altera Corporation | Methods and apparatus for probing signals from a circuit after register retiming |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5325502A (en) * | 1991-05-15 | 1994-06-28 | Micron Technology, Inc. | Pipelined SAM register serial output |
| CN1243316A (en) * | 1998-07-28 | 2000-02-02 | 日本电气株式会社 | Readout amplifier circuit |
| CN1300465A (en) * | 1999-04-16 | 2001-06-20 | 塔特公司 | Improved operational amplifier output stage |
| CN1332518A (en) * | 2000-04-26 | 2002-01-23 | 日本精密电路株式会社 | Amplifier |
-
2002
- 2002-02-15 GB GB0203605A patent/GB0203605D0/en not_active Ceased
-
2003
- 2003-02-14 CN CN 200510055487 patent/CN1808448A/en active Pending
- 2003-02-14 CN CN 200510055488 patent/CN1818911A/en active Pending
- 2003-02-14 CN CN 200510055486 patent/CN1808328A/en active Pending
- 2003-02-14 CN CNB2005100554840A patent/CN100433021C/en not_active Expired - Lifetime
- 2003-02-14 CN CN 200510055485 patent/CN1808447A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5325502A (en) * | 1991-05-15 | 1994-06-28 | Micron Technology, Inc. | Pipelined SAM register serial output |
| CN1243316A (en) * | 1998-07-28 | 2000-02-02 | 日本电气株式会社 | Readout amplifier circuit |
| CN1300465A (en) * | 1999-04-16 | 2001-06-20 | 塔特公司 | Improved operational amplifier output stage |
| CN1332518A (en) * | 2000-04-26 | 2002-01-23 | 日本精密电路株式会社 | Amplifier |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106505990A (en) * | 2015-09-08 | 2017-03-15 | 飞思卡尔半导体公司 | There is the input buffer of optional delayed and speed |
| CN106505990B (en) * | 2015-09-08 | 2021-12-03 | 恩智浦美国有限公司 | Input buffer with selectable hysteresis and speed |
Also Published As
| Publication number | Publication date |
|---|---|
| GB0203605D0 (en) | 2002-04-03 |
| CN1808448A (en) | 2006-07-26 |
| CN1776691A (en) | 2006-05-24 |
| CN1818911A (en) | 2006-08-16 |
| CN1808447A (en) | 2006-07-26 |
| CN1808328A (en) | 2006-07-26 |
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