JPH10163477A - Semiconductor device and fabrication thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a junction leakage current from increasing at a source- drain part by forming a selective epitaxial layer stretching from an LDD layer at the source-drain part of an MOS transistor by a given width onto a device region adjacent to the LDD layer. SOLUTION: Since a high integration high speed semiconductor device has a selective epitaxial layer 31 grown from an LDD layer 17 at a source-drain part while stretching onto a trench element isolation region 12, the bottom part of a contact hole 23 does not come into direct contact with the boundary between the trench element isolation region 12 and the LDD layer 17 and thereby abnormal deposition of TiSi2 20 is prevented in the formation of TiSi2 20. Furthermore, since an additional interval corresponding to pattern matching margin is not required between a contact hole 23 and the trench element isolation region 12, length at the MOS transistor part is shortened thus realizing high integration of semiconductor device.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a highly integrated semiconductor device including a MOS transistor as a constituent element.
The present invention relates to a highly integrated semiconductor device having a feature in a source / drain portion of an OS transistor portion and a method for manufacturing the same.

[0002]

2. Description of the Related Art In recent years, with the increase in speed and integration of MOS transistor type semiconductor devices, each component of the semiconductor device has been increasingly miniaturized. For example, the gate electrode length of a MOS transistor has become less than half a micron. ing. For this reason, in the manufacture of a high-speed, highly integrated semiconductor device, not only the development of a microfabrication technique, but also the development of the configuration of the MOS transistor itself in consideration of the short channel effect of the MOS transistor and the like, and a low-resistance wiring technique Has been actively developed. Such a high-speed, highly integrated semiconductor device and its manufacturing method will be described with reference to FIG.

First, as shown in FIG. 2A, a trench isolation region 12 is formed on the surface of a P-type semiconductor substrate 11, and then a gate oxide film 13 is formed by thermal oxidation.
A polysilicon film 14 is deposited by a method D, and a Co film is further deposited by a sputtering method. Thereafter, a heat treatment is performed to cause the polysilicon film 14 and the Co film to react with each other, thereby forming a CoSi ₂ film as a refractory metal silicide film. 15 are formed.
Thereafter, a CVD SiO ₂ film 16 is formed by the CVD method.

Next, photolithography technology and RIE
(Reactive Ion Etching) method and the like, the CVD SiO ₂ film 16 / CoSi ₂ film 15 / polysilicon film 14 / gate oxide film 13 are patterned to form the polysilicon film 14 and the CoSi ₂ film 15 in the MOS transistor portion 1. Gate electrode 2 composed of
The gate electrode portion 2 having a is formed. Thereafter, As ions are implanted into the surface of the semiconductor substrate 11 by an ion implantation method, and LDD (Lightly Doped Drain) is implanted.
n) The layer 17 is formed.

[0005] Next, as shown in FIG. 2 (b), after depositing a CVD SiO ₂ film by the CVD method, the CVD SiO ₂ film is etched back by anisotropic etching such as RIE to form a gate electrode portion 2. A sidewall oxide film 18 is formed on the side wall of. Thereafter, As ions are implanted by an ion implantation method, and a heat treatment such as activation of the implanted ions is performed, so that the source / drain layer 19 having the LDD layer 17 is formed in the source / drain section 3 of the MOS transistor section 1.
Is formed, the polysilicon film 14 becomes a low-resistance polysilicon film 14 due to the implanted As ions.

Next, as shown in FIG. 2C, the side wall oxide film 18 is formed when forming a self-aligned contact hole.
SiN film 21 formed by CVD or the like for maintaining the shape
BPSG (Boro-Phospho)
An interlayer insulating film 22 such as a Silicate Glass film is deposited. Then, CMP (ChemicalM
After performing a flattening treatment of the interlayer insulating film 22 by using an electrical polishing method or the like, the interlayer insulating film 22 / SiN film 21 is etched by RIE or the like using a patterned photoresist as a mask, and the source / drain is etched. A contact hole 23 is formed in the part 3 and the like. The contact hole 23 is a partially self-aligned contact hole 23 only on the gate electrode 2 side, as shown in FIG.

Next, electrodes such as the source / drain portion 3 are formed. This electrode formation is performed first by securing the ohmic contact with the source / drain layer 19 and by forming the source / drain layer 1.
A TiSi ₂ film 20 described later is formed for lowering the resistance of 9 parts. To form the TiSi ₂ film 20, a Ti film is first deposited by a sputtering method or the like, and then a low-temperature heat treatment is performed. By this low-temperature heat treatment, the silicon in the source / drain portion 3 reacts with the Ti film, and a C49-phase TiSi ₂ film having a low-temperature stable phase and high resistance is formed in the source / drain portion. After that, the side wall of the contact hole 23 and the interlayer insulating film 2
2 The unreacted Ti film on the surface and the like is removed by a mixed solution of sulfuric acid and hydrogen peroxide solution. Thereafter, a high-temperature heat treatment is performed to cause a phase transition of the C49 phase TiSi ₂ film, thereby forming a high-temperature stable phase and low-resistance C54 phase TiSi ₂ film 20.
Thereafter, a TiN film 24 serving as a barrier film is deposited by a reactive sputtering method or the like, and a blanket W film 25 is further deposited by a CVD method. Then, etch back is performed, and the blanket W film 25 and the TiN film 24 are Plug, so-called tungsten plug 2
6 is formed. As described above, the source / drain layer 1
9 and the like are formed.

Thereafter, although not shown in the drawings, after depositing a TiN film or an Al alloy film, forming a wiring by patterning, further depositing a passivation film and the like, opening a window of a pad portion, and the like. Make the device.

As described above, a highly integrated and high speed semiconductor device is manufactured.
When forming the contact hole 23 to the drain part 3,
As shown in FIG. 2C, an interval corresponding to the pattern matching accuracy, that is, a distance equal to or longer than the alignment margin ΔL needs to be provided between the trench element isolation region 12 and the contact hole 23. If the alignment margin Δ
The design of the semiconductor device without taking L equal distance, the contact hole is formed causing a misalignment of the pattern, as shown in FIG. 3, with TiSi ₂ film 20 forming step, the source-drain layer 19 and trench element isolation region 1
Due to the distortion at the boundary with the _second layer ₂ , an abnormal reaction or abnormal diffusion of Ti occurs at the boundary, thereby forming an abnormal portion 27 of the TiSi ₂ film 20. When the abnormal portion 27 is formed, there is a possibility that a junction leak current may increase when a voltage is applied to the source / drain layer 19.

For the above-described reasons, when forming a contact hole 23 in the source / drain layer 19 or the like, a semiconductor device is designed with an alignment margin .DELTA.L, so that MOS transistors having the same dimensions are two-dimensionally arranged. In a semiconductor device such as a memory having such a configuration, a length L _{1 of} one MOS transistor unit 1 needs to be twice as long as the alignment margin ΔL, as shown in FIG. 2C. There is. Therefore, there is a problem that it becomes a hindrance to the high integration of the semiconductor device. In the above semiconductor device, the element isolation region is a trench element isolation region.
LOCOS (Local Oxidation) having an insulating film in an element isolation region above the surface of the semiconductor substrate 11
f Silicon) There is also a method for achieving high integration of a semiconductor device by forming a self-aligned contact hole by using an element isolation region. However, it is difficult to reduce the width of a LOCOS element isolation region. Not only is it difficult to achieve high integration, but if the contact hole is a complete self-aligned contact hole, the same phenomenon occurs at the periphery of the LOCOS isolation region as at the periphery of the trench isolation region 12 described above. May increase the junction leakage current.

[0011]

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems in the semiconductor device and the method for manufacturing the same. That is, the object of the present invention is to
Between the drain contact hole and the element isolation region,
It is an object of the present invention to provide a highly integrated semiconductor device which does not have an interval corresponding to pattern alignment accuracy and a method for manufacturing the same.

[0012]

According to the present invention, there is provided a semiconductor device comprising:
It is proposed to solve the above-mentioned problem, and
In a highly integrated semiconductor device including an S transistor as a constituent element, a selective epitaxial layer extending a predetermined width from an LDD layer in a source / drain portion of a MOS transistor to an element isolation region adjacent to the LDD layer. It is characterized by the following.

Further, a method of manufacturing a semiconductor device according to the present invention
In a highly integrated semiconductor device including a MOS transistor as a constituent element, a step of forming an element isolation region in a semiconductor substrate, a step of forming a gate electrode part of the MOS transistor, and a step of forming an ion in a source / drain part of the MOS transistor Forming an LDD layer by an implantation method;
A step of forming a sidewall insulating film on the side wall of the gate electrode portion, a step of forming a selective epitaxial layer from the LDD layer of the source / drain portion by selective epitaxial crystal growth, and a step of forming a selective epitaxial layer by ion implantation. A step of lowering the resistance of the selective epitaxial layer by ion implantation, a step of depositing an interlayer insulating film, forming a contact hole in the interlayer insulating film, and forming an electrode connected to the selective epitaxial layer in the contact hole portion And a process.

According to the present invention, a selective epitaxial layer is grown from the LDD layer of the source / drain portion of the MOS transistor portion, and extends over the device isolation region adjacent to the source / drain layer. By making the width of the upper selective epitaxial layer approximately equal to the dimension of the pattern alignment accuracy, the bottom of the contact hole can be configured not to directly intersect with the periphery of the element isolation region.
When the Si ₂ film is formed, an abnormal portion of the TiSi ₂ film is not formed in the source / drain layer, and an increase in junction leak current of the source / drain layer can be suppressed. LDD of source / drain part
The selective epitaxial layer formed on top of the layer
Since it becomes a high concentration layer at the drain, the source
It becomes equivalent to the MOS transistor in the drain layer,
There is also an effect of suppressing deterioration of characteristics due to the short channel effect of the transistor.

[0015]

Embodiments of the present invention will be described below with reference to the accompanying drawings. The same components as those in FIG. 2 referred to in the description of the prior art are denoted by the same reference numerals.

This embodiment is an example in which the present invention is applied to a highly integrated semiconductor device including a MOS transistor as a constituent element and a method of manufacturing the same, and this will be described with reference to FIG. First, as shown in FIG. 1A, an element isolation region, for example, a trench element isolation region 12 is formed on the surface of a P-type semiconductor substrate 11 by forming a trench by RIE or the like,
CVDSi insulating film by VD method, the trenches in the method of etch-back for example after depositing a CVD SiO ₂
It is formed by burying an O ₂ film. Next, a gate oxide film 13 having a thickness of about 6 is formed on the surface of the semiconductor substrate 11 by thermal oxidation.
It is formed on the order of nm. Then, using a low pressure CVD method or the like,
Depositing a polysilicon film 14 having a thickness of about 200 nm;
After that, a high melting point metal such as C
O, and a Co film is deposited to a thickness of about 20 nm. Then, the Co film and the polysilicon film 14 are reacted by heat treatment to form a high melting point metal silicide film C.
An oSi ₂ film 15 is formed. Thereafter, an insulating film, for example, a CVD SiO ₂ film 16 having a thickness of about 200 nm is deposited by the CVD method.

Next, the CVD SiO ₂ film 16 / CoSi ₂ film 15 is formed by using the photolithography technique and the RIE method.
/ Polysilicon film 14 / gate oxide film 13 is patterned to form a polysilicon film 1 in MOS transistor portion 1.
Then, a gate electrode portion 2 having a polycide gate electrode 2a composed of the SiN 4 and the CoSi ₂ film 15 is formed. Thereafter, ion implantation, for example, using As ions, is performed on the surface of the semiconductor substrate 11 at an implantation energy of about 25 keV and a dose of about 2 keV.
The LDD layer 17 is formed by ion implantation at E13 / cm ² .

Next, as shown in FIG. 1B, an insulating film having a thickness of about 200 nm, for example, CVD SiO
After depositing the _two films, the CVD SiO ₂ film is etched back by anisotropic etching such as RIE to form a sidewall oxide film 18 on the side wall of the gate electrode portion 2. Then, the selective epitaxial layer 3 having a thickness of about 150 nm is epitaxially grown from the LDD layer 17 in the source / drain portion by using the selective epitaxial crystal growth method.
Form one. During the epitaxial growth, the selective epitaxial layer 31 grows laterally from the LDD layer 17 so as to protrude above the trench element isolation region 12, and the selective epitaxial layer 31 has a thickness of about 150 n.
At m, the width of the selective epitaxial layer 31 overhanging the trench isolation region 12 is about 100 nm.

Next, impurity ions serving as dopants are ion-implanted into the polysilicon film of the polycide gate electrode 2a and the selective epitaxial layer 31 of the source / drain portion 3 by an ion implantation method. The ion implantation conditions are, for example, using As ions, and an implantation energy of about 2
0 keV and a dose amount of about 3E15 / cm ² . After that, heat treatment for activation of the ion implanted ions,
RTA (Rapid Thermal Anneali)
ng) at a temperature of about 1000 ° C. for a time of about 10 seconds.

Next, as shown in FIG. 1C, the side wall oxide film 18 at the time of forming a self-aligned contact hole is formed.
SiN film 21 formed by CVD or the like for maintaining the shape
Is deposited to a thickness of about 50 nm, and an interlayer insulating film 22 such as a BPSG film is deposited to a thickness of about 700 nm. After that, the interlayer insulating film 22 is planarized by using a CMP method or the like, and then the interlayer insulating film 22 / SiN film 21 is etched by RIE or the like using the patterned photoresist as a mask, and the source / drain is etched. A contact hole 23 is formed in the part 3 and the like. In this case, as shown in FIG. 1 (c), the contact hole 23 is a partially self-aligned contact hole 23 only on the gate electrode portion 2 side.
It is.

Next, electrodes such as the source / drain portion 3 are formed. This electrode formation is performed first by securing the ohmic contact with the source / drain layer 19 and by forming the source / drain layer 1.
A TiSi ₂ film 20 described later is formed for lowering the resistance of 9 parts. The TiSi ₂ film 20 is formed by first forming a substantially uniform Ti film on the bottom of the fine contact hole 23 by a sputtering method using a collimator plate to a thickness of about 30 nm.
Degree formed. Thereafter, a heat treatment in a nitrogen atmosphere by the RTA method, for example, is performed at about 600 ° C. for about 60 seconds to cause the Ti film at the bottom of the contact hole 23 and the silicon of the selective epitaxial layer 31 to react with each other.
CSi-phase TiSi with low temperature stable phase and high resistance on one surface
_Two films are formed. Next, the unreacted Ti film on the side wall of the contact hole 23 and the surface of the interlayer insulating film 22 is removed with a mixed solution of sulfuric acid and hydrogen peroxide. Thereafter, a high-temperature heat treatment is performed to cause a phase transition of the C49 phase TiSi ₂ film, thereby forming a high-temperature stable phase and low-resistance C54 phase TiSi ₂ film 20.

Next, a TiN film 24 serving as a barrier film is deposited to a thickness of about 50 nm by a reactive sputtering method or the like, and a blanket W film 25 is deposited to a thickness of about 300 nm by a CVD method. Backing is performed to form a buried plug with a blanket W film 25 and a TiN film 24, a so-called tungsten plug 26, in the contact hole 23. As described above, electrodes such as the source / drain layers 19 are formed. Note that the tungsten plug 26 may be formed by a selective tungsten CVD method.

Thereafter, although not shown in the drawings, after depositing a TiN film or an Al alloy film, forming a wiring by patterning, further depositing a passivation film and the like, opening a window of a pad portion, and the like. Make the device.

In the above-described highly integrated and high-speed semiconductor device, since the selective epitaxial growth is performed from the LDD layer 17 in the source / drain portion and the selective epitaxial layer 31 overhangs the trench isolation region 12, The bottom of the contact hole 23 does not directly contact the boundary between the trench isolation region 12 and the LDD layer. Therefore, when the TiSi ₂ film 20 is formed, an abnormal portion 27 of the TiSi ₂ film 20 as shown in FIG. do not do. In addition,
Even if there is a misalignment of the pattern alignment margin ΔL, for example, about 50 nm, the selective epitaxial layer 31 overhanging the trench element isolation region 12 is about 100 nm. The Ti film does not contact the boundary of the region 12, and the TiSi ₂ film 20
No abnormal part is formed.

Therefore, in the MOS transistor section 1 of the semiconductor device of the present embodiment, like the MOS transistor section 1 of the conventional semiconductor device shown in FIG. 2C, between the contact hole 23 and the trench isolation region 12. Since it is not necessary to provide an extra interval corresponding to the pattern matching margin ΔL, the length L ₂ of the MOS transistor portion can be reduced to about (L ₁ −2ΔL), and high integration of the semiconductor device can be achieved. to enable.

The present invention has been described with reference to the embodiments.
The present invention is not limited to these examples.
For example, in the embodiments of the present invention, the device isolation region is described as a trench device isolation region, but may be a LOCOS device isolation region. In the embodiment of the present invention, a polysilicon film and a CoS
Although the description has been made using the polycide gate electrode made of the i ₂ film, a polycide gate electrode made of a polysilicon film and a TiSi ₂ film, a PtSi ₂ film, or another refractory metal silicide film may be used. In the embodiment of the present invention, the TiSi ₂ film is used for the ohmic property between the selective epitaxial layer of the source / drain portion and the tungsten plug and for reducing the resistance of the selective epitaxial layer.
A Si ₂ film, a PtSi ₂ film, or another refractory metal silicide film may be used. In addition, the manufacturing apparatus and the process conditions in the manufacturing process of the semiconductor device can be appropriately changed without departing from the technical idea of the present invention.

[0027]

As is apparent from the above description, a highly integrated semiconductor device including the MOS transistor of the present invention as a constituent element performs selective epitaxial crystal growth from the LDD layer of the source / drain portion, and performs element isolation. A protruding selective epitaxial layer is formed above the region, and a contact hole and an electrode are formed in the selective epitaxial layer to produce a highly integrated semiconductor device without an increase in source / drain junction leakage current. it can.
Further, since the selective epitaxial layer formed above the LDD layer in the source / drain portion becomes a high concentration layer in the source / drain portion, the MOS of the source / drain layer having a shallow junction is formed.
This is equivalent to a transistor, and has an effect of suppressing deterioration of characteristics due to a short channel effect of a MOS transistor.

[Brief description of the drawings]

FIGS. 1A and 1B are schematic cross-sectional views of a semiconductor device, illustrating the steps of an embodiment to which the present invention is applied in the order of steps. FIG. 1A shows a state in which a gate electrode portion is formed and an LDD layer is formed, and FIG. A state in which an epitaxial layer is formed, ions are implanted into the selective epitaxial layer and the polysilicon film in the gate electrode portion, and a heat treatment for activation is performed, and (c) is a state in which a tungsten plug is formed in a contact hole.

FIGS. 2A and 2B are schematic cross-sectional views of a semiconductor device illustrating a conventional method of manufacturing a semiconductor device in the order of steps. FIG. 2A shows a state in which a gate electrode portion is formed and an LDD layer is formed, and FIG. A state in which a film is formed and a source / drain layer is formed by ion implantation, and (c) is a state in which a tungsten plug is formed in a contact hole.

FIG. 3 is a schematic cross-sectional view of a semiconductor device for explaining a problem in a case where a bottom of a contact hole contacts a peripheral portion of a trench element isolation region in a conventional semiconductor device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... MOS transistor part, 2 ... gate electrode part, 2a ...
Polycide gate electrode, 3 source / drain portion, 11
... Semiconductor substrate, 12 ... Trench element isolation region, 13 ... Gate oxide film, 14 ... Polysilicon film, 15 ... CoSi ₂
Film, 16: CVD SiO ₂ film, 17: LDD layer, 18:
Side wall oxide film, 19: source / drain layer, 2
0: TiSi ₂ film, 21: SiN film, 22: interlayer insulating film, 23: contact hole, 24: TiN film, 25:
Blanket W film, 26 ... tungsten plug, 27 ...
Abnormal part, 31 ... Selective epitaxial layer

Claims (4)

[Claims] 1. A highly integrated semiconductor device including a MOS transistor as a constituent element, wherein an LDD of a source / drain portion of the MOS transistor is provided.
A semiconductor device comprising a selective epitaxial layer extending a predetermined width from a layer above an element isolation region adjacent to the LDD layer. 2. The semiconductor device according to claim 1, wherein said predetermined width is substantially equal to a dimension of pattern alignment accuracy. 3. A method for manufacturing a highly integrated semiconductor device including a MOS transistor as a constituent element, wherein: a step of forming an element isolation region in a semiconductor substrate; a step of forming a gate electrode portion of the MOS transistor; Forming an LDD layer in a source / drain portion of a MOS transistor by an ion implantation method; forming a sidewall insulating film on a side wall of the gate electrode portion; and forming the source / drain portion in a selective epitaxial crystal growth method. A step of forming a selective epitaxial layer from the LDD layer, a step of implanting ions into the selective epitaxial layer by an ion implantation method to reduce the resistance of the selective epitaxial layer, and a step of depositing an interlayer insulating film. Forming a contact hole in the interlayer insulating film, and forming a contact hole in the contact hole portion; The method of manufacturing a semiconductor device characterized by a step of forming an electrode to be connected to the selective epitaxial layer. 4. The method according to claim 1, wherein the selective epitaxial layer is formed of the LD.
Selective epitaxial crystal growth from the D layer;
The method according to claim 1, further comprising: extending the selective epitaxial layer on the element isolation region adjacent to the D layer, and performing selective epitaxial crystal growth until the selective epitaxial layer on the element isolation region has a predetermined width. Item 4. The method for manufacturing a semiconductor device according to Item 3.