JPH10163254A - Circuit board - Google Patents
Circuit boardInfo
- Publication number
- JPH10163254A JPH10163254A JP32298496A JP32298496A JPH10163254A JP H10163254 A JPH10163254 A JP H10163254A JP 32298496 A JP32298496 A JP 32298496A JP 32298496 A JP32298496 A JP 32298496A JP H10163254 A JPH10163254 A JP H10163254A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- electronic component
- mounting
- adhesive
- mounting board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0313—Organic insulating material
- H05K1/0353—Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement
- H05K1/0366—Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement reinforced, e.g. by fibres, fabrics
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/321—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、例えばフェイスダ
ウンボンディング方式により半導体チップ等の電子部品
を実装基板と異方導電性接着剤等の接着剤で接着固定す
ると共に、両者の電極同士を電気的に接続する回路板に
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to, for example, an electronic component such as a semiconductor chip, which is bonded and fixed to a mounting board with an adhesive such as an anisotropic conductive adhesive by a face-down bonding method, and electrically connects both electrodes. To a circuit board to be connected.
【０００２】[0002]
【従来の技術】一般に、半導体チップをフェイスダウン
ボンディング方式により直接基板に実装する方法とし
て、半導体チップの電極部分にはんだバンプを形成し実
装基板にはんだ接続するフリップチップ方式、半導体チ
ップに設けた突起電極に導電性接着剤を塗布し実装基板
電極に接着する接続方法が用いられている。2. Description of the Related Art In general, as a method of directly mounting a semiconductor chip on a substrate by a face-down bonding method, a flip chip method in which solder bumps are formed on electrode portions of the semiconductor chip and soldered to a mounting substrate, projections provided on the semiconductor chip. A connection method is used in which a conductive adhesive is applied to the electrodes and the electrodes are bonded to the mounting substrate electrodes.
【０００３】また、半導体チップ、トランジスタ、ダイ
オ−ド、サイリスタ等の能動素子、コンデンサ、抵抗
体、コイル等の受動素子等の電子部品と実装基板とを機
械的な電極接続により電気的に接続する方法として、接
着剤または導電粒子を分散させた異方導電性接着剤があ
る。すなわち、接着フィルムを電子部品と電極や回路の
間に設け、加圧または加熱加圧手段を構じることによっ
て、両者の電極同士が電気的に接続されると共に、隣接
電極間の絶縁性を付与して、電子部品と回路とが接着固
定されるものである。この機械的な電極接続による実装
方法は、現在ガラス基板で適用されているほか、汎用性
の高いガラスクロス補強樹脂製の配線板に適用する検討
が進められている。Also, electronic components such as active elements such as semiconductor chips, transistors, diodes and thyristors, and passive elements such as capacitors, resistors and coils are electrically connected to a mounting board by mechanical electrode connection. As a method, there is an adhesive or an anisotropic conductive adhesive in which conductive particles are dispersed. That is, by providing an adhesive film between an electronic component and an electrode or a circuit and forming a pressurizing or heating pressurizing means, both electrodes are electrically connected to each other, and at the same time, insulation between adjacent electrodes is improved. In addition, the electronic component and the circuit are bonded and fixed. This mounting method by mechanical electrode connection is currently applied to a glass substrate, and studies are being made to apply it to a wiring board made of glass cloth reinforced resin having high versatility.
【０００４】[0004]
【発明が解決しようとする課題】このガラスクロス補強
樹脂製の配線板は、配線密度に優れ、かつ経済的に多層
配線化でき、配線板材料としてもっとも一般的に利用さ
れている。しかし、従来のＦＲ−４グレードのガラスク
ロス補強樹脂製配線板では、Ｘ及びＹ方向の線膨張率が
大きく、半導体チップ実装時の加熱加圧による基板の膨
張から、実装後の室温への冷却による基板の収縮によっ
て接続部材に反りが生じ、接続信頼性を低下するという
問題があった。本発明は、導電粒子を分散させた異方導
電性接着剤等の接着剤により、半導体チップや電子部品
と実装基板とを機械的な電極接続で電気的な接続を得る
ことに際し、上記問題点に鑑みてなされたもので、半導
体チップをガラスクロス補強樹脂製配線板による実装基
板に接続でき、長期接続信頼性に優れた回路板を提供す
るものである。The wiring board made of the glass cloth reinforced resin is excellent in wiring density and can be economically formed into a multilayer wiring, and is most commonly used as a wiring board material. However, the conventional FR-4 grade glass cloth reinforced resin wiring board has a large coefficient of linear expansion in the X and Y directions, and the board expands due to heating and pressing during mounting of the semiconductor chip, and then cools down to room temperature after mounting. As a result, the connection member is warped due to the shrinkage of the substrate, and the connection reliability is reduced. The present invention is directed to obtaining an electrical connection between a semiconductor chip or an electronic component and a mounting board by mechanical electrode connection using an adhesive such as an anisotropic conductive adhesive in which conductive particles are dispersed. It is an object of the present invention to provide a circuit board which can connect a semiconductor chip to a mounting board formed of a wiring board made of glass cloth reinforced resin and has excellent long-term connection reliability.
【０００５】[0005]
【課題を解決するための手段】本発明の回路板は、実装
基板表面の配線の所定の領域に電子部品の接続電極に対
応して形成された接続用電極端子上に前記電子部品の接
続電極が対応するように前記電子部品を当接載置し、前
記電子部品の前記接続電極形成面側が接着剤を介して前
記実装基板表面に接着固定され、前記接続用電極端子と
前記電子部品の接続電極とが電気的に接続される回路板
であって、前記実装基板は複数層の導体配線層が絶縁層
を介して積層接着された多層配線板であり、前記絶縁層
の少なくとも前記電子部品が接着固定される側の最外層
の１層がガラス基材で補強された樹脂よりなりＸ及びＹ
方向の線膨張率が１３ｐｐｍ／℃以下の絶縁層であるこ
とを特徴とする。According to the present invention, there is provided a circuit board comprising a connection electrode of an electronic component on a connection electrode terminal formed in a predetermined region of a wiring on a surface of a mounting board so as to correspond to the connection electrode of the electronic component. The electronic component is abutted and mounted so that the connection electrode forming surface side of the electronic component is adhered and fixed to the mounting substrate surface via an adhesive, and the connection between the connection electrode terminal and the electronic component is performed. A circuit board electrically connected to electrodes, wherein the mounting board is a multilayer wiring board in which a plurality of conductive wiring layers are laminated and bonded via an insulating layer, and at least the electronic component of the insulating layer is One of the outermost layers on the side to be bonded and fixed is made of a resin reinforced with a glass base material.
The insulating layer has a coefficient of linear expansion in the direction of 13 ppm / ° C. or less.
【０００６】[0006]
【発明の実施の形態】本発明における半導体チップと実
装基板の接続を図１を用いて説明する。図１において半
導体チップ１に設けた接続電極である突起電極（バン
プ）３は、実装基板２表面に設けた導体回路のチップ搭
載用電極４と位置合わせされる。導電粒子を分散させた
異方導電性接着剤１０は、半導体チップ１と実装基板２
間に配置される。この状態から半導体チップ１側から加
圧加熱することにより接着剤１０は流動し、接着剤の場
合は、半導体チップに設けた接続電極と実装基板表面に
設けた導体回路のチップ搭載用電極が直接機械的に接し
電気的な接続を得る。１１は導電粒子である。DESCRIPTION OF THE PREFERRED EMBODIMENTS The connection between a semiconductor chip and a mounting board according to the present invention will be described with reference to FIG. In FIG. 1, a bump electrode (bump) 3 serving as a connection electrode provided on a semiconductor chip 1 is aligned with a chip mounting electrode 4 of a conductor circuit provided on the surface of a mounting substrate 2. The anisotropic conductive adhesive 10 in which conductive particles are dispersed includes the semiconductor chip 1 and the mounting substrate 2.
Placed between. In this state, the adhesive 10 flows by applying pressure and heating from the semiconductor chip 1 side. In the case of the adhesive, the connection electrodes provided on the semiconductor chip and the chip mounting electrodes of the conductor circuits provided on the surface of the mounting board are directly connected. Mechanical contact and electrical connection. Reference numeral 11 denotes conductive particles.
【０００７】本発明における実装基板の導体配線層は、
２層以上必要で高密度化をはかるためには３層またはそ
れ以上が望ましい。導体配線層は既存の銅箔をエッチィ
ング法で回路形成したもの等任意の回路形成法が使用で
きる。複数の導体配線層は絶縁層で絶縁され、この絶縁
層の少なくとも半導体チップが接着固定される側の最外
層の１層はガラス基材で補強された樹脂よりなりＸ及び
Ｙ方向の線膨張率が室温で１３ｐｐｍ／℃以下の絶縁層
を使用する必要がある。導体配線の表面には、錫（Ｓ
ｎ）、金（Ａｕ）、ニッケル（Ｎｉ）、はんだ等のめっ
き等による表面層を形成することもできる。本発明の実
装基板は、複数層の導体配線層が絶縁層を介して積層接
着され、所定の導体配線層間を導体化された穴で電気的
に接続してなる多層配線板も使用される。In the present invention, the conductor wiring layer of the mounting board is
Two or more layers are required, and three or more layers are desirable in order to increase the density. For the conductor wiring layer, any circuit forming method such as a circuit formed by etching an existing copper foil by an etching method can be used. The plurality of conductor wiring layers are insulated by an insulating layer, and at least one outermost layer of the insulating layer on the side to which the semiconductor chip is bonded and fixed is made of a resin reinforced with a glass base material, and has a linear expansion coefficient in the X and Y directions. However, it is necessary to use an insulating layer of 13 ppm / ° C. or less at room temperature. On the surface of the conductor wiring, tin (S
n), a surface layer can be formed by plating of gold (Au), nickel (Ni), solder, or the like. The mounting board of the present invention also uses a multilayer wiring board in which a plurality of conductive wiring layers are laminated and bonded via an insulating layer, and predetermined conductive wiring layers are electrically connected to each other through conductive holes.
【０００８】本発明における接着剤は、チップと基板の
熱膨張係数の違いに基づく応力を緩和する目的で接着後
の４０℃での弾性率が１００〜４０００ＭＰａが好まし
く、特に１００〜１５００ＭＰａであれば特に好まし
い。例えば、接着剤として、エポキシ樹脂とイミダゾー
ル系、ヒドラジド系、三フッ化ホウ素−アミン錯体、ス
ルホニウム塩、アミンイミド、ポリアミンの塩、ジシア
ンジアミド等の潜在性硬化剤の混合物に、接着後の４０
℃での弾性率が１００〜１５００ＭＰａになるようにア
クリルゴムを配合した接着剤があげられる。接着剤硬化
物の弾性率は、例えば、レオロジ（株）製レオスペクト
ラＤＶＥ−４（引っぱりモード、周波数１０Ｈｚ、５℃
／ｍｉｎで昇温）を使用して測定できる。The adhesive in the present invention preferably has an elastic modulus at 40 ° C. of 100 to 4000 MPa after bonding for the purpose of relieving the stress based on the difference in the thermal expansion coefficient between the chip and the substrate, especially if it is 100 to 1500 MPa. Particularly preferred. For example, as an adhesive, a mixture of an epoxy resin and a latent curing agent such as an imidazole type, a hydrazide type, a boron trifluoride-amine complex, a sulfonium salt, an amine imide, a polyamine salt, dicyandiamide, etc.
An adhesive compounded with an acrylic rubber so that the elastic modulus at 100 ° C. is 100 to 1500 MPa can be used. The elastic modulus of the cured adhesive is, for example, Rheological Co., Ltd. Rheospectra DVE-4 (pulling mode, frequency 10 Hz, 5 ° C.)
/ Min).
【０００９】本発明で用いるアクリルゴムとしては、ア
クリル酸、アクリル酸エステル、メタクリル酸エステル
またはアクリロニトリルのうち少なくともひとつをモノ
マー成分とした重合体または共重合体があげられ、中で
もグリシジルエーテル基を含有するグリシジルアクリレ
ートやグリシジルメタクリレートを含む共重合体系アク
リルゴムが好適に用いられる。これらアクリルゴムの分
子量は、接着剤の凝集力を高める点から２０万以上が好
ましい。アクリルゴムの接着剤中の配合量は、１５ｗｔ
％以下であると接着後の４０℃での弾性率が１５００Ｍ
Ｐａを越えてしまい、また４０ｗｔ％以上になると低弾
性率化は図れるが接続時の溶融粘度が高くなり接続電極
界間、または接続電極と導電粒子界面の溶融接着剤の排
除性が低下するため、接続電極間または接続電極と導電
粒子間の電気的導通を確保できなくなる。このため、ア
クリル配合量としては１５〜４０ｗｔ％が好ましい。接
着剤に配合されたこれらのアクリルゴムは、ゴム成分に
起因する誘電正接のピーク温度が４０〜６０℃付近にあ
るため、接着剤の低弾性率化を図ることができる。The acrylic rubber used in the present invention is a polymer or copolymer containing at least one of acrylic acid, acrylic acid ester, methacrylic acid ester and acrylonitrile as a monomer component. Among them, it contains a glycidyl ether group. A copolymer acrylic rubber containing glycidyl acrylate or glycidyl methacrylate is preferably used. The molecular weight of these acrylic rubbers is preferably 200,000 or more from the viewpoint of increasing the cohesive strength of the adhesive. The amount of acrylic rubber in the adhesive is 15 wt.
% Or less, the elastic modulus at 40 ° C. after bonding is 1500M.
If it exceeds Pa, and if it exceeds 40 wt%, the modulus of elasticity can be reduced, but the melt viscosity at the time of connection increases, and the removability of the molten adhesive between the connection electrode boundaries or at the interface between the connection electrode and the conductive particles decreases. As a result, it becomes impossible to secure electrical continuity between the connection electrodes or between the connection electrodes and the conductive particles. Therefore, the acrylic compounding amount is preferably 15 to 40% by weight. These acrylic rubbers compounded in the adhesive have a peak temperature of dielectric loss tangent due to the rubber component in the vicinity of 40 to 60 ° C., so that the elastic modulus of the adhesive can be reduced.
【００１０】本発明に用いられる接着剤には、チップの
バンプや回路電極の高さばらつきを吸収するために、異
方導電性を積極的に付与する目的で導電粒子を分散する
こともできる。本発明において導電粒子は例えばＡｕ、
Ｎｉ、Ａｇ、Ｃｕ、Ｗやはんだなどの金属粒子またはこ
れらの金属粒子表面に金やパラジウムなどの薄膜をめっ
きや蒸着によって形成した金属粒子であり、ポリスチレ
ン等の高分子の球状の核材にＮｉ、Ｃｕ、Ａｕ、はんだ
等の導電層を設けた導電粒子を用いることができる。In the adhesive used in the present invention, conductive particles can be dispersed for the purpose of positively imparting anisotropic conductivity in order to absorb height variations of chip bumps and circuit electrodes. In the present invention, the conductive particles are, for example, Au,
Metal particles such as Ni, Ag, Cu, W and solder, or metal particles formed by plating or depositing a thin film of gold or palladium on the surface of these metal particles. , Cu, Au, a conductive particle provided with a conductive layer of solder or the like can be used.
【００１１】粒径は基板の電極の最小の間隔よりも小さ
いことが必要で、電極の高さばらつきがある場合、高さ
ばらつきよりも大きいことが好ましく、１μｍ〜１０μ
ｍが好ましい。また、接着剤に分散される導電粒子量
は、０．１〜３０体積％であり、好ましくは０．２〜１
５体積％である。It is necessary that the particle size is smaller than the minimum distance between the electrodes of the substrate, and if there is a variation in the height of the electrodes, it is preferably larger than the variation in the height.
m is preferred. The amount of the conductive particles dispersed in the adhesive is 0.1 to 30% by volume, preferably 0.2 to 1%.
5% by volume.
【００１２】本発明における半導体チップの接続電極に
は、金、ニッケル、ハンダ等をめっきし突起電極とした
めっきバンプ、また 金、アルミニウム等の金属ワイヤ
の先端を熱エネルギによりボール状としこのボールを接
続端子が構成される半導体チップの電極パッド上に圧着
した後前記金属ワイヤを切断して構成された突起電極で
あるボールバンプ、はんだボール、溶融はんだ成形バン
プ、カラムの半田付け等による突起電極が使用できる。
本発明の電子部品としては、半導体チップ、トランジス
タ、ダイオ−ド、サイリスタ等の能動素子、コンデン
サ、抵抗体、コイル等の受動素子が使用される。The connection electrodes of the semiconductor chip according to the present invention are plated bumps formed by plating gold, nickel, solder, or the like, or the tips of metal wires, such as gold and aluminum, are formed into a ball shape by thermal energy. The bump electrodes formed by cutting the metal wire after being pressed onto the electrode pads of the semiconductor chip on which the connection terminals are formed are ball bumps, solder balls, molten solder molding bumps, and bump electrodes formed by column soldering. Can be used.
As the electronic component of the present invention, an active element such as a semiconductor chip, a transistor, a diode, and a thyristor, and a passive element such as a capacitor, a resistor, and a coil are used.
【００１３】[0013]
【作用】一般のガラスエポキシ基材（ＦＲ−４グレー
ド）はＸ及びＹ方向の線膨張率が１６ｐｐｍ／℃である
のに対し、本発明における実装基板には線膨張率１３ｐ
ｐｍ／℃以下のガラスクロス補強樹脂製の絶縁層等のガ
ラス基材で補強された樹脂よりなる絶縁層を用いるた
め、半導体チップ等の電子部品との接続部分に生じる内
部応力を小さくできる。同時に、本発明における接着剤
は、好ましくは４０℃での弾性率が１００〜１５００Ｍ
Ｐａのため、熱衝撃試験、ＰＣＴ試験やはんだバス浸漬
試験などの信頼性試験において生じる内部応力を接着剤
で吸収できるため、信頼性試験後においても接続部での
接続抵抗の増大や接着剤の剥離がなく、接続信頼性が大
幅に向上する。The general glass epoxy base material (FR-4 grade) has a linear expansion coefficient of 16 ppm / ° C. in the X and Y directions, while the mounting substrate of the present invention has a linear expansion coefficient of 13 p.
Since an insulating layer made of a resin reinforced with a glass base such as an insulating layer made of a glass cloth reinforced resin having a temperature of pm / ° C. or less is used, internal stress generated at a connection portion with an electronic component such as a semiconductor chip can be reduced. At the same time, the adhesive of the present invention preferably has an elastic modulus at 40 ° C of 100 to 1500M.
Since the internal stress generated in reliability tests such as thermal shock test, PCT test and solder bath immersion test can be absorbed by the adhesive because of Pa, even after the reliability test, the connection resistance at the connection part increases and the adhesive There is no peeling, and connection reliability is greatly improved.
【００１４】[0014]
実施例 Ｘ及びＹ方向の線膨張率が１１ｐｐｍ／℃のガラスクロ
ス・エポキシ樹脂両面銅張り積層板であるＭＣＬ−Ｅ−
６７９ＬＤ（日立化成工業株式会社製、商品名）の表面
銅箔を既存のエッチィング法で半導体チップ搭載用配線
を加工し、表面にニッケル／金めっきを施し実装基板を
得た。半導体チップの接続電極として金めっきにより突
起電極を形成したものを用いた。この後、半導体チップ
の突起電極と実装基板とを接着後の４０℃における弾性
率が１，２００ＭＰａの異方導電フィルムにより接続す
る。まず、実装基板に異方導電フィルムを転写した後、
半導体チップの突起電極と実装基板の半導体チップ搭載
用回路との位置合せを行い、半導体チップを１８０℃、
１０ｋｇｆ／チップの温度及び圧力により２０秒間加熱
圧着して異方導電フィルムを硬化させる。これによっ
て、異方導電フィルムを介して半導体チップの突起電極
と実装基板の半導体チップ搭載用回路とを電気的に接続
されると同時に半導体チップと実装基板間は異方導電フ
ィルムの接着剤の硬化によって、この接続状態を保持す
る。このようにして得た半導体チップと実装基板を接続
した部材を（−５５℃、３０分）／（１２５℃、３０
分）の条件で繰り返す冷熱サイクル試験に曝した。この
冷熱サイクル試験１，０００回後の半導体チップの突起
電極と実装基板の半導体チップ搭載用回路の接続抵抗を
測定したところ５０ｍΩ以下であった。また実装後の半
導体チップのソリは５μｍであった。Example MCL-E- is a glass-cloth / epoxy resin double-sided copper-clad laminate having a linear expansion coefficient of 11 ppm / ° C. in the X and Y directions.
The surface copper foil of 679LD (trade name, manufactured by Hitachi Chemical Co., Ltd.) was processed into a wiring for mounting a semiconductor chip by an existing etching method, and the surface was plated with nickel / gold to obtain a mounting substrate. As the connection electrode of the semiconductor chip, one having a protruding electrode formed by gold plating was used. Thereafter, the bump electrode of the semiconductor chip and the mounting substrate are connected by an anisotropic conductive film having an elastic modulus of 1,200 MPa at 40 ° C. after bonding. First, after transferring the anisotropic conductive film to the mounting board,
Align the protruding electrode of the semiconductor chip with the circuit for mounting the semiconductor chip on the mounting board, and set the semiconductor chip at 180 ° C.
The anisotropic conductive film is cured by applying heat and pressure at a temperature and pressure of 10 kgf / chip for 20 seconds. As a result, the protruding electrodes of the semiconductor chip and the circuit for mounting the semiconductor chip on the mounting board are electrically connected via the anisotropic conductive film, and at the same time, the adhesive of the anisotropic conductive film is cured between the semiconductor chip and the mounting board. Holds this connection state. The member obtained by connecting the semiconductor chip and the mounting board obtained in this way is (−55 ° C., 30 minutes) / (125 ° C., 30 minutes).
Min) under the repeated thermal cycle test. The connection resistance between the protruding electrode of the semiconductor chip and the circuit for mounting the semiconductor chip on the mounting board after 1,000 cycles of the cooling / heating cycle test was 50 mΩ or less. The warpage of the semiconductor chip after mounting was 5 μm.
【００１５】比較例 実施例において、ガラスクロス・エポキシ樹脂両面銅張
り積層板であるＭＣＬ−Ｅ−６７９ＬＤ（日立化成工業
株式会社製、商品名）に代えて、Ｘ及びＹ方向の線膨張
率が１６ｐｐｍ／℃のガラスクロス・エポキシ樹脂両面
銅張り積層板であるＭＣＬ−Ｅ−６７（日立化成工業株
式会社製、商品名）を用いた外は、実施例と同様にして
半導体チップと実装基板を接続した。このようにして得
た半導体チップと実装基板を接続した部材を（−５５
℃、３０分）／（１２５℃、３０分）の条件で繰り返す
冷熱サイクル試験に曝した。この冷熱サイクル試験１，
０００回後の半導体チップの突起電極と実装基板の半導
体チップ搭載用回路の接続抵抗を測定したところ１Ω以
上であった。また実装後の半導体チップのソリは１８μ
ｍであった。COMPARATIVE EXAMPLE In the examples, instead of MCL-E-679LD (trade name, manufactured by Hitachi Chemical Co., Ltd.), which is a glass cloth / epoxy resin double-sided copper-clad laminate, the coefficient of linear expansion in the X and Y directions was changed. Except for using MCL-E-67 (trade name, manufactured by Hitachi Chemical Co., Ltd.) which is a glass cloth / epoxy resin double-sided copper-clad laminate of 16 ppm / ° C., a semiconductor chip and a mounting board were formed in the same manner as in the example. Connected. The member connecting the semiconductor chip thus obtained and the mounting board is referred to as (-55
(30 ° C., 30 minutes) / (125 ° C., 30 minutes). This thermal cycle test 1,
After 000 times, the connection resistance between the protruding electrode of the semiconductor chip and the circuit for mounting the semiconductor chip on the mounting board was measured and found to be 1 Ω or more. The warpage of the semiconductor chip after mounting is 18μ.
m.
【００１６】[0016]
【発明の効果】本発明により、半導体チップ等の電子部
品と実装基板との接続信頼性に優れる回路板を得ること
ができる。According to the present invention, it is possible to obtain a circuit board having excellent connection reliability between an electronic component such as a semiconductor chip and a mounting board.
【図１】 本発明の回路板の断面図である。FIG. 1 is a sectional view of a circuit board of the present invention.
１： 半導体チップ ２： 実装基板 ３： 突起電極（バンプ） ４： チップ搭載用電極 １０：異方導電性接着剤 １１：導電粒子 1: semiconductor chip 2: mounting substrate 3: protruding electrode (bump) 4: chip mounting electrode 10: anisotropic conductive adhesive 11: conductive particle
───────────────────────────────────────────────────── フロントページの続き (72)発明者 渡辺 治 茨城県つくば市和台48 日立化成工業株式 会社筑波開発研究所内 (72)発明者 小島 和良 茨城県つくば市和台48 日立化成工業株式 会社筑波開発研究所内 ──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Osamu Watanabe 48 Wadai, Tsukuba, Ibaraki Prefecture Within Hitachi Chemical Co., Ltd.Tsukuba Development Laboratory Co., Ltd. (72) Inventor Kazuyoshi Kojima 48 Wadai, Tsukuba City, Ibaraki Prefecture Hitachi Chemical Co., Ltd. Inside the development laboratory
Claims (5)
部品の接続電極に対応して形成された接続用電極端子上
に前記電子部品の接続電極が対応するように前記電子部
品を当接載置し、前記電子部品の前記接続電極形成面側
が接着剤を介して前記実装基板表面に接着固定され、前
記接続用電極端子と前記電子部品の接続電極とが電気的
に接続される回路板であって、前記実装基板は複数層の
導体配線層が絶縁層を介して積層接着された多層配線板
であり、前記絶縁層の少なくとも前記電子部品が接着固
定される側の最外層の１層がガラス基材で補強された樹
脂よりなりＸ及びＹ方向の線膨張率が１３ｐｐｍ／℃以
下の絶縁層であることを特徴とする回路板。An electronic component is abutted on a connection electrode terminal formed in a predetermined region of a wiring on a surface of a mounting board so as to correspond to the connection electrode of the electronic component so that the connection electrode of the electronic component corresponds to the connection electrode terminal. A circuit board on which the connection electrode forming surface side of the electronic component is mounted and fixed to the mounting substrate surface via an adhesive, and the connection electrode terminal and the connection electrode of the electronic component are electrically connected. Wherein the mounting board is a multilayer wiring board in which a plurality of conductive wiring layers are laminated and bonded via an insulating layer, and one of the outermost layers of the insulating layer on which at least the electronic component is bonded and fixed. A circuit board comprising a resin reinforced with a glass substrate and having a coefficient of linear expansion in the X and Y directions of 13 ppm / ° C. or less.
接着剤が、接着後の４０℃における弾性率が１００〜
１，５００ＭＰａである請求項１記載の回路板。2. An adhesive for bonding and fixing an electronic component to a surface of a mounting board has an elastic modulus at 40 ° C. of 100 to 100 after bonding.
2. The circuit board according to claim 1, wherein the pressure is 1,500 MPa.
接着剤が、異方導電性接着剤である請求項１又は２記載
の回路板。3. The circuit board according to claim 1, wherein the adhesive for bonding and fixing the electronic component to the surface of the mounting board is an anisotropic conductive adhesive.
着剤を介して実装基板表面に接着固定される請求項１〜
３各項記載の回路板。4. The whole surface of the electronic component on the connection electrode forming surface side is adhered and fixed to the surface of the mounting board via an adhesive.
3. The circuit board according to any one of the above items.
１〜４各項記載の回路板。5. The circuit board according to claim 1, wherein the electronic component is a semiconductor chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32298496A JPH10163254A (en) | 1996-12-03 | 1996-12-03 | Circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32298496A JPH10163254A (en) | 1996-12-03 | 1996-12-03 | Circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH10163254A true JPH10163254A (en) | 1998-06-19 |
Family
ID=18149852
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP32298496A Pending JPH10163254A (en) | 1996-12-03 | 1996-12-03 | Circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH10163254A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2000009623A1 (en) * | 1998-08-13 | 2000-02-24 | Hitachi Chemical Company, Ltd. | Adhesive for bonding circuit members, circuit board, and method of producing the same |
| EP1454973A1 (en) * | 1998-08-13 | 2004-09-08 | Hitachi Chemical Co., Ltd. | Adhesive for bonding circuit members, circuit board and process for its production |
| KR100832283B1 (en) * | 2000-03-15 | 2008-05-26 | 소니 케미카루 앤드 인포메이션 디바이스 가부시키가이샤 | Anisotropically electroconductive connecting material |
| US7750310B2 (en) | 2005-08-16 | 2010-07-06 | Hitachi, Ltd. | Semiconductor radioactive ray detector, radioactive ray detection module, and nuclear medicine diagnosis apparatus |
| JP4930598B2 (en) * | 2007-10-18 | 2012-05-16 | 日立化成工業株式会社 | Circuit connection material, circuit connection body and circuit member connection method |
-
1996
- 1996-12-03 JP JP32298496A patent/JPH10163254A/en active Pending
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8273458B2 (en) | 1997-02-14 | 2012-09-25 | Hitachi Chemical Company, Ltd. | Adhesive for bonding circuit members, circuit board and process for its production |
| WO2000009623A1 (en) * | 1998-08-13 | 2000-02-24 | Hitachi Chemical Company, Ltd. | Adhesive for bonding circuit members, circuit board, and method of producing the same |
| EP1454973A1 (en) * | 1998-08-13 | 2004-09-08 | Hitachi Chemical Co., Ltd. | Adhesive for bonding circuit members, circuit board and process for its production |
| US7247381B1 (en) | 1998-08-13 | 2007-07-24 | Hitachi Chemical Company, Ltd. | Adhesive for bonding circuit members, circuit board, and method of producing the same |
| US7879445B2 (en) | 1998-08-13 | 2011-02-01 | Hitachi Chemical Company, Ltd. | Adhesive for bonding circuit members, circuit board and process for its production |
| US8252419B2 (en) | 1998-08-13 | 2012-08-28 | Hitachi Chemical Company, Ltd. | Adhesive for bonding circuit members, circuit board and process for its production |
| US8273457B2 (en) | 1998-08-13 | 2012-09-25 | Hitachi Chemical Company, Ltd. | Adhesive for bonding circuit members, circuit board and process for its production |
| KR100832283B1 (en) * | 2000-03-15 | 2008-05-26 | 소니 케미카루 앤드 인포메이션 디바이스 가부시키가이샤 | Anisotropically electroconductive connecting material |
| US7750310B2 (en) | 2005-08-16 | 2010-07-06 | Hitachi, Ltd. | Semiconductor radioactive ray detector, radioactive ray detection module, and nuclear medicine diagnosis apparatus |
| JP4930598B2 (en) * | 2007-10-18 | 2012-05-16 | 日立化成工業株式会社 | Circuit connection material, circuit connection body and circuit member connection method |
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