JPH10163226A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent deterioration of high frequency characteristics of an element which is caused by decrease in average velocity of electrons, by restraining the Γ-L transition of electrons in a channel. SOLUTION: In a semiconductor device provided with a buffer layer 11, a channel layer 12, an electrode layer, and electrodes of a gate, a source and a drain, a region A where the change in potential or electronegativity or conduction band level or valence electron level along the current conduction direction in the channels is made larger than the other parts is formed in at least a part of the channel layer 12 between the part just under a gate electrode 22 and a drain electrode layer 21 or a source electrode layer 23.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-speed semiconductor device used in high-frequency circuits, information communication systems, optical transmission systems and the like.

[0002]

2. Description of the Related Art In the field of information communication, with the rapid market expansion of satellite communication systems and portable information communication systems, the demand for high-frequency devices has been increasing year by year.
Various high-frequency devices having a cut-off frequency exceeding 100 GHz have been reported. In addition, as device miniaturization progresses, many field effect transistors having a gate width of 100 nm or less have been reported at the research level.

[0003] In the above-mentioned fine element, further speedup can be expected due to the ballistic transport phenomenon that the electron drift speed exceeds the saturation speed. Research on new devices utilizing such a ballistic transport phenomenon has been actively conducted, and using a vertical bipolar transistor as a prototype, a BCT (Balistic Collection Transistor) [American Electrical and Electronic Engineers Association Transaction on Electron device, 3
Vol. 5, No. 4, p. 401, 1988], CT (Coherent Transistor) [American Institute of Electrical and Electronics Engineers, Transaction on Electron Device, 40]
Vol. 8, page 1512, 1993].

On the other hand, a horizontal element such as a field-effect transistor has a stronger restriction on fine processing dimensions than a vertical element. For example, while using a molecular beam epitaxy method (MBE), the vertical structure can be controlled on the order of several nanometers, while the gate width on the horizontal structure is on the order of tens of nanometers. Is not easy. For this reason, the horizontal element has a longer electron traveling distance in the active region than the vertical element.

[0005]

When the source and drain lengths are large to some extent, electrons are scattered by phonons and the like, and some of them are shifted to L band and X band having a large state density. Since the electrons that have transitioned to the L band and the X band have an effective mass several tens of times that in the Γ band, the average velocity of the electrons is greatly reduced, and the high frequency characteristics of the device are reduced. Therefore, the Γ-
Suppressing the L transition is an issue necessary for improving the device characteristics.

[0006]

SUMMARY OF THE INVENTION In a semiconductor device having at least a buffer layer, a channel layer, an electrode layer, and gate, source and drain electrodes on a semiconductor substrate, a portion immediately below a gate electrode of the channel layer and a drain or source The problem is solved by providing at least a portion between the electrode layers with a change in the potential or electronegativity or the conduction band or valence band level along the direction of current conduction in the channel, which is larger than other portions.

[0007]

FIG. 1 shows a MESF according to the invention.
The structure of ET (metal-semiconductor field effect transistor)
FIG. 6 shows a conventional structure. Here, the description will be made assuming the case of an n-channel using GaAs as a semiconductor material.

In the region 1 of FIG. 1, for example, 1 × 1 p-type impurity is implanted into the left end of the region by focused ion beam implantation (FIB).
It is formed by introducing 0 ¹⁸ / cm ³ . 4 and 5 are band diagrams along the movement path of electrons in the channel. FIG. 4 shows the case where the present invention is used, and FIG. 5 shows the prior art. In FIG. 4, since a part of the region is a p-type with a relatively high concentration, the levels of the conduction band and the valence band are increased, and the inclination of the conduction band from the gate to the region is reduced.

In the case of GaAs, the lowest energy level in the conduction band is a Γ band having a small effective mass.
The energy level 0.29 eV higher than the band has the bottom of the L band having a large effective mass. When the potential gradient of the channel is large, as shown in FIG. 5, electrons move from the Γ band to the L band while traveling from the gate to the drain, so that the electron velocity decreases. On the other hand, using the present invention, as shown in FIG. 4, the potential gradient in the channel is relaxed to suppress an excessive increase in the kinetic energy of electrons,
By suppressing the Γ-L transition, the electron speed can be improved. Note that the method of changing the potential and the like of the region is not limited to p-type impurity doping.

Embodiment 1 (FIG. 1) First, a method for manufacturing a device using the present invention will be described. Ga
A buffer layer having a thickness of 5
A 100 nm p-type GaAs layer 11 (1 × 10 ¹⁷ / cm ³ ) is grown by MBE, and an nGaAs layer 12 is formed thereon.
(200 nm ³ × 10 ¹⁷ / cm ³ ). GaAs
A silicon oxide film (not shown) is deposited on the layer 12 by a thermal CVD method. An oxide film at the source and drain portions is removed by photolithography and etching, n-type impurities are ion-implanted, and then AuGe 21 and 23 are deposited, and an ohmic junction 13 of the source and drain is formed by alloying. The gate electrode is formed by patterning the gate by photolithography to remove the etching oxide film and depositing Al.

Thereafter, Be ions are implanted between the gate and the drain by a focused ion beam technique (acceleration energy 60
A region A is formed at a keV and a dose of 1 × 10 ¹⁴ / cm ² ). Here, FIB is used, but the method of introducing impurities is not limited thereto.

Here, the object of the present invention can be achieved not only by the impurity introduction into the region A but also by a structure in which the crystal structure is partially changed by some means.

Embodiment 2 (FIG. 2) A p-type GaAs layer 11 (1 × 10 ¹⁷ / cm) having a thickness of 500 nm is formed as a buffer layer on a GaAs semi-insulating substrate 10.
³ ) is grown by molecular beam epitaxy (MBE), on which an undoped GaAs layer (20 nm)
nAlGaAs layer (10 nm, 5 × 10 ¹⁸ / cm ³ ), undoped GaAs
Layer (2 nm), nAlGaAs layer (20 nm 3 × 10 ¹⁹ / c
m ³ ) and an nGaAs layer (50 nm ³ × 10 ¹⁹ / cm ³ ) are sequentially laminated.

After element isolation by mesa etching, a silicon oxide film (not shown) is deposited by thermal CVD. By photolithography and etching, the oxide film of the source and drain parts is removed, AuGe is deposited,
An ohmic junction is formed by alloying. The oxide film at the opening between the source and the drain is removed by photolithography and etching, the nGaAs layer and the nAlGaAs layer are removed by etching, the undoped GaAs layer is removed by dry etching, and the gate electrode 22 is formed by a lift-off method after depositing Al. Form. Subsequently, a p-type impurity ion is implanted by FIB to form a region B.

Embodiment 3 (FIG. 3) The manufacturing process up to the formation of the gate electrode 22 is the same as in Embodiment 2. However, the acceleration energy of the FIB is changed discontinuously on the way to keep the impurity ion concentration on the channel low. As a result, impurity ions serving as scattering centers on the electron traveling path can be eliminated, and an increase in the probability of elastic scattering, which is one of the causes of a reduction in electron velocity, can be suppressed.

It is to be noted that the embodiment of the present invention is not limited to AlGaAs / GaAs-.
MESFET and HEMT have been described as examples. However, the semiconductor material to which the present invention can be applied is not limited to GaAs and AlGaAs. For example, two or more conduction bands or valence electrons having different effective masses and different band bottom energies, such as InGaAs, InGaP, InGaSb, InSb, and mixed crystals thereof, are used. If the material has a band, the above discussion holds.

The kind of the carrier is not limited to the electron but may be a hole as long as the above conditions such as InGaAs are satisfied.
As for the element structure, the present invention is applicable to MESFET, HE
The present invention is not limited to MT, and can be similarly applied to a field-effect element.

As described above, the present invention can be applied to the whole field effect element, but is also suitable for application to a high frequency circuit in order to improve the electron velocity in the channel of the element. Further, as described above, the present invention can be implemented without particularly complicated processes such as ion implantation. Therefore, the present invention has good applicability to an integrated circuit, and the use of the present element can realize high performance of an integrated circuit. In addition, the present invention satisfies the above requirements without increasing the power consumption of the elements, and thus is suitable for application to components of a communication system, for example, mobile terminals.

[0019]

According to the semiconductor device of the present invention, by suppressing the Γ-L transition of electrons in the channel, it is possible to improve the electron speed without excessively miniaturizing in the horizontal direction. As a result, an element having high cut-off frequency and excellent characteristics having a mutual conductance can be obtained.

[Brief description of the drawings]

FIG. 1 is a sectional view showing an element structure of a MESFET according to one embodiment of the present invention.

FIG. 2 is a sectional view showing an element structure of a HEMT according to one embodiment of the present invention.

FIG. 3 is a sectional view showing an element structure of a HEMT according to one embodiment of the present invention.

FIG. 4 is a band diagram of the device of the present invention.

FIG. 5 is a band diagram of a prior art device.

FIG. 6 is a sectional view showing an element structure of a conventional MESFET.

[Explanation of symbols]

10 semi-insulating substrate, 11 buffer layer, 12 channel layer, 13 contact layer, 131 i-GaAs layer,
132 ... N-AlGaAs layer, 133 ... n-GaAs layer, 14
... Carrier supply layer (N-AlGaAs), 21 ... Source electrode,
22: gate electrode, 23: drain electrode.

Claims (9)

[Claims] In a semiconductor device having at least a buffer layer, a channel layer, an electrode layer, and gate, source, and drain electrodes on a semiconductor substrate, a portion between a portion immediately below a gate electrode of the channel layer and a drain or source electrode layer is provided. Has at least one region where the change in potential or electronegativity or conduction band or valence band level along the direction of current conduction in the channel is larger than that in other portions (hereinafter referred to as region A). A semiconductor device characterized by the above-mentioned. 2. The semiconductor device according to claim 1, wherein a distance from the electrode layer to the region A is half or less than a distance between the gate and the electrode layer. 3. A semiconductor device having at least a buffer layer, a channel layer, an electrode layer, and gate, source and drain electrodes on a semiconductor substrate, between a portion immediately below the gate electrode of the channel layer and the drain or source electrode layer. Wherein at least a part of the semiconductor device is provided with a region having a higher impurity concentration than another part (hereinafter referred to as a region B). 4. A semiconductor device having at least a buffer layer, a channel layer, an electrode layer, and gate, source, and drain electrodes on a semiconductor substrate, wherein a portion immediately below a gate electrode of the channel layer and a drain or source electrode layer are provided. A semiconductor device provided with a region (hereinafter referred to as a region C) having an impurity concentration higher than that of the other portion in at least a part other than the current path. 5. The semiconductor device according to claim 2, wherein
A semiconductor device, wherein the impurity in the region B or the region C is introduced by a focused ion beam (FIB). 6. A semiconductor device having at least a buffer layer, a channel layer, an electrode layer, and gate, source, and drain electrodes on a semiconductor substrate, between a portion immediately below the gate electrode of the channel layer and the drain or source electrode layer. A semiconductor crystal provided in at least a part thereof with a region different from other parts. 7. A high-frequency circuit using the semiconductor device according to claim 1. 8. An integrated circuit using the semiconductor device according to claim 1. 9. A communication system using the semiconductor device according to claim 1.