JPH1016292A - Imaging system and control method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To correct color shift quickly in color printing. SOLUTION: A target address generation circuit 22 detects the main scanning sync signal, i.e. a BD signal, immediately after detection of a TOP signal indicating the head of a drum and an address being generated at that moment of time in synchronism with driving of the drum is employed as a target address. An address comparison circuit 29 compares a currently generated set address with the target address and makes a decision which of the incremental or decremental correction of the set address is performed quicker. A set address control circuit 26 increments or decrements the set address one by one according to the decision results. A constant phase difference waveform generation circuit 30 generates a plurality of phase difference signals corresponding to the value of the set address and a clock selection circuit 32 outputs a phase difference waveform corresponding to the set address. Consequently, the set address approaches the target address gradually and a pulse motor clock being generated in synchronism with an output signal from the clock selection circuit 32 has a phase corresponding to the target address.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image forming apparatus, and more particularly to an image forming apparatus for controlling color misregistration when performing color printing and a control method therefor.

[0002]

2. Description of the Related Art When performing multi-color printing by an electrophotographic method or the like, since a color image is formed by superimposing images of respective colors, control for preventing color misregistration is performed.

As one of the color misregistration control methods in such a multi-color printing operation of electrophotography or the like, a method of controlling the phase of a synchronous motor in the main scanning direction to match the phase of a drive motor of a photoconductor or a transfer body is used. Is considered. With this control, the relationship between the position of the image and the position of the photosensitive member or the transfer member is matched for each color to prevent color shift.

As a first method, a plurality of signals having a constant phase difference are matched with a reference signal from a plurality of signals having a fixed phase difference with respect to the main scanning direction synchronization signal immediately after the sub-scanning direction synchronization signal is output. There is a method of selecting a signal to be used as a drive motor control signal.

As a second method, there is a method of detecting a phase difference between a sub-scanning direction synchronizing signal and a main scanning direction synchronizing signal, and performing correction control to suppress the phase difference.
For example, there is a method in which the phase difference between the sub-scanning direction synchronization signal and the main scanning direction synchronization signal immediately after the detection of the sub-scanning direction synchronization signal is counted by a detection pulse, and phase control is performed by switching to the correction signal by that value. is there.

[0006]

However, in the first conventional example described above, in order to match the phase of the control signal of the photosensitive drum or the transfer drum with the phase of the synchronization signal in the main scanning direction, A long control time is required, and a circuit configuration required for this control is also large.

In the second method, detection pulses,
The frequency setting of the drum drive signal and the correction signal has become complicated, making it difficult to select a reference clock.

Further, in the conventional circuit configuration, the period of the detection pulse directly affects the period of the correction signal, and there is a contradictory problem that shortening the control time leads to deterioration in detection accuracy.

An object of the present invention is to solve the above-mentioned problems of the prior art, and a first object of the present invention is to make the phase of the main scanning direction synchronizing signal and the phase of the drum control signal coincide with each other in a short time. I do.

It is another object of the present invention to reduce the circuit scale required to match the phase of the drum control signal with the phase of the synchronization signal in the main scanning direction.

It is another object of the present invention to uniquely determine a frequency division ratio of a frequency divider for generating a correction pulse.

Further, according to the present invention, in the color misregistration control, a starting point of a phase difference measuring clock for measuring a time length of a phase difference between a sub-scanning direction synchronizing signal and a main scanning direction synchronizing signal is synchronized with a reference clock. An image forming apparatus that enables color misregistration control that improves the measurement accuracy of the phase difference signal by increasing or decreasing the measurement value in units of the phase difference measurement clock based on the result of comparison between the phase difference time agency and the value measured by the phase difference measurement clock Is to provide.

[0013]

To achieve the above object, an image forming apparatus according to the present invention has the following arrangement.
That is, an image forming apparatus that draws a line in the main scanning direction on a drawing surface in synchronization with a main scanning synchronization signal, and conveys the drawing surface in the sub-scanning direction to form an image. Means for generating a sub-scanning synchronizing signal indicating a predetermined position, reference clock generating means for generating a reference clock, and synchronizing with the reference clock, a plurality of pulse signals having the same cycle and having different phases from each other. A constant phase difference signal generating means for generating, a main scanning synchronization detecting means for detecting a first main scanning synchronization signal which is a main scanning synchronization signal immediately after the generation of the sub-scanning signal, and an address generated in synchronization with the reference clock From, target address generation means for selecting a target address at the timing of the first main scanning synchronization signal,
Setting address generating means for generating a cyclic address corresponding to one of the constant phase difference signals; comparing an address generated by the setting address generating means with a target address generated by the target address generating means; Address comparing means, a signal selecting means for selecting a constant phase difference signal corresponding to the set address generated by the set address generating means, and the constant phase difference signal selected by the signal selecting means. Sub-scanning means for transporting the drawing surface in the sub-scanning direction, wherein the set address generating means gradually changes the current set address to the target address in a direction in which the difference between the two addresses is minimized. Get closer.

Alternatively, a first address generating means and a constant phase difference for generating a predetermined number of constant phase difference signals corresponding to a value indicated by a lower part of the first address generated by the first address generating means. Signal generating means, second address generating means for generating a second address in synchronization with one cycle of the first address generating means, and the second address from the predetermined number of constant phase difference signals. Selecting means for selecting and outputting a constant phase difference signal corresponding to a lower value of the counter; detecting means for detecting a match between an upper bit of the first address counter and an upper bit of the second address counter; A second selecting means for outputting a constant phase difference signal selected by the selecting means at a timing coincident by the means, and a signal output by the second selecting means. And Zui comprising, driving means for driving the image drawing surface in the sub-scanning direction, on the image drawing surface, and means for drawing an image along the main scanning direction.

Alternatively, an image forming apparatus for forming an image by carrying a drawing surface in a sub-scanning direction while drawing a line in a main scanning direction on a drawing surface in synchronization with a main scanning synchronization signal, A driving unit that conveys a drawing surface in a sub-scanning direction with a reference signal having a predetermined period, a phase shift between the main scanning synchronization signal and the reference signal, and a timing of the reference signal in order to correct the phase shift. And a phase correcting means for changing the phase of the reference signal and outputting the reference signal based on the result of the determination by the determining means.

Alternatively, an image forming apparatus for forming an image by drawing a line in the main scanning direction on a drawing surface in synchronization with a main scanning synchronization signal and conveying the drawing surface in the sub-scanning direction to form an image. Basic signal output means for outputting a synchronization signal, measurement signal output means for outputting a measurement signal of a predetermined period, and phase difference signal generation means for generating a phase difference signal between a predetermined position on the drawing surface and the main scanning synchronization signal A correction signal output unit that outputs a correction synchronization signal having a period obtained by adding the period of the measurement signal and the period of the basic synchronization signal, and a phase difference signal generated by the phase difference signal generation unit The length of the phase difference measurement means for measuring the number of wavelengths of the measurement signal, and when the phase shift is detected by the detection means,
Control means for outputting the correction synchronization signal having a wave number corresponding to the number measured by the phase difference measurement means, and thereafter outputting the basic synchronization signal, and driving means for driving the drawing surface in the sub-scanning direction .

The control method of the image forming apparatus according to the present invention has the following configuration. That is, while drawing a line in the main scanning direction on the drawing surface in synchronization with the main scanning synchronization signal,
A method of controlling an image forming apparatus that forms an image by transporting the drawing surface in a sub-scanning direction in synchronization with a reference signal having a predetermined period, comprising detecting a phase shift between the main scanning synchronization signal and the reference signal. A determination step of determining a method of reducing the required time, which is either a stepwise advance or a delay of the timing of the reference signal, in order to correct the phase shift; and a determination of the reference signal based on a determination result by the determination unit. And a phase correcting step of changing the phase and outputting.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION

[First Embodiment] FIG. 1 shows a schematic configuration of an example of an image forming apparatus according to the present embodiment. The image forming apparatus of this embodiment is a color laser beam printer (color image forming apparatus) using an electrophotographic process. Since the color laser beam printer itself is publicly known, the description thereof will be briefly omitted.

In FIG. 1, reference numeral 1 denotes a printer main body, and 2 denotes an interface unit which inputs digital image data read by a scanner or the like (not shown) or created by a computer or the like. The printer 1 prints out an image corresponding to the data input from the interface unit 2 in full color. The RGB signals sent from the interface unit 2 to the signal processing unit 3 are converted into magenta (M), cyan (C),
The image signal is converted into yellow (Y) and black (Bk) image signals and sent to the laser driver 4. The laser driver 4 modulates the semiconductor laser 5 with respect to the image signal and outputs a modulated laser beam L corresponding to the image signal. The laser beam L scans a photosensitive drum 9 as an image holding member via a polygon mirror 6, an f-θ lens 7, and a mirror 8.

The photosensitive drum 9 is driven to rotate at a predetermined peripheral speed (process speed) in a counterclockwise direction in the figure, and an electrostatic latent image is formed by scanning the laser beam on the charged surface of the photosensitive drum. Is done.

Reference numeral 12 denotes a rotary developing unit, which is composed of a magenta developing unit 13, a cyan developing unit 14, a yellow developing unit 15, and a black developing unit 16. The four developing units alternately contact the photosensitive drum, and Is developed with toner.

The above-described latent image formation and development are repeated for each of the magenta, cyan, yellow, and black image signals, so that the four color toner images of the magenta toner image, the cyan toner image, the yellow toner image, and the black toner image are the same. The images are sequentially transferred onto the transfer belt 17 in an overlapping manner.

When the development of all four colors is completed on the transfer belt 17, the paper P fed from the paper cassette 18 is wound around the transfer belt 17, and the developed image is transferred to the transfer belt 17 again, whereby a full-color image is formed. Is formed.

FIG. 7 is a block diagram of a configuration for realizing color shift prevention in the printer of FIG. In the figure, the same parts as those in FIG. 1 are denoted by the same reference numerals. The laser driver 4 causes the semiconductor laser 5 to output laser light modulated based on the YMCBk signal output from the signal processing unit 3. Laser light is polygon mirror 6
Is reflected by the laser sensor 71 through the f-θ lens 7.
And is reflected by the reflection mirror 8 to scan the developing drum 9 to form an electrostatic latent image. When detecting the laser beam, the sensor 71 outputs a beam detection signal (BD signal). The BD signal is input to the signal processing unit 3, where the horizontal synchronization of the image signal is adjusted and the phase control circuit 74
Is also entered. Further, the sensor 72 detects a predetermined position on the outer peripheral portion of the developing drum 9 and outputs a TOP signal.

The phase control circuit 74 includes a BD signal and a TOP signal.
Pulse motor 73 that drives the developing drum based on a signal
Is controlled so that the image formed on the developing drum is at the same position for each color.

In the configuration shown in FIG. 1, it is necessary to control the multicolor image formed on the transfer belt 17 so that the image of any color formed on the developing drum is located at the same position. is there. Therefore, the transfer belt 1
7, a sensor 10 for detecting a mark attached to a predetermined position
1 (FIG. 1), and the output signal thereof can control the positional deviation between the developing drum 9 and the transfer belt. The point of this control may be the same as that described below. Alternatively, the developing drum and the transfer belt can be mechanically synchronized by omitting the sensor 10. <Description of Phase Control Circuit> FIG. 2 is a block diagram showing a detailed description of the phase control circuit 74.

The reference CLK generating circuit 20 comprises a crystal oscillator or the like, and generates a reference CLK signal 21. The target address generation circuit 22 firstly outputs a main scanning direction synchronization signal 23 (hereinafter abbreviated as a BD signal) immediately after detecting the sub-scanning direction synchronization signal 24 (hereinafter abbreviated as a TOP signal), that is, on the developing drum 9. The main scanning direction synchronizing signal indicating the first line of the image formed in the main scanning direction is detected. That is, the shift amount from the detection of the TOP signal to the detection of the BD signal is detected. As a result, an n-bit target address At25 that matches the phase of the BD signal 23 is specified from the reference CLK signal 21 or an address signal generated from a clock obtained by arbitrarily dividing the target signal, and is used as a target value for phase control. . That is, for example, an address is generated by an n-bit cyclic counter A clocked by a reference CLK signal, and the counter A is detected at the timing when the BD signal immediately after the TOP signal is detected.
Is latched as a target address. It is desirable that the cycle of the cyclic counter A (2 @ n clock) coincides with the number k of signals generated by the constant phase difference waveform generating circuit 30 described later (2 ^ n = k). Note that x ^ y indicates x to the power of y.

The set address control circuit 26 generates an m-bit set address Aa 28 for determining the phase of the pulse motor clock signal 35. In the non-control section, the set address Aa28 is a fixed value. Only in the control section, the phase of the motor clock signal is changed by making the address up / down by the up / down flag 27 output from the address comparison circuit 29 so as to match the target. Thus, the positional relationship between the position on the developing drum and the position of the image is always kept constant.

The address comparison circuit 29 calculates the target address A
The difference between t25 and the set address Aa28 is calculated, and the currently selected set address Aa28 becomes the target address Aa.
It is determined whether the set address should be selected to be up / down / maintain in order to reach the shortest at t25. The result is output to the set address control circuit 26 as an up / down flag 27.

The constant phase difference waveform generating circuit 30 has a reference CLK
The signal 21 is frequency-divided and each has a constant delay time τ with a period τs.
Generate k constant phase difference delay signals 31 having d.
Each of these constant phase difference signals corresponds to a unique address, and each time the address increases or decreases by one, the phase of the corresponding phase difference signal moves backward / forward by τd. That is, the delay time τd is k and the period τs (τs = k ·
τd). However, the delay time τd is basically the same as the output cycle of the target address At25.

The clock selection circuit 32 selects one of k constant phase difference delay signals 31 as a motor control clock signal 33 based on an m-bit address control signal 28 output from the set address control circuit 26.

The pulse motor clock generation circuit 34 generates a pulse motor clock having the same phase as the phase selected by the clock selection circuit 32,
Generates, for example, a four-phase drive signal for driving the pulse motor in synchronization with the pulse motor clock. <Address Control Procedure> FIG. 3 is a flowchart showing an outline of an address control operation by the phase control circuit shown in FIG. The procedure of FIG. 3 is a control that is comprehensively performed by the configuration of FIG. 1, and each step of FIG. 3 is performed corresponding to each block of FIG. Further, the control in FIG. 3 can be realized by a mechanical control processor which is a processor for controlling the printer engine. In this case, the program of the procedure of FIG. 3 is stored in a ROM or the like, and the processor executes the program.

In FIG. 3, when the TOP signal 24 is detected, the control operation is started (step S301), and the BD signal 23 output immediately after the detection is detected (step S3).
02), an n-bit target address At25 having phase information is generated by those signals (step S30).
3). The target address At25 is a control target value to be finally reached. Next, the currently set address Aa25 is extracted (step S304). The setting address Aa25 is an m-bit address for generating a pulse motor clock signal.

Next, the magnitude relationship between the target address At25 and the set address Aa28 is compared (step S30).
5). Further, it is determined whether the set address 28 is to be raised or lowered depending on whether the difference value is larger or smaller than half the value of all addresses A = 2 ^ n (steps S306 and S307). That is, to match the set address with the target address, the current set address is added or subtracted, whichever is earlier. However, if the target address At = set address Aa, there is no need to change the set address.

For example, assume that the total number of addresses is "16", the value of the target address 25 is "2", and the value of the currently selected set address 28 is "7". Since (destination address At25 value) <(set address Aa value) in the address comparison, and the difference value is equal to or less than a half value “8 (= 2/16)” of all addresses, the set address 2
The direction in which the value of 8 is to be decreased is selected.

When the direction for changing the set address is determined in this way, when increasing the set address, one is added to the set address Aa (step S308).
It is determined whether or not the address matches the target address At (step S
309) If they do not match, repeat from step S308 until they match. Similarly, when decreasing the set address, 1 is subtracted from the set address Aa (step S310), and it is determined whether or not the set address Aa matches the target address At (step S311).
Repeat from 308 until match. In this manner, by shifting the address by one, the phase of the clock input to the pulse motor clock generation circuit is shifted by τd.

When the target address and the control address match in this way, the control operation is terminated to fix the set address, and the value is continuously output until the next control operation is started (step S312). That is, when the set address finally reaches the phase corresponding to the target address, the set address is fixed, and the phase of the pulse motor drive signal is fixed.

The phase control is performed in the non-image area after the detection of the TOP signal 24. When the TOP signal 24 has a positive logic, the start timing may be either the leading edge or the trailing edge. When the target address signal At28 is detected, the control operation is started, and the control address signal Aa28 is turned up / down to match the target address signal At28 having the phase information of the BD signal 23.

FIG. 8 shows the timing of the configuration of FIG. 1 when the total number of addresses is "16", the value of the target address At is "2", and the value of the currently selected set address Aa is "7". It is an example of a figure.

When the BD signal immediately after the TOP signal is detected,
The value of the target address generation count at that time is set as the target address At. This value is “2”. Also,
The current value of the set address Aa is “7”, and in the address comparison, (target address Aa25 value) <(set address Aa value), and the difference value is a half value “8” of all addresses.
(= 2/16) "or less, the direction of decreasing the value of the set address Aa is selected. As a result, the value of the set address Aa is subtracted from “6” “5” “4” “3” “2”.

FIG. 9 is a timing chart showing how the set address Aa is subtracted in synchronization with the BD signal and a motor control clock is generated in accordance with the result. Signal φ7 ~
φ2 is a phase difference waveform signal corresponding to address values 7 to 2, respectively. The setting address Aa is "7" → "6" → ...
When it changes to “2”, the phase difference waveform selected by the clock selection circuit 32 as the motor control clock also changes correspondingly to φ7 → φ6 →... → φ2. As a result, the motor control clock signal changes its phase so as to reach the phase corresponding to the target address in the shortest time. As a result, the phase of the pulse motor for driving the developing drum is adjusted to the BD signal detected immediately after the signal TOP, and the position of the image formed on the developing drum can be kept constant.

As described above in detail, according to the image forming apparatus of the present embodiment, when performing the phase control for making the phase of the drum control signal coincide with the phase of the BD signal immediately after the detection of the TOP signal, the drum control signal is output. This brings about an effect that the control for matching the set address to be managed to the target address corresponding to the phase of the BD signal is completed in a short time that is half the normal time. [Second Embodiment] As a second embodiment, a configuration of a circuit for selecting one specified from a plurality of phase difference delay signals will be described. First, a conventional example will be described.

FIG. 4 is a block diagram showing a conventional example of a circuit configuration for selecting one specified from a plurality of constant phase difference waveform signals. In the present embodiment, it is sufficient to show only the configuration of these blocks, and thus the description of the target address generation circuit, the address comparison circuit, and the set address control circuit in the first embodiment is omitted.

In FIG. 4, the constant phase difference waveform generating circuit 30 in FIG.
It includes a 64 decoder 42, a drum clock generation circuit 45, and an address counter 47. Here, an example will be described in which the constant phase difference delay signal 31 in FIG. 2 is set to k = 64.

A 6-bit address signal (A0-A) is supplied from the address counter (a) 40 by the reference CLK signal 21.
5) 41 is output. This address signal 0-2 ^ 6-1
= 63 based on 64 constant phase difference delayed signals 43
-64 decoder 42. As a result, the constant phase difference delay signal 43 has the same delay amount τd as the period of the reference CLK signal 21. Drum clock generation circuit 4
5 generates a drum address clock signal 46 having the same cycle as the motor control clock signal 33. With the drum address clock signal 46, an address counter (b) 47
Inputs a 6-bit clock selection control signal 48 to the 64-1 multiplexer 44. This is intended to cause the constant phase difference delay signal 43 to be selected at the cycle of the drum address clock signal 46. Further, the 64-1 multiplexer 44 is one of means for realizing the clock selection circuit 32.

Next, a description will be given of a circuit according to the present invention, which is an improvement of the above conventional example.

FIG. 5 is a block diagram showing a second embodiment of the present invention, and FIG. 6 is a timing chart of main blocks. The constant phase difference waveform generating circuit 30 includes an address counter (c) 50, address counters (d) 57 and 3-8.
The decoder 53, the 8-1 multiplexer and the coincidence detecting circuit 60 are used.

The 6-bit address signal (C0 to C5) output from the address counter (c) 50 is divided into upper 3 bits (C3 to C5) and lower 3 bits (C0 to C2). And 3-8 decoder 53. Lower 3-bit address signal (C0-C2)
Reference numeral 52 is used by the 3-8 decoder 53 to generate eight constant phase difference delay signals (φ0 to φ7) 54 as shown in FIG. On the other hand, the upper three bits of the address signal (C
3 to C5) 51 are input to the coincidence detection circuit 60 and compared with the address signals (D3 to D5) 58 of the upper 3 bits of the address counter (d) 57.

The drum clock generation circuit 45 generates the drum address clock signal 46. The period will be described assuming that the period is 64 times the reference CLK signal 21 as an example.

The address counter (d) 57 generates a 6-bit address signal (D0 to D5) based on the drum address clock signal 46, and inputs an upper 3-bit address signal (D3 to D5) 58 to the coincidence detection circuit 60. The lower 3 bits of the address signal (D0 to D2) 59 are set to 8-1.
It is a control signal for the multiplexer 55. Focusing on the 8-1 multiplexer 55, one of the eight constant phase difference delay signals (φ0 to φ7) 54 is designated by the address value of the lower 3-bit address signal (D0 to D2) 59. The output of the 8-1 multiplexer 55 is the address designation (D0 to D0) of the lower three bits of the address counter (d).
D2) is equal to 8 of the period of each constant phase difference signal.
Because it is twice, one constant phase difference delay signal (φ0 to φ7) specified by the address signal (D0 to D2) 59
Is repeatedly output eight times. That is, eight phase difference delay signals having different phases can be obtained from one phase difference delay signal. The original signal is 8 from φ0 to φ7
Since eight signals having different phases are further obtained, a total of 8 × 8 = 64 phase difference delay signals are generated.

Therefore, in the match detection circuit 60, the address (D) of the upper three bits of the address counter (d) 57
3 to D5) and the upper three bits of the address (c3) of the address counter (c) 50 (C3 to C5) to compare the eight constant phase difference delay signals (φ0 to φ7) output from the 8-1 multiplexer 55. ) 54 to output a data selector control signal 61 enabling one to be selected.

The data selector 62 realizes the clock selection circuit 32 shown in FIG. 2 and has eight constant phase difference delay signals (φ0
~ Φ7) 54 is further shifted by 8 from the upper 3-bit address signal.
By defining the addresses, 64 constant phase difference delay signals corresponding to 64 addresses are obtained. The motor control clock signal 33 is obtained by selecting one of the 64 signals having different phases obtained thereby.

With the above configuration, a signal having a phase shifted by a delay time τd at a predetermined cycle can be selected and output from a plurality of constant phase difference delay signals. By applying such a circuit and adding a circuit for fixing the clock selection control signal 48 when it reaches the target address, the configuration shown in FIG. 2 can be realized. According to this configuration, the 6-64 decoder and the 64-bit decoder are not reduced in accuracy as compared with the conventional example.
A simple circuit configuration can be realized without using a large-scale circuit such as one multiplexer.

According to the image forming apparatus having the above configuration, a configuration for selecting a desired one from a plurality of constant phase difference signals is constituted by a minimum constant phase difference signal generation circuit and a coincidence detection circuit. In addition, there is an effect that the color misregistration control is performed without deteriorating the detection accuracy. [Third Embodiment] As a third embodiment, another example of the configuration of the phase control circuit in FIG. 7 will be described.

FIG. 10 is a block diagram showing a detailed description of the phase control circuit according to the present embodiment, and FIG. 11 shows a timing chart of main blocks.

The reference CLK generating circuit 24 includes a crystal oscillator or the like, and generates a reference CLK signal 25 having a period τ0. The frequency divider (a) 26 is for the phase difference measurement circuit 32, the frequency divider (b) 27 is for the basic pulse generation circuit 36, and the frequency divider (c)
Reference numeral 28 denotes a clock signal (2
9 to 31).

The TOP-BD detection circuit 22 receives the sub-scanning direction synchronizing signal 20 (hereinafter abbreviated as a TOP signal) and the main scanning direction synchronizing signal 21 (hereinafter abbreviated as a BD signal), and
The BD signal 21 immediately after the output of the OP signal 20 is detected. The detection result is output to the phase difference measurement circuit 32 as a pulse-like phase difference signal 23 from the edge of the TOP signal to the rising edge of the BD signal. The phase difference measurement circuit 32
The phase difference is measured by counting the phase difference signal 23 by the phase difference measurement clock 29 having the cycle k · τ0, and the result is sent to the correction section control circuit 34 as the phase difference count value 33.

The basic pulse generating circuit 36 generates a basic drum pulse signal 38 having a period n · τ0 based on the basic drum clock 30. The basic drum pulse signal 38 has the same frequency as the drum drive signal 43. The correction pulse generation circuit 37 generates a cycle (n) based on the correction drum clock 31.
+ K) · Generates a corrected drum pulse signal 39 of τ0.
Basic drum pulse signal 38 and correction drum pulse signal 3
9 is input to the drum pulse selection circuit 40 and any one is selected and output as the drum pulse signal 41 by the correction control signal 35.

The drum pulse signal 41 is further fed back to the correction section control circuit 34. The correction section control circuit 34 counts the drum pulse signal 41 by the same number as the phase difference count value 33. Correction drum pulse signal 3
The cycle of 9 is the cycle n · τ0 of the basic drum pulse signal 38.
Is added to the period k · τ0 of the phase difference measurement clock 29. The correction pulse generation circuit 37 outputs a correction drum pulse signal 39 whose cycle is longer by one clock (k · τ0) of the phase difference measurement clock than the reference drum pulse signal by the same number as the phase difference count value 33, and finally outputs the correction drum pulse signal 39. To B
Control is performed so that the phases of the D signal 21 and the drum pulse signal 41 match. Therefore, the clock selection signal 35
The phase difference between the signal and the TOP signal is measured, and the correction drum pulse signal 39 is selected in the correction section from the start to the end of the correction of the drum pulse, and the basic drum pulse signal 38 is selected in the other than the correction section. It becomes a control signal.

Next, the relationship between the reference CLK generating circuit 24 according to the present invention and the frequency divider (a) 26, frequency divider (b) 27, and frequency divider (c) 28 will be described below.

The frequency f0 of the reference CLK signal 25 is defined as a period τ0. The frequency dividing ratio of the frequency divider (a) 26 is set to 1 / k, and the frequency dividing ratio of the frequency divider (b) 27 is set to 1 / n. Thereby, the phase difference measurement clock 29 and the basic drum clock 3
If the periods of 0 are τk and τn, respectively, the following [1],
[2] It is represented by the formula.

Τk = k · τ0 [1] τn = n · τ0 [2] (k and n are arbitrary integers) In the above-described phase control circuit, the period τn ′ of the correction drum pulse signal 39 is , Phase difference measurement clock 29
And the period τn of the basic drum pulse signal 38 are set. Therefore, the period τn ′ of the correction drum pulse signal 39 is expressed by the following equation [3].

Τn ′ = τk + τn = (k + n) · τo [3] From the above, the 29 cycles τk of the phase difference measurement clock and the 38 cycles τn of the basic drum pulse signal have an arbitrary integer ratio with respect to 25 cycles τ0 of the reference CLK signal. Can be set by selecting When the 29 cycles τk of the phase difference measurement clock and the 38 cycles τn of the basic drum pulse signal are determined, the 39 cycles τn ′ of the corrected drum pulse signal are uniquely determined. vice versa,
When 38 cycles τn of the basic drum pulse signal or 29 cycles τk of the phase difference measurement clock are determined, 25 cycles τ0 of the reference LCK signal are determined by an arbitrary integer ratio.

According to the image forming apparatus described in detail above, the color misregistration control circuit detects the sub-scanning direction synchronizing signal and an arbitrary main scanning direction synchronizing signal, and measures a phase difference measurement clock and a rotator driving unit for measuring them. By selecting the frequency division ratio of each frequency divider that generates the basic pulse for driving the pulse generator to an arbitrary integer ratio, it is possible to realize that the frequency divider that generates the phase correction pulse is uniquely determined. For this reason, the frequency of the signal can be easily determined.

By adjusting the phase of the basic drum clock to the phase of the BD signal by such a phase control circuit,
An image of each color can be formed at a fixed position on the drum, and color shift can be prevented. [Fourth Embodiment] FIG. 12 is a block diagram showing a phase control circuit according to a fourth embodiment of the present invention. FIG.
Compared with 0, the difference is that a phase difference clock generation circuit 50 is used instead of the frequency divider (a) 26. The phase difference clock generation circuit 50 synchronizes not only the frequency division of the reference clock but also the phase of the generated phase difference measurement clock with the reference clock. FIG. 13 is a block diagram showing details of the phase difference clock generation circuit 50, and FIG.
Is a timing chart of the main blocks of the phase difference clock generation circuit.

In FIG. 13, a measurement basic clock generation circuit 56 divides the reference CLK signal 25 and generates a measurement basic clock 57 whose rising edge coincides with the reference clock signal. This is to make the phase difference between the rising edge of the measurement clock 57 and the phase difference signal 23 less than the period τ0 of the reference CLK signal 25. Note that the phase difference signal 23 has the same meaning as in the third embodiment. FIG.
In No. 4, as an example, the period τc of the measurement basic clock 57 is set to be eight times the period τ0 of the reference CLK signal 25.

The period detection circuit 58 samples the level of the measurement basic clock 57 at the falling edge of the phase difference signal 23, and performs measurement based on the actual length τp of the phase difference signal 23 and the sampling by the measurement basic clock 57. It is detected whether the time error ΔP1 is larger or smaller than の of the period τc of the measurement basic clock 57. The output has two cases depending on the magnitude relationship between ΔP1 and τc.

In case 1, error ΔP1 is 1 / period τc.
If it is larger than 2, the cycle detection circuit 58 outputs a signal indicating that a high level has been detected as a cycle determination signal.
The clock gate control circuit 60 outputs a gate control signal 61 that falls after the phase difference signal 23 ends. The clock gate 62 starts the output of the measurement basic clock 57 as the measurement clock 51 from the second rising from the rising of the phase signal 23, falls at the falling of the gate control signal 61, and stops the output. Since the phase difference measurement circuit 32 does not count the last rising edge of the measurement clock 51, the actual length .tau.
, There are α rising edges of the measurement basic clock 57, whereas the actual number of clocks is (α−1). Thus, the relationship between the actual length τp of the phase difference signal 23 and the measurement value τs by the measurement clock 51 is represented by the following equation [4].

Τp−τs <１ ／ · τc + τ0 (where τp ≧ τs) [4] On the other hand, in case 2, the error ΔP1 is smaller than の of the period τc, and the gate control signal 61 Phase difference signal 23
After the end, the signal is set to stop at the first rising edge of the measurement clock 57. The clock gate 62 outputs the measurement clock 51 in the same manner as in the case 1. That is, contrary to Case 1, when the end point of the phase difference signal 23 exceeds a half cycle from the rise of the measurement basic clock 57, the number of clocks of the measurement basic clock 57 measured by the phase difference measurement circuit 32 is set to α. Number. Accordingly, the relationship between the actual length τp of the phase difference signal 23 and the measurement value τs by the measurement clock 51 is expressed by the equation (5).

Τp−τs ≧ − ／ · τc + τ0 (5) (where τp ≦ τs, τc> τ0) In both cases 1 and 2, the minimum value of | τp−τs | When [4] and [5] are put together, the following expression is obtained: [1/2] [tau] c + [tau] 0> [tau] p- [tau] s≥- [1/2] [tau] c + [tau] 0 [6].

That is, by outputting the measurement clock as described above, when the phase difference is measured by the number of measurement clocks, the error is calculated by subtracting the error of the period of the measurement clock by 2 as shown in Expression [6].
It can be made smaller than a value obtained by adding one-half and the period of the reference clock. For this reason, the error can be suppressed to a small value, and the maximum value of the error is determined only by the cycle of the measurement basic clock and the reference clock. By determining the periods of the clock and the reference clock, it is possible to control color misregistration with higher accuracy. [Other Embodiments] The present invention relates to a plurality of devices (for example, a host computer, an interface device, a reader,
Printer, etc.)
The present invention may be applied to a device including one device (for example, a copying machine, a facsimile device, etc.).

Another object of the present invention is to provide a storage medium storing a program code of software for realizing the functions of the above-described embodiments to a system or an apparatus, and to provide a computer (or CPU) of the system or apparatus.
And MPU) read and execute the program code stored in the storage medium.

[0073]

As described above, by controlling the phase of the drive signal of the pulse motor, the desired phase can be adjusted in the shortest time. Also, the structure for control can be simplified.

Further, there is an effect that the configuration for selecting one designated from a plurality of constant phase difference signals is constituted by a minimum circuit, and the color shift control is performed without deteriorating the detection accuracy.

Further, the configuration for suppressing the color shift of the color image can be a configuration in which the correction drum clock is uniquely determined from the basic drum pulse and the phase difference measurement clock, and the frequency of the signal can be determined. It can be easily performed, and the design of a circuit for suppressing color misregistration becomes easy.

In the color misregistration control circuit of the image forming apparatus, the error can be suppressed to a small value, and the maximum value of the error is determined only by the cycle of the measurement basic clock and the reference clock. By determining the periods of the measurement basic clock and the reference clock so that the error falls within the range, color shift control can be performed with higher accuracy.

[0077]

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an image forming apparatus according to the present invention.

FIG. 2 is a block diagram illustrating a phase control circuit according to the first embodiment.

FIG. 3 is a flowchart showing an outline of an operation of address control by a phase control circuit.

FIG. 4 is a block diagram showing a conventional example of a constant phase difference waveform generation circuit and a clock generation circuit.

FIG. 5 is a block diagram of a constant phase difference waveform generation circuit and a clock generation circuit according to a second embodiment.

FIG. 6 is a diagram illustrating an output timing chart of main blocks according to the second embodiment.

FIG. 7 is a block diagram of a configuration for preventing color misregistration in the image forming apparatus.

FIG. 8 is a diagram illustrating an example of timing by the circuit of FIG. 2;

FIG. 9 is a diagram showing an example of timing by the circuit of FIG. 2;

FIG. 10 is a diagram illustrating details of a phase control circuit according to the second embodiment.

FIG. 11 is a timing chart in the phase control circuit according to the second embodiment.

FIG. 12 is a block diagram illustrating a phase control circuit according to a fourth embodiment of the present invention.

FIG. 13 is a block diagram showing details of a phase difference clock generation circuit 50;

FIG. 14 is a timing chart in the phase difference clock generation circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Printer main body 2 Interface part 3 Signal processing part 4 Laser driver 5 Semiconductor laser 6 Polygon mirror 7 f-theta lens 8 Mirror 9 Photosensitive drum 10 Sensor 11 Engine control part 12 Rotary developing device

Claims (15)

[Claims] 1. An image forming apparatus for forming an image by drawing a line in a main scanning direction on a drawing surface in synchronization with a main scanning synchronization signal and conveying the drawing surface in a sub-scanning direction to form an image. Means for generating a sub-scanning synchronization signal indicating a predetermined position on the drawing surface; reference clock generating means for generating a reference clock; and a plurality of clocks having the same cycle and different phases from each other in synchronization with the reference clock. A constant phase difference signal generating unit that generates a pulse signal; a main scanning synchronization detecting unit that detects a first main scanning synchronization signal that is a main scanning synchronization signal immediately after the generation of the sub-scanning signal; From the address
Target address generation means for selecting a target address at the timing of the first main scanning synchronization signal; setting address generation means for generating a cyclic address corresponding to one of the constant phase difference signals; Address comparing means for comparing the address generated by the setting address with the target address generated by the target address generating means; and signal selection for selecting a constant phase difference signal corresponding to the set address generated by the set address generating means. Means, and a sub-scanning means for conveying the drawing surface in the sub-scanning direction in synchronization with the constant phase difference signal selected by the signal selection means, the setting address generating means,
An image forming apparatus, wherein the address is gradually approached in a direction in which a difference between the two addresses is minimized so as to match the target address. 2. A first address generating means, and a constant phase difference for generating a predetermined number of constant phase difference signals corresponding to a value indicated by a lower order of the first address generated by the first address generating means. Signal generating means; second address generating means for generating a second address in synchronization with one cycle of the first address generating means; and the second address from the predetermined number of constant phase difference signals Selecting means for selecting and outputting a constant phase difference signal corresponding to a lower value of the counter; detecting means for detecting a match between an upper bit of the first address counter and an upper bit of the second address counter; Means for outputting a constant phase difference signal selected by the selection means at a timing coincident by the means, and based on a signal output by the second selection means. hand,
An image forming apparatus comprising: a driving unit that drives an image drawing surface in a sub-scanning direction; and a drawing unit that draws an image on the image drawing surface along a main scanning direction. 3. An image forming apparatus for forming an image by drawing a line in a main scanning direction on a drawing surface in synchronization with a main scanning synchronization signal and conveying the drawing surface in a sub-scanning direction to form an image. A driving unit that conveys a drawing surface in a sub-scanning direction with a reference signal having a predetermined period, a phase shift between the main scanning synchronization signal and the reference signal, and a timing of the reference signal to correct the phase shift. Selecting means for selecting a method that requires a shorter required time, either advancing or delaying in a stepwise manner, and phase correcting means for changing and outputting the phase of the reference signal based on a selection result by the selecting means. Image forming apparatus. 4. The apparatus according to claim 1, wherein the selection unit detects a main scanning synchronization signal immediately after detecting a sub-scanning synchronization signal indicating a predetermined position on the drawing surface, as a main scanning synchronization signal for detecting a phase shift. Item 4. The image forming apparatus according to Item 3. 5. The method according to claim 1, wherein the determining unit is configured to determine which one of a value to be added and a value to be subtracted from the set address corresponding to the phase of the reference signal so as to be a target address corresponding to the phase of the main scanning synchronization signal. Is small, and the phase correction means performs addition or subtraction on the set address by a predetermined unit in accordance with the result of the determination, and each time the set address changes, the reference of the phase corresponding to the address value is changed. The image forming apparatus according to claim 3, wherein the image forming apparatus outputs a signal. 6. The phase correction means includes phase difference waveform generation means for generating a plurality of constant phase difference waveforms having a fixed phase shift and corresponding to each value of the set address, respectively. 6. The image forming apparatus according to claim 5, wherein a reference signal corresponding to a phase of the constant phase difference waveform is output. 7. The phase difference waveform generating means includes: a first waveform generating means for generating a plurality of constant phase difference waveforms shifted by a predetermined time; and a phase difference waveform generated by the first waveform generating means. 7. The image forming apparatus according to claim 6, further comprising: a second waveform generating unit configured to generate a phase difference waveform delayed by a unit of a cycle. 8. An image forming apparatus for forming an image by drawing a line in a main scanning direction on a drawing surface in synchronization with a main scanning synchronization signal and conveying the drawing surface in a sub-scanning direction to form an image. Basic signal output means for outputting a synchronization signal; measurement signal output means for outputting a measurement signal having a predetermined period; phase difference signal generation means for generating a phase difference signal between a predetermined position on the drawing surface and the main scanning synchronization signal A correction signal output unit that outputs a correction synchronization signal having a period obtained by adding the period of the measurement signal and the period of the basic synchronization signal; and a phase difference signal generated by the phase difference signal generation unit. The phase difference measurement means for measuring the length of the measurement signal by the number of wavelengths of the measurement signal, When the phase shift is detected by the detection means, the wave number corresponding to the number measured by the phase difference measurement means Outputs correction synchronization signal An image forming apparatus comprising: a control unit that outputs the basic synchronization signal; and a driving unit that drives the drawing surface in a sub-scanning direction. 9. The measurement signal output unit, the basic signal output unit, and the correction signal output unit output a signal in synchronization with the same reference signal, and the measurement signal output unit outputs a start point of the phase difference signal. A basic measurement signal output unit that outputs a basic measurement signal in synchronization with the immediately following reference signal, a unit that determines whether an end point of the phase difference signal is the first half or the second half of the cycle of the basic measurement signal, Having the same cycle as the signal, starting from the second cycle of the basic measurement signal, ending with the end point of the phase difference signal if the end point of the phase difference signal is the first half of the cycle of the basic measurement signal, 9. The image forming apparatus according to claim 8, further comprising means for outputting a measurement signal that ends at the end point of the cycle of the basic measurement signal if the end point of the phase difference signal is the latter half of the cycle of the basic measurement signal. apparatus. 10. The image according to claim 1, wherein an image for each element color is formed on the drawing surface, and a color image is printed and recorded on the medium by overlapping the image. Forming equipment. 11. The image forming apparatus according to claim 1, wherein an image is formed by an electrophotographic method. 12. An image is formed by drawing a line in the main scanning direction on a drawing surface in synchronization with a main scanning synchronization signal and conveying the drawing surface in a sub-scanning direction in synchronization with a reference signal having a predetermined period. A method of controlling an image forming apparatus, comprising: detecting a phase shift between the main scanning synchronization signal and the reference signal; and correcting or phasing the timing of the reference signal in order to correct the phase shift. A control method for an image forming apparatus, comprising: a determination step of determining a method requiring a shorter required time; and a phase correction step of changing and outputting a phase of a reference signal based on a determination result by the determination unit. . 13. The main scanning synchronization signal for detecting a phase shift, wherein a main scanning synchronization signal immediately after detecting a sub-scanning synchronization signal indicating a predetermined position on the drawing surface is detected as the main scanning synchronization signal. Item 13. The method for controlling an image forming apparatus according to Item 12. 14. The method according to claim 1, wherein the determining step includes determining whether to set a target address corresponding to the phase of the main scanning synchronization signal with respect to a set address corresponding to the phase of the reference signal. Is small, and the phase correction step adds or subtracts one by one to the set address according to the result of the determination, and every time the set address changes, the reference signal of the phase corresponding to the address value is changed. The method of controlling an image forming apparatus according to claim 12, wherein: 15. The phase correcting step according to a phase of a constant phase difference waveform corresponding to the set address from a plurality of constant phase difference waveforms respectively shifted by a fixed time corresponding to each value of the set address. The method according to claim 14, wherein the selected reference signal is selected and output.