JPH10162582A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor memory which can perform stable sensing operations even when the data transmitting route is different or environmental condition varies by sending data to a sense amplifier circuit by transmitting enable signals through a signal line which is wired in the same form as that of a bit line. SOLUTION: Enable signals BSAEN and MSAEN are inputted to a bit-line sense amplifier circuit 139 by using a dummy bit line 144 which is not a metal passing line. An inverter 143 transmits its output through the dummy bit line 144 and inputs the enable signal BSAEN to a bit-line sense amplifier circuit 123. Inverters 145 and 147 input the enable signal MSAEN to a line sense circuit 139 by delaying the output signal of the inverter 143. Even when the transmitting timing of read-out data on the bit line 144 changes due to a process or environmental variation, the sensing margin of the sense amplifier becomes constant, because the enable signals also change identically.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a semiconductor memory.

[0002]

2. Description of the Related Art When data stored in an SRAM is read, it is amplified to a logic level by a sense amplifier. The first sense amplifier converts the differential data signal output from the data cell into an intermediate differential signal, and the second sense amplifier amplifies the intermediate differential signal to a logic level.

FIG. 1 is a circuit diagram of a peripheral circuit for explaining a conventional SRAM memory cell array and a data transmission path.

The peripheral circuit has a bit line sense amplifier circuit 123 and an input / output line sense amplifier circuit 139. The bit line sense amplifier 123 as the first sense amplifier is connected to the section data output lines SDL119 to SDL119.
SDLB121 and main data output line MDL125
, And transmits the intermediate differential signal to the input / output line sense amplifier circuit 139 through the main data output lines 125 to 127.

The memory cell array includes a precharge circuit 1
05, and a Y pass gate circuit 117. Each memory cell includes a latch circuit 109 and transmission MOS transistors 107, 1 for transmitting data to these.
And 11. Memory cell latch circuit 109
Is a flip-flop composed of two cross-connected inverters. The structure of such an SRAM is as follows.
U.S. Pat. No. 4,916,66, issued Apr. 10, 990
No. 8 “INTERNAL SYNCHRONIZATION TYPE MOS SRAM WITH
ADDRESS TRANSITION DETECTING CIRCUIT ”and“ 1985 INT
ERNATIONAL SOLID-STATE CIRCUITS CONFERENCE DIGEST
OF TECHNICAL PAPER pp 64, 65A 17ns 64K COMS RAM WI
TH A SCHMITT TRIGGER SENSE AMPLIFIER ”.

A precharge circuit (or equalize circuit) 105 is connected to a memory cell and generates a precharge signal for precharging a bit line or an equalize signal for equalizing a corresponding memory cell.

When any one of the multiple word lines is enabled, the data latched by the latch circuit 109 of the memory cell connected to the word line is read out to the bit lines BLn and BLBn. You. The data read to the bit lines BLn and BLBn is transmitted to the bit line sense amplifier circuit 123 via the Y pass gate circuit 117 and is amplified. At this time, the bit line sense amplifier circuit 123
The input / output line sense amplifier circuit 139 is controlled by a sense amplifier enable drive circuit 130 including an inverter delay chain circuit or a metal passing line. The sense amplifier enable drive circuit 130 outputs enable signals BSAEN and MSAEN by a NAND gate 129 and a number of inverters 131...
3 and 139 are controlled.

[0008]

In the sense amplifier circuit having such a structure, when sensing data, the timing at which data from the memory cell reaches the sense amplifier and the timing at which the sense amplifier enable signals BSAEN and MSAEN are enabled are determined. is important. Since the transmission path of the data from the memory cell to each sense amplifier is different from the transmission path of the sense amplifier enable signals BSAEN and MSAEN, there is a problem that the sensing margin of each sense amplifier changes due to a change in process or environmental conditions. .

Specifically, VCC = 3.1 V, Temp
Although data can be output normally under the slow environment condition of = 110 ° C., under the fast environment condition of VCC = 3.5 V and Temp = −10 ° C., the signals SAS165 and SA shown in FIG.
The sensing margin decreases due to the SB167 flip phenomenon. FIG. 3 shows signals 149 and 151 transmitted on lines SDL and SDLB, and FIG.
Signals 153 and 15 transmitted by L and MDLB
5 is shown. Under the fast environment condition, the operation is faster and the operation voltage is higher than under the slow environment condition. Therefore, in order to eliminate such a flip phenomenon, the sense amplifier enable signal may be delayed, but this has a disadvantage in that the overall operation speed is reduced.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor memory which can perform a stable sensing operation even when the data transmission path is different or the environmental conditions fluctuate without delaying the overall operation speed.

[0011]

In order to achieve the above object, a semiconductor memory according to the present invention provides an enable signal to a sense amplifier circuit for amplifying read data placed on a bit line and controls the operation of the semiconductor amplifier. The memory is characterized in that the enable signal is transmitted through a signal line having the same wiring form as a bit line and provided to a sense amplifier circuit. An enable signal is provided to the sense amplifier circuit using one or more dummy bit lines provided in the memory cell as signal lines. A bit line sense amplifier circuit for primary-amplifying read data placed on the bit line, and an input / output line sense amplifier circuit for secondary-amplifying data output from the bit line sense amplifier circuit; An enable signal is provided to the bit line sense amplifier circuit by a signal line having the same wiring form as that described above, and is provided to the input / output line sense amplifier circuit after being delayed.

The present invention is also characterized in that an enable signal is provided to the sense amplifier circuit through a transmission path having the same form as a data transmission path for reading data from a memory cell.
A dummy bit line provided in a memory cell is set to 1
The enable signal is provided to the sense amplifier circuit by utilizing the above-mentioned configuration.

[0013]

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings.

FIG. 2 is a schematic block diagram of a semiconductor memory using a dummy data line according to the present invention for a sense amplifier enable signal.

Subword lines SWL0,..., SWLn
, BLn, BLB
The gates and drain terminals of the transmission MOS transistors 107 and 111 are connected between n, and a source circuit of the transmission MOS transistors 107 and 111 is connected to a latch circuit 109 for latching and storing data. The latch circuit 109 has a flip-flop structure in which inverters are cross-connected, and complementary data is stored in the gates (first and second nodes) of two drive transistors. Such an SRAM unit cell and precharge circuit 10
5, Y pass gate circuit 117 and decoders 101, 10
3 (113, 115) is the same as that described in the prior art. Also, the section data line SDL11
9, SDLB121 and main data line MDL12
5, the MDLB 127 is connected to the bit line sense amplifier circuit 123 and the input / output line sense amplifier circuit 139.

The bit line sense amplifier circuit 123 is driven by the sense amplifier enable drive circuit 132 to amplify the read data to an intermediate differential signal, and the input / output line sense amplifier circuit 139 amplifies the intermediate differential signal to a logic level. I do. Sense amplifier enable drive circuit 1
32 enables the bit line sense amplifier circuit 123 and the input / output line sense amplifier circuit 139 by the enable signals BSAEN and MSAEN, and the circuit includes a NAND gate 141 and an inverter 14 which respond to a pulse.
3, 145 and 147.

Sense amplifier enable drive circuit 132
Can be configured as a conventional inverter delay chain circuit, but the enable signal BSA is generated by using a dummy bit line 144 which is not a metal passing line.
EN and MSAEN are connected to the bit line sense amplifier circuit 12
3 and input to the input / output line sense amplifier circuit 139.
Inverter 143 outputs its output to dummy bit line 1
44, and input the BSAEN to the bit line sense amplifier circuit 123. Inverters 145, 14
7 inputs the MSAEN to the input / output line sense amplifier circuit 139 with a delay in the output signal of the inverter 143.

At this time, a large number of dummy bit lines are arranged between the memory cell array region and the peripheral circuit region, and a dummy cell is formed between the dummy word line and the dummy bit line. This is to minimize the loading effect generated in the process, and the present invention uses the dummy bit line.
Therefore, even if the transmission timing of the read data on the bit line changes due to a process or environmental change, the enable signal also changes in the same manner, and the sensing margin of the sense amplifier becomes constant.

FIG. 6 to FIG.
It is a figure which shows each signal waveform applied to the fast environmental conditions of C = 3.5V and Temp = -10 degreeC. In this circuit, stable operation is performed under slow environmental conditions.

FIG. 6 shows the signals of SDL149 and SDLB151. The potential is amplified several nanoseconds faster than the slow condition, and the amplitude is increased by several volts. FIG. 7 shows MDL153 and M
The signal of the DLB 155 has a voltage similar to the voltage under the slow condition, and has a smaller amount of voltage change than the waveform of FIG. In addition, SAS16 which is the final signal
5. The waveform of SASB 167 is 31 in the waveform of FIG.
No flip phenomenon occurred between ns and 32 ns,
Performs stable sensing operation.

[0021]

As described above, according to the present invention, even if data transmission through a bit line changes due to process or environmental fluctuations, the enable signal to the sense amplifier also changes, so that the sensing margin of the sense amplifier is kept constant. Therefore, a sufficient sensing margin can be secured.

[Brief description of the drawings]

FIG. 1 is a main part circuit diagram of a conventional SRAM cell array and peripheral circuits.

FIG. 2 is a main part circuit diagram of a cell array and peripheral circuits of the SRAM of the present invention.

FIG. 3 is a signal waveform diagram applied to a fast environmental condition in a conventional SRAM circuit.

FIG. 4 is a signal waveform diagram applied to a fast environmental condition in a conventional SRAM circuit.

FIG. 5 is a signal waveform diagram applied to a fast environmental condition in a conventional SRAM circuit.

FIG. 6 is a signal waveform diagram applied to a fast environmental condition in the SRAM circuit of the present invention.

FIG. 7 is a signal waveform diagram applied to a fast environmental condition in the SRAM circuit of the present invention.

FIG. 8 is a signal waveform diagram applied to a fast environmental condition in the SRAM circuit of the present invention.

[Explanation of symbols]

 105 Precharge circuit 117 Y pass gate circuit 123 Bit line sense amplifier circuit 132 Sense amplifier enable drive circuit 139 Input / output line sense amplifier circuit

Claims (5)

[Claims] 1. A semiconductor memory for controlling the operation by providing an enable signal to a sense amplifier circuit for amplifying read data placed on a bit line, wherein the enable signal is transmitted by a signal line having the same wiring form as the bit line. A semiconductor memory characterized in that the semiconductor memory is provided to a sense amplifier circuit. 2. The semiconductor memory according to claim 1, wherein an enable signal is provided to the sense amplifier circuit by using at least one dummy bit line provided in the memory cell as a signal line. 3. A bit line sense amplifier circuit for primary amplifying read data placed on a bit line, and an input / output line sense amplifier circuit for secondary amplifying data output from the bit line sense amplifier circuit. 3. The semiconductor according to claim 1, further comprising: a signal line having the same wiring form as the bit line to provide an enable signal to the bit line sense amplifier circuit and delay the enable signal to provide the input / output line sense amplifier circuit. memory. 4. A semiconductor memory, wherein an enable signal is provided to a sense amplifier circuit through a transmission path having the same form as a data transmission path for reading data from a memory cell. 5. The semiconductor memory according to claim 4, wherein an enable signal is provided to the sense amplifier circuit using at least one dummy bit line provided in the memory cell.