JPH10162571A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain semiconductor device which is free from malfunctions and faults and can be integrated highly in a higher reliable state by making the potential at a word line sufficiently higher and the electric field between the gates and sources or drains of MOS transistors of memory cells weaker in accordance with written information. SOLUTION: When the writing potential of storage information in memory cells M0-Mn is high, the writing potential is impressed upon the capacitors C0-Cn of the cells M0-Mn when the potential at a word line is a high value Vch . When the writing potential of the storage information in the cells M0-Mn is low, the writing potential is impressed upon the capacitors C0-Cn when the potential at the word line is an intermediate value Vc . Since the potential at the word line can be made sufficiently higher in accordance with the information written in the memory cells M0-Mn, the potential impressed upon the capacitors C0-Cn of the cells M0-Mn does not drop. In addition, since the wiring potential is not impressed when the potential at the word line is the high value Vch and the writing potential is low, the electric field impressed upon a gate oxide film, etc., becomes weaker.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
The present invention relates to a semiconductor device having a semiconductor memory circuit including an S transistor and a capacitor, and more particularly to a semiconductor device capable of high integration without deteriorating reliability.

[0002]

2. Description of the Related Art DRAM (Dynamic Random Access Memor)
The memory cell of y) is composed of one MOS transistor and one capacitor. Writing of storage information to a memory cell is performed by storing a high potential or a low potential applied to a bit line in a capacitor via a MOS transistor and holding the same. The amount of charge stored in the capacitor decreases due to a decrease in the potential of the word line which rises at the time of writing.

[0005] Therefore, the potential of the word line is higher than the high potential, which is the write information, by a threshold voltage or more. Regarding such technology, see "IEEE
JOURNAL OF SOLID-STATE C
IRCUITS, VOL. 26, NO. 4, APRI
L 1991 ". However, in this technique, when the potential to be written to the memory cell is high, the potential difference from the word line potential is small, so that the writing potential may decrease. When the word line potential decreases in this manner, the write potential becomes insufficient, the memory cell signal during the read operation decreases, and a malfunction of the semiconductor device is caused. In order to avoid such a problem, it is necessary to increase the word line potential.

On the other hand, DRAMs suitable for high integration have been further increased in capacity due to advances in miniaturization technology. With this miniaturization technique, the gate oxide film becomes thinner, and the withstand voltage of the film decreases. In particular, when the potential to be written to the memory cell is low, the potential difference from the high potential of the word line is large,
When the high potential of the word line is increased, the electric field between the gate and the source or drain of the MOS transistor becomes large, and the gate oxide film may be broken or deteriorated.

[0005]

The problem to be solved is that, in the prior art, if the word line potential is increased in order to apply a sufficient write potential to the capacitor of the memory cell, the gate oxide film will not be formed. The point is that the pressure resistance cannot be guaranteed. SUMMARY OF THE INVENTION An object of the present invention is to solve these problems of the prior art and to provide a semiconductor device capable of high reliability and high integration without malfunction and failure.

[0006]

In order to achieve the above object, a semiconductor device according to the present invention comprises (1) a plurality of pairs of bit lines Bt and Bb and a plurality of word lines W arranged in a matrix.
0 to Wn, the word lines W0 to Wn and the bit lines Bt and Bt.
b, memory cells M0 to Mn including charge transfer MOS transistors N0 to Nn and information storage capacitors C0 to Cn, and sense amplifiers St and Sb connected between a pair of bit lines Bt and Bb. A semiconductor device having at least a circuit for reading and writing information stored in memory cells M0 to Mn, wherein the potentials of word lines W0 to Wn are output in time series to a high potential Vch, an intermediate potential Vc, and a low potential Vss. A high-potential stored information when the word lines W0 to Wn are set to the high potential Vch by the word line potential control circuit WVC and a low potential when the intermediate potential Vc is set. Cells M0 to Mn
By providing a write control circuit WRC for writing data to the memory cell and changing the potential of the word line in accordance with the information to be written, the potential of the word line can be sufficiently increased in accordance with the information to be written and applied to the capacitor of the memory cell. The write potential can be prevented from lowering, and the electric field between the gate and the source or the drain of the MOS transistor of the memory cell can be made smaller than before, so that the destruction and deterioration of the gate oxide film can be suppressed. It is characterized by being able to. (2) In the semiconductor device according to the above (1), the sense amplifiers St and Sb may include:
A first sense amplifier (sense amplifier S) that amplifies a high-potential memory cell signal output from memory cells M0 to Mn.
P) and a second sense amplifier (sense amplifier SN) for amplifying a low-potential memory cell signal output from the memory cells M0 to Mn. The write control circuit WRC controls the drive of the sense amplifiers SP and SN. During the setting of the word line high potential by the word line potential control circuit WVC, the operation of amplifying the memory cell signal by the sense amplifier SP is completed;
While the word line potential control circuit WVC sets the intermediate potential of the word line, the operation of amplifying the memory cell signal by the sense amplifier SN is completed. (3) In the semiconductor device according to any one of the above (1) and (2), the word line potential control circuit WVC uses a row address strobe signal (/ RAS, where "/" means low active). ) Detect rising and falling of / RAS
Based on the detection means (timing circuit TC) and the detection result of the timing circuit TC, the word line is connected to a high potential power supply (V
ch) or an intermediate potential power supply (Vc) for switching to and connecting to the potential switch (switching circuit SW)
And at least Also, (4)
In the semiconductor device described in (3), the write control circuit WRC has at least a switching detection unit (an inverter I2 and a NAND gate NAN) that detects a switching operation of a connection destination of a word line by the switching circuit SW,
In response to the detection result by the inverter I2 and the NAND gate NAN, at least writing control of memory information of low potential to the memory cell is performed.
(5) In the semiconductor device according to any one of the above (1) and (2), the word line potential control circuit WVC
Is a delay circuit DC0 for delaying transmission of a previously generated signal R for a predetermined time, and a directly generated previously generated signal R
And NAN of signal R input via delay circuit DC0
A NAND gate NT1 for performing a D operation, and potential switching means (switching circuit SC, word driver WD) for switching the word line to either a high potential power supply or an intermediate potential power supply based on the output of the NAND gate NT1
C), wherein the word line is connected to the high potential power supply, and then switched to the intermediate potential power supply after a lapse of a predetermined time by the delay circuit DC0. (6) In the semiconductor device according to any one of (1) to (5), when information is input from outside the semiconductor device, the high potential VH and the intermediate potential Vp are generated, and the information from outside is generated. If the potential is high, the high potential VH is output to the bit line to which the memory cell for storing this information is connected, and the intermediate potential Vp is output to a pair of bit lines. Is applied to a bit line to which a memory cell for storing data is connected, and a high potential Vp is applied to a pair of bit lines.
H for outputting external information (writing circuit W
C), if low-potential information is input from outside the semiconductor device, the sense amplifier SN is activated and the intermediate potential is set when setting the intermediate potential of the word line to which the memory cell is connected by the word line potential control circuit WVC. Vp is amplified to a low potential and applied to the memory cell M0. Also,
(7) In the semiconductor device according to any one of the above (1) to (6), the period for maintaining the high potential of the word line at the time of outputting information to the outside of the semiconductor device is defined by the period from the outside of the semiconductor device. Potential holding time control means (potential holding time control circuit OS, or switch elements ST and SB and switch control circuit BT) which is set to be shorter than the period for maintaining the high potential of the word line when the information is input. It is characterized by the following. (8) In the semiconductor device described in (7), the potential maintaining time control means (potential maintaining time control circuit OS) includes a / WE detecting means (inverters IW1 and IW2) for detecting a write enable signal (/ WE). ), And if the result of detection of the write enable signal by the / WE detecting means is a read operation instruction, timing control means (switch SW2, switch SW1; And a delay circuit DC1). Also,
(9) In the semiconductor device described in (7), the potential maintaining time control means includes switching means (switch elements ST and SB) for controlling connection between the memory cell and the sense amplifier in each of the bit line pairs; And at least a switch control circuit BT for turning off the switch elements ST and SB when the high-potential amplification by the sense amplifier SP is completed at the time of outputting information to the outside of the device. After the connection between the cell and the sense amplifier is cut off, low potential amplification is performed by the sense amplifier SN, and information is output to the outside of the semiconductor device.

[0007]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a circuit diagram showing a first embodiment of a configuration according to the present invention of a semiconductor device of the present invention. In FIG. 1, Bt and Bb indicate bit lines, W0 to Wn indicate word lines, and M0 to Mn indicate memory cells, respectively.
PC is a precharge circuit, SP is a bit line Bt,
A sense amplifier as a first sense amplifier of the present invention for amplifying the Bb pair to a high potential, SN is a sense amplifier as a second sense amplifier of the present invention for amplifying the bit lines Bt and Bb pair to a low potential, St, Sb is a column selection signal (YS0 to YS)
n) are transfer MOS transistors (transfer gates) selected by n), and these circuit groups are arrays A0 to An. WVC is a word line potential control circuit according to the present invention, and WRC is a write control circuit according to the present invention.

The sense amplifier SP is connected to a common source line CP
Is connected to the PMOS transistor PS via the
The gate of the S transistor PS is connected to the output of the inverter IP. Similarly, the sense amplifier SN is connected to the NMOS transistor NS via a common source line CN, and the gate of the NMOS transistor NS is connected to the inverter I
It is connected to the output of the NAND gate NAN via N. The bit lines Bt and Bb are connected to input / output lines (hereinafter, referred to as IO lines) IOt and IOb via transfer MOS transistors St and Sb, respectively.
b is connected to the main amplifier MA and the write circuit WC.

The main amplifier MA outputs information stored in the memory cell to the outside of the semiconductor device, and the write circuit WC writes information outside the semiconductor device to the memory cell. The plate line PL of the memory cell is connected to a plate voltage source VPL that supplies a plate voltage. The gates of the transfer MOS transistors St and Sb are connected to column selection lines YS0 to YSn that propagate the output of a column selection decoder (not shown). The word lines W0 to Wn are connected to the output of the word driver WD, and the input of the word driver WD is connected to the output of the row decoder XD. The word driver WD is an inverter including a PMOS transistor and an NMOS transistor, and receives a word line drive signal Fw at a source of the PMOS transistor.
As inputs to the row decoder XD, addresses ax0 to axn
Are selectively input.

The operation of the circuit will be described below assuming that word line W0 is selected. Note that the word driver WD and the output circuit Iw are inverters composed of a PMOS transistor and an NMOS transistor, and respectively control the sources of the PMOS transistors. First, in order to select the word line W0, the addresses ax0 and ax1, which are input signals of the row decoder XD, are set to High level.
As a result, the input of the word driver WD becomes Low level, and the PMOS transistor is activated. That is, the word line W0 is connected to the connection line for transmitting the word line drive signal Fw, and the word line W0 is connected to the word line drive signal Fw.
w is propagated.

The word line drive signal Fw is generated by the word line potential control means WVC according to the present invention as follows. First, when a row address strobe signal (/ RAS) is input from outside the semiconductor device to the timing circuit TC as the / RAS detection means of the present invention, the timing circuit TC determines the falling timing of the signal (/ RAS). And the rising timing is detected, and the waveform of the output signal is shaped and output to the switching circuit SW as the potential switching means of the present invention. Note that "/" in "/ RAS" or the like indicates low active.

When the signal (/ RAS) from the timing circuit TC falls, the switching circuit SW switches to the node N.
2 is at a low level, and the node N1 is at a high level. As a result, the PMOS transistor Phh is turned on, and the PMOS transistor Pcc is turned off. Conversely, when the signal / RAS rises, the PMOS transistor Ph
h is turned off, and the PMOS transistor Pcc is turned on. In this embodiment, the input signal of the timing circuit TC is set to / RAS, but another row-related control signal may be used.

On the other hand, in order to select the word line drive signal Fw, the input address signals a0, a of the NAND gate NA are selected.
1 are both at a high level, and the output of the NAND gate NA is at a low level. The latch circuit LC uses this NA
This circuit latches the output of the ND gate NA, and propagates the output of the NAND gate NA to the input of the output circuit Iw. Thereby, the PMOS transistor of the output circuit Iw is activated. Here, row address strobe signal / RAS has fallen in advance, word line drive signal Fw attains high potential Vch, and the potential of selected word line W0 also attains high potential Vch. Therefore, the charge transfer MOS transistor N0 of the memory cell M0 connected to the word line W0 is activated.

The bit lines Bt, Bt,
The Bb pair is charged to the precharge level Vp by the precharge circuit PC before the word line W0 becomes the high potential Vch. Then, the potential of the word line W0 becomes high potential V
When the channel becomes ch, the storage information (memory cell signal) of the memory cell M0 is output to the bit line Bt. Here, when the signal FS of the write control circuit WRC becomes High level, the PMOS transistor PS is activated, and the sense amplifier SP is driven. When the potential to be written to the memory cell is high, the data is “1”, and when the potential to be written to the memory cell is low, the data is “0”. When the storage information of the memory cell is “1”, the sense amplifier SP , The bit line Bt is amplified to a high potential, and the paired bit line Bb is held at the precharge level Vp.

When the information stored in the memory cell is "0", the sense amplifier SP holds the bit line Bt at a potential lower than the precharge level Vp by the amount of the memory cell signal. Amplified to high potential. When the bit line Bb is amplified to a high potential in this manner, the precharge level Vp of the common source CN attempts to increase the potential. However, the precharge level Vp is maintained because the NMOS transistor DN is in a normal conduction state. When reading information stored in a memory cell in this way, usually,
One of the column selection signals YS0 to YSn is High.
Level, and the signal of the selected bit line pair Bt, Bb is output to the IO line and output to the outside of the semiconductor device via the main amplifier MA. Also, in the page mode,
The column selection signals YS0 to YSn are sequentially selected, and the bit line pair B
The signals t and Bb are sequentially output to the IO line.

Next, a row address strobe signal / RAS
Rises to the High level at the end of the column selection. In this way, when the signal (/ RAS) becomes High level, the node N2 is set to High level via the timing circuit TC and the switching circuit SW, and the node N1 is set to Low level. As a result, the word line drive signal Fw becomes the intermediate potential Vc, and the word line W0 also becomes the intermediate potential Vc. Here, when the node N1 goes low, the output of the inverter I2 of the write control circuit WRC goes high, and the output of the NAND gate NAN goes low. Thereby, the common source line C
The NMOS transistor DN holding N at the precharge level Vp becomes non-conductive, and the NMOS transistor NS is activated.

When the common source line CN drops to the low potential VL, the sense amplifier SN is driven, and the bit line pair B
The signal difference between t and Bb is amplified to a low potential. After that, the address signals a0 and a1 become High level, the word line drive signal Fw is set to the ground level, and the word line W0 is also set to the ground level. In this embodiment, the low potential of the word line is set to the ground level. However, the present invention is not limited to this. Further, the low potential amplified by the sense amplifier SN may be the same as the low potential of the word line, or may be other than that.

In a write operation, a write circuit WC for writing information from outside the semiconductor device to a memory cell outputs a high potential and an intermediate potential. Hereinafter, description will be made assuming that the word line W0 is selected. Word line W0 is at high potential Vch
At this time, one of the output potentials of the write circuit WC is applied to the capacitor of the memory cell, and the other output potential is applied to the other of the paired bit lines. When the information to be written has a high potential, the above operation can apply a potential to the capacitor of the memory cell. However, when the information to be written has a low potential, the write circuit WC temporarily writes an intermediate potential to the memory cell M0 via the bit line Bt, for example, and applies a high potential to the bit line Bb forming a pair. When the word line W0 reaches the intermediate potential Vc, the sense amplifier SN
Of the capacitor C0 of the memory cell M0.
Is written with a low potential.

As described above, in the semiconductor device of this embodiment,
The word line potential is changed in time series into a high potential Vch, an intermediate potential Vc,
When the potential is switched to the low potential Vss and the storage information to be written to the memory cells M0 to Mn is at the high potential, the word line
Is applied to the capacitors C0 to Cn of the memory cells M0 to Mn when the word line is at the intermediate potential Vc, the stored information is applied to the capacitors C0 to Cn of the memory cells M0 to Mn. Apply. Thereby, the potential of the word line can be made sufficiently high in accordance with the information to be written in the memory cells M0 to Mn.
To Mn of the capacitors C0 to Cn do not decrease.

When the word line is at the high potential Vch, a low write potential is not applied, so that the electric field applied to the gate oxide film is smaller than in the prior art. As a result, a sufficient write potential can be applied to the capacitor of the memory cell, and a semiconductor device in which the gate oxide film is less likely to be broken or deteriorated can be obtained. And the reliability of the system using this semiconductor device can be improved. In circuits other than memory cells, such as the word driver WD, a high potential Vch is applied to the gate oxide film. However, the probability of the gate oxide film being broken or deteriorated depends on the layout area ratio and the memory cell array. Is overwhelmingly large, so that if an excessive electric field is applied to the memory cell, the failure of the semiconductor device can be reduced.

Next, the operation of the semiconductor device of this embodiment according to the present invention will be described with reference to FIG. FIG. 2 is an explanatory diagram showing an operation example according to the present invention of the semiconductor device in FIG. This example shows a read operation waveform in the page mode, which is also a rewrite operation waveform. In the figure, / R
AS is a row address strobe signal, Wn is the potential of a word line, B is the potential of a bit line Bt to which a memory cell is connected, / B is the potential of a bit line paired with the bit line Bt, Y
S0 to YSn indicate column selection signals, respectively. This operation waveform shows a case where data “1” is written in the memory cell.

When row address strobe signal / RAS is Hi
During the gh level period, the bit line pair Bt, Bb is precharged to the precharge level Vp. When the signal / RAS falls to the low level, the potential of the word line rises to the high potential Vch. A memory cell signal Vs, which is information stored in a memory cell ([1]), is output as the potential B of the bit line Bt. This memory cell signal Vs is
The signal is amplified to the high potential VH by the sense amplifier SP in FIG.

At this time, if the word line voltage W satisfies the following relational expression, a sufficient write voltage can be applied to the capacitor of the memory cell. Vch> VH + Vth (A) Vth is a threshold voltage of the MOS transistor for charge transfer. Here, when the column selection signals YS0 to YSn are selectively applied to a high potential, the potential difference (B, / B) of the bit line pair is output to the IO line in FIG. It is read out as stored information outside the device. In the page mode, the column selection signals YS0 to YS
By sequentially selecting n, stored information is sequentially read out of the semiconductor device.

When such column selection is completed, the word line W
n is lowered to the intermediate potential Vc, and the sense amplifier SN of FIG. 1 is driven to amplify the potential / B of the bit line Bb to the low potential VL. At this time, if the word line voltage Wn satisfies the following relational expression, a sufficient write voltage can be applied to the capacitor of the memory cell. Vc> VL + Vth (B) Then, if the potential of the word line is lowered to the low potential Vss while the write potential is applied to the capacitor, the write operation of the stored information is completed.

In this embodiment, the information stored in the memory cell is at a high potential. However, the operation may be performed in the same manner even when the stored information is at a low potential. Further, in this embodiment, the low potential of the word line is set to the ground potential. However, the present invention is not limited to this. Further, a PMOS transistor may be used as the MOS transistor for charge transfer of the memory cell, and the voltages of the word line and the bit line may be inverted voltages.
Furthermore, although the folded bit line configuration is used in this embodiment, an open bit line configuration may be used.

As described above, in the first embodiment, when the word line is at a high potential, the bit line of the memory cell does not go to a low potential, so that a voltage is applied between the gate and the source or drain of the MOS transistor for charge transfer. No excessive electric field is applied. As a result, destruction and deterioration of the gate oxide film hardly occur. Further, since the word line potential is sufficiently increased in accordance with the stored information, the potential applied to the capacitor is not reduced.

FIG. 3 is a circuit diagram showing a semiconductor device according to a second embodiment of the present invention. In the figure, Bt and Bb are bit lines, W0 to Wn are word lines, M
0 to Mn are memory cells, Di is input data, Do
Indicates output data. Further, PC is a precharge circuit, SP is a sense amplifier as a first sense amplifier of the present invention which amplifies to a high potential, and SN is a sense amplifier as a second sense amplifier of the present invention which amplifies to a low potential.

The sense amplifier SP has a common source line CP
Is connected to the PMOS transistor PS via the
The gate of the S transistor PS is connected to the output of the inverter IP. Similarly, the sense amplifier SN is connected to the NMOS transistor NS via a common source line CN, and the gate of the NMOS transistor NS is connected to the inverter I
It is connected to the output of the NAND gate NAN via N. Bit lines Bt and Bb are connected to IO lines (input / output lines) IOt and I via transfer MOS transistors St and Sb.
Ob, and the IO lines IOt and IOb are connected to a main amplifier MA and a writing circuit WC as an external information writing unit of the present invention.

The plate line PL of the memory cell is connected to a plate voltage source VPL for supplying a plate voltage.
The gates of the transfer MOS transistors St and Sb are connected to a column selection line YSn that propagates the output of a column selection decoder (not shown). In addition, word lines W0 to W0
Wn is connected to the output of the sub-word driver SWD. The sub-word driver SWD includes a row decoder XDE
C output signals MWt, MWb and word line drive signal Fw
Are connected. This word line drive signal Fw
Is an output signal from the word potential control circuit according to the present invention constituted by the word driver WDC, the switching circuit SC, and the timing circuit TC.

The operation of each circuit of this embodiment will be described below on the assumption that the word line W0 is selected. First, in order to select the word line W0, the input signal addresses a1 to a3 of the row decoder XDEC are all set to High level. As a result, the output signal MWb of the NAND gate NA1 becomes L
low level, the output signal MWt of the inverter I1 is High.
h level. Receiving these output signals MWb and MWt, the PMOS transistor PW and the NMOS transistor NWt constituting the sub-word driver SWD are activated and become a normal conduction state, and the NMOS transistor NWb is turned off. That is, the word line W0 is connected to the output of the word driver WDC, and propagates the word line drive signal Fw.

Next, the word line drive signal Fw is output as follows. The signal R for controlling the timing circuit TC is a signal generated from the row address strobe signal / RAS, and is input at a low level during precharge. The address signals ax1 and ax2 are input at a low level. Further, a low level is also input to the precharge signal Xp. Therefore, the NMOS transistor NW0 is conductive, the PMOS transistor PW0 is nonconductive, and the word line drive signal Fw is also at the Low level.
Therefore, the word line W0 is at a low potential. Here, when the address signals ax1 and ax2 are set to High level, the node a is set to Low level, and the NMOS transistor NW
0 is non-conductive, and the PMOS transistor PW0 is conductive.

At this time, since the PMOS transistor Phh is conducting, the word line drive signal Fw is at the high potential Vc.
Output h. Therefore, the word line W0 has the high potential Vch. When the potential of the word line increases in this way, a memory cell signal is output to the bit line Bt as storage information of the memory cell. Here, when the signal FP is set to the high level, the sense amplifier SP is activated, and the sense amplifier SP amplifies the signal difference between the pair of bit lines Bt and Bb to a high potential. Note that the signal FN is also set to the high level at the same time as the signal FP, but since the node N1 is at a high potential, NAN
The output of the D gate NAN becomes High level, and the sense amplifier SN is inactive.

As described above, the period in which the word line maintains the high potential Vch is a period in which at least one of the two inputs of the NAND gate NT1 is at the low level. Therefore, when the signal R is set to High level, NAN
One of the inputs of the D gate NT1 becomes High level,
The other is the delay time (td) of the delay circuit DC0 according to the present invention.
0) After that, the level changes from low to high. In response to these input signals, the output of the NAND gate NT1 according to the present invention switches to the low level, and the inverter IS of the switching circuit SC which partially constitutes the potential switching means of the present invention.
The outputs of 0 and IS1 also switch.

When these signals are switched, the node N2 of the word driver WDC which constitutes the potential switching means of the present invention together with the switching circuit SC is Low.
To the High level, and the PMOS transistor Ph
h is turned off, the node N1 changes from high to low level, and the PMOS transistor Pcc is turned on.
That is, the word line drive signal Fw outputs the intermediate potential Vc, and the word line W0 has the intermediate potential Vc.

When the node N1 changes from High to Low level, the node N1 is connected to the node N1 via the inverter I2.
The output of the ND gate NAN switches to Low level,
The output of the inverter IN switches to a high level.
As a result, the sense amplifier SN is activated, and amplifies the signal difference between the pair of bit lines Bt and Bb to a low potential. If the addresses ax1 and ax2 and the precharge signal Xp are set to Low level after the sense amplifier SN completes the voltage amplification, the word line W0 becomes low potential. In this embodiment,
Although the low potential of the word line is set to the ground potential, the invention is not limited to this.

Next, the write operation of this embodiment will be described. In the write operation, one of the high potential VH and the intermediate potential VP of the write potential output from the write circuit WC is applied to the capacitor of the memory cell when the word line is at the high potential Vch, and the other write potential forms a pair. Applied to the other bit line. When the writing potential is high, the writing operation can be applied to the capacitor of the memory cell by the above operation. However, when the writing potential is low, the intermediate potential VP is temporarily applied to the capacitor of the memory cell, the potential of the word line is set to the intermediate potential, and then applied to the capacitor using the low potential amplification of the sense amplifier SN. Thereafter, when the word line is set to a low potential, the write operation is completed.

During a read operation, the write circuit W
The output node of C must be high impedance. Therefore, when the write enable signal / WE is at a high level, the PMOS transistor and the NMOS transistor that output a signal to the IO line are turned off. As described above, in the second embodiment, the word line potential is switched to the high potential, the intermediate potential, and the low potential in a time series, and when the storage information to be written to the memory cell is at the high potential, the word line potential is switched to the high potential. When the potential applied to the capacitor of the memory cell and the storage information to be written to the memory cell is low, the potential is applied to the capacitor of the memory cell when the word line is at the intermediate potential.

Next, the operation of the semiconductor device of this embodiment according to the present invention will be described with reference to FIG. FIG. 4 is an explanatory diagram showing an operation example of the semiconductor device in FIG. 3 according to the present invention. This example shows operation waveforms, and FIG. 4A shows an operation for writing information from outside the semiconductor device to a memory cell. FIG. 4B shows an operation for reading information stored in a memory cell and an operation for rewriting information stored in a memory cell. The horizontal axis represents time, and the vertical axis represents voltage.

In this operation waveform, the voltage W of the word line, the voltage B of the bit line to which the memory cell is connected, the voltage / B of the bit line paired with the bit line, the column selection signal Ys output by the column decoder Is schematically shown. In the writing operation illustrated in FIG. 4A, description is given on the assumption that stored information held by a memory cell is at a high potential and information to be written is at a low potential. First, the memory cell signal Vs is output as the bit line voltage B before the word line potential reaches the high potential Vch. This memory cell signal Vs is amplified to the high potential VH by the sense amplifier SP of FIG. At this time, if the voltage W of the word line satisfies the above expression (A), a sufficient write voltage can be applied to the capacitor of the memory cell.

Next, when the column selection signal Ys is applied to a high potential, the bit line pair is connected to the output of the write circuit WC via the IO lines IOt and IOb. In order to make the information to be written have a low potential, an intermediate potential (VP) is once applied to the capacitor of the memory cell, and a high potential / B (VH) is applied to the other of the paired bit lines. Thereafter, the word line potential W is dropped to the intermediate potential Vc, and the sense amplifier SN in FIG. 3 is driven to amplify the bit line potential B to the low potential VL. At this time, if the voltage W of the word line satisfies the above expression (B), a sufficient write voltage can be applied to the capacitor of the memory cell.

When the potential of the word line is lowered to a low potential while maintaining the write potential, the write operation of the stored information is completed. In this embodiment, the storage information of the memory cell is set to a high potential and the write information is set to a low potential. However, the operation of the circuit may be performed in the same manner even when the storage information is set to a low potential and the write information is set to a high potential. Further, even when the storage potential and the write potential are the same, the operation of the circuit may be performed in the same manner.

As described above, in the second embodiment, the period during which the high potential of the word line is held is determined by the delay time of the delay circuit, and therefore the row address strobe signal / RAS or the like input from outside the semiconductor device is used. Even if the phase shift occurs, the period during which the word line maintains the high potential does not deviate. That is, the period in which the word line is at a high potential is extended, and does not overlap with the period in which the bit line is at a low potential. Thus, no excessive electric field is applied between the gate and the source or the drain of the MOS transistor for charge transfer. Therefore, destruction and deterioration of the gate oxide film hardly occur. Further, since the word line potential is sufficiently increased according to the stored information, the potential applied to the capacitor is not reduced.

FIG. 5 is a circuit diagram showing a semiconductor device according to a third embodiment of the present invention. This embodiment is the same as the embodiment shown in FIG. 3 except that a circuit for switching the signal delay time according to the operation mode is added to the embodiment shown in FIG. In the present embodiment, the potential maintaining time control circuit OS according to the present invention receives the write enable signal / WE as an input, and the complementary signals W and / W are output by the inverters IW1 and IW2 as the / WE detecting means of the present invention.
Generates W. Further, the signal R is input to the timing circuit TC through a path including the delay circuit DC1 and the switch SW1 or a path including only the switch SW2, which constitutes the timing control unit of the present invention. The switch SW1 is connected by the signal W output from the inverter IW1 when the write enable signal / WE is at a low level, and is disconnected when the write enable signal / WE is at a high level. The switch SW2 performs the reverse operation of the switch SW1 by the inverter IW2.

At the time of the write operation, the write enable signal / WE is at the low level, the switch SW1 is closed,
Switch SW2 is open. Therefore, since the signal R passes through the delay circuit DC1, the switch SW1, and the delay circuit DC2, the signal R arrives at the input of the NAND gate NT1 later, and the period during which the word line W0 is maintained at a high potential becomes longer. On the other hand, during the read operation, the write enable signal /
WE is at a high level, and the switch SW2 is closed. Therefore, the signal R passes through only the delay circuit DC2 and reaches the input of the NAND gate NT1. Therefore, the period during which the word line W0 is maintained at a high potential is short, and the time when the sense amplifier SN is driven is earlier than in the read operation. As a result, the time when the column selection signal YSn is set to the High level can be earlier, and the information stored in the memory cell can be read out quickly.

Next, the operation of the semiconductor device of this embodiment according to the present invention will be described with reference to FIG. FIG. 6 is an explanatory diagram showing an operation example according to the present invention of the semiconductor device in FIG. This example shows operation waveforms, and FIG. 6A shows an operation for writing information from outside the semiconductor device to the memory cells. FIG. 6B shows an operation for reading information stored in a memory cell and also an operation for rewriting information stored in a memory cell. The horizontal axis represents time, and the vertical axis represents voltage. In the read operation in FIG. 6B, the write operation (a) in FIG.
As compared to the case, the period during which the word line W is maintained at the high potential Vch is shorter (only “td2” with respect to “td1 + td2”), and the potential of the word line is set to the intermediate potential Vc earlier.

In the write operation shown in FIG. 6A, the bit line is selected by the column selection signal Ys, and the word line potential W is maintained at the high potential Vch until the write circuit applies a write potential to the memory cell. Must. This maintaining period corresponds to the delay circuit DC1 in FIG.
And the delay time td2 of the delay circuit DC2. On the other hand, in the read operation shown in FIG. 6B, in order to read out the storage information of the memory cell as quickly as possible, the period in which the potential W of the word line is maintained at the high potential Vch is set by the delay circuit DC2 of FIG. Only time td2 is set.

As described above, in the third embodiment, the period during which the high potential Vch of the word line is maintained is changed according to the operation mode of the semiconductor device, and during the read operation, the potential of the word line is changed to the intermediate potential Vc earlier. The timing at which the sense amplifier SN of FIG. 5 amplifies to a low potential is advanced, and the timing of reading stored information to the outside is advanced. Thus, FIGS. 1 and 3
As in the first and second embodiments, the gate oxide film can be prevented from being broken or deteriorated without lowering the rewrite potential, and the read time can be shortened.

FIG. 7 is a circuit diagram showing a fourth embodiment of the configuration according to the present invention of the semiconductor device of the present invention. The semiconductor device according to the present embodiment has a circuit (switch elements ST, SB, switch control circuit BT, etc.) as potential maintaining time control means of the present invention for switching a signal delay time according to an operation mode, similarly to the embodiment shown in FIG. ). That is, in the present embodiment, the switch elements ST and SB composed of NMOS transistors are provided between the bit lines Bt and Bb connecting the plurality of memory cells M0 to Mn and the bit lines bt and bb connecting the sense amplifiers SP and SN. And then,
A switch control circuit BT for controlling these switch elements ST and SB is added, and a NA is set so that the sense amplifier SN operates in response to an output signal of the switch control circuit BT.
An ND gate NR is added. Other configurations are the same as those of the embodiment in FIG.

With such a configuration, in the semiconductor device of this embodiment, the switching elements ST and SB
Between bit lines (bit lines Bt and Bb and bit line b
(between t and bb), and then drive the sense amplifier SN that amplifies to a low potential. That is, first, in the write operation, the write enable signal / WE is set to Lo.
The switch control circuit BT applies a high level to the gates of the switch elements ST and SB. As a result, the switch elements ST and SB are in the normal conduction state, and the bit line pairs Bt and bt, and Bb and bb are connected, respectively, and perform the same operation as in each of the embodiments shown in FIGS.

On the other hand, in the read operation, the signal FP goes low after the word line goes high.
Level, and the sense amplifier SP amplifies the memory cell signal to a high potential. On the other hand, when the signal FP becomes High level, the delay time td3 of the delay circuit DC3 elapses and N
The input of the AND gate NT2 is set to High level. The other input of the NAND gate NT2 is also at H level because the write enable signal / WE is already at High level.
high level, and its output Fc goes low, and N
The MOS transistors ST and SB are turned off. That is, the bit line Bt and the bit line bt and the bit line B
b and the bit line bb are cut off.

Thereafter, the sense amplifier SN is driven after the delay time of the delay circuit DC4 has elapsed, and the bit line pair bt, bb is driven.
Is amplified to a low potential. At this point, the column selection signal Y
By bringing Sn to a high level, the bit line pair b
The signals t and bb are read out to the IO lines (IOb and IOt) and read out of the semiconductor device via the main amplifier MA. To rewrite the memory cell at a low potential, the word line is set to the intermediate potential Vc, and then the switch elements ST and S
B may be made conductive. As described above, in the fourth embodiment, stored information can be read quickly without changing the period during which the potential of the word line is maintained in accordance with the operation mode.

Next, the operation of the semiconductor device of this embodiment according to the present invention will be described with reference to FIG. FIG. 8 is an explanatory diagram showing an operation example of the semiconductor device in FIG. 7 according to the present invention. This example shows operation waveforms, and FIG. 8A shows an operation for writing information from outside the semiconductor device to the memory cells. FIG. 8B illustrates an operation for reading out information stored in a memory cell and an operation for rewriting information stored in a memory cell. The horizontal axis represents time, and the vertical axis represents voltage. In this example, as shown by the broken line (bb) in FIG. 8B, during the read operation, the bit lines Bt, Bt,
Bit lines bt, b connected to Bb and the sense amplifier
In FIG. 8, the switching elements ST and SB between the points b and b are turned off.
The low-potential amplification by the sense amplifier SN is performed earlier than the write operation shown in FIG.

That is, in FIG. 8, the signal Fc is the gate signal of the switch elements ST and SB shown in FIG. 7, and bb is the potential of the bit line to which the sense amplifiers SP and SN are connected. In the read operation shown in FIG. 8B, the memory cell signal is output by setting the word line W to the high potential Vch, and the bit line is amplified to the high potential Bt by the sense amplifier SP of FIG. After that, the signal Fc is changed to Low.
Level, the bit line Bt and the bit line bt, and
The bit line Bb and the bit line bb are separated, and low-potential amplification (bb) is performed by the sense amplifier SN. This allows
Since the bit line can be selected earlier by the column selection signal Ys, the reading of the stored information can be accelerated.

The low-potential rewriting is performed by setting the word line to the intermediate potential Vc and then setting the signal Fc to the high level, and setting the bit line Bt, the bit line bt, and the bit line Bt.
b and the bit line bb are connected, the bit line Bb has a low potential, and a low potential is applied to the capacitor of the memory cell.
As described above, in the fourth embodiment, reading of stored information can be performed quickly without changing the period during which the potential of the word line is maintained in accordance with the operation mode of the semiconductor device. Also, since the load on the sense amplifier when amplifying to a low potential is small,
The time required for amplification can be shortened, and the reading of stored information can be accelerated.

As described above with reference to FIGS. 1 to 8, in the semiconductor device of this embodiment, the potential of the word line is switched in time series to a high potential, an intermediate potential, and a low potential, and the memory cell signal is switched. When amplifying to a high potential, the amplification is completed when the word line is at a high potential, and when amplifying to a low potential, the amplification is completed when the word line is at an intermediate potential. When writing storage information from outside the semiconductor device to the memory cell,
A high potential and an intermediate potential are output. When the word line is at a high potential, one of the output potentials is applied to a capacitor of the memory cell, and the other output potential is applied to a pair of bit lines. When the information to be written has a high potential, the potential is applied to the capacitor of the memory cell as it is. When the information to be written has a low potential, the intermediate potential is written once, and when the word line reaches the intermediate potential. To apply the voltage to the capacitor using the low potential amplification of the sense amplifier.

By doing so, the electric field applied to the gate and the source or drain of the charge transfer MOS transistor can be made smaller than before, and the destruction and deterioration of the gate oxide film can be suppressed. Further, since the potential of the word line is sufficiently higher than the writing potential, a sufficient potential can be applied to the capacitor of the memory cell without lowering the writing potential. Therefore, failures and malfunctions of the semiconductor device can be reduced, and the reliability of a system including such a semiconductor device can be improved.

The present invention is not limited to the embodiment described with reference to FIGS. 1 to 8 and can be variously modified without departing from the gist thereof. For example, in the present embodiment, the semiconductor device as a single semiconductor memory device has been described as an example, but the semiconductor memory device and the central processing unit (C
The present invention is also applicable to a semiconductor device in which a PU (Central Processing Unit) is mounted. In this case, the reliability of the semiconductor device can be improved. In FIG. 1, the low potential writing by the sense amplifier SN is performed using the signal FS. However, the output (node N2) of the switching circuit SW is connected to the inverter IP of the write control circuit WRC and the NAND circuit NAN. The respective input terminals may be connected via an inverter and a delay circuit, and the output of the switching circuit SW may be used.

[0058]

According to the present invention, even if the word line potential is increased in order to apply a sufficient write potential to the capacitor of the memory cell, the withstand voltage of the gate oxide film can be guaranteed, and high reliability without malfunction and failure can be ensured. High integration of various semiconductor devices is possible.

[Brief description of the drawings]

FIG. 1 shows a first configuration of a semiconductor device according to the present invention.
FIG. 3 is a circuit diagram showing an example of the embodiment.

FIG. 2 is an explanatory diagram showing an operation example according to the present invention of the semiconductor device in FIG. 1;

FIG. 3 shows a second configuration of the semiconductor device according to the present invention;
FIG. 3 is a circuit diagram showing an example of the embodiment.

FIG. 4 is an explanatory diagram showing an operation example according to the present invention of the semiconductor device in FIG. 3;

FIG. 5 shows a third configuration of the semiconductor device according to the present invention;
FIG. 3 is a circuit diagram showing an example of the embodiment.

FIG. 6 is an explanatory diagram showing an operation example according to the present invention of the semiconductor device in FIG. 5;

FIG. 7 shows the fourth configuration of the semiconductor device according to the present invention;
FIG. 3 is a circuit diagram showing an example of the embodiment.

FIG. 8 is an explanatory diagram showing an operation example according to the present invention of the semiconductor device in FIG. 7;

[Explanation of symbols]

A0-An: array, a0-a3, ax0-axn: address, Bb, Bt: bit line, BT: switch control circuit, C0-Cn: capacitor, CN, CP: common source line, DC0-DC3: delay circuit, Di: input data,
DN: NMOS transistor, Do: output data, F
c, FN, FP, Fs: signal, Fw: word line drive signal, IOb, IOt: input / output line, I1, I2, IN, I
P, IS0, IS1, IW1, IW2: Inverter, I
w: output circuit, LC: latch circuit, MA: main amplifier, M0 to Mn: memory cell, MWb, MWt: output signal, N0 to Nn: node, NA, NAN, NT1: NA
ND gate, NS, NW0, NWb, NWt: NMOS
Transistor, OS: potential holding time control circuit, PC: precharge circuit, PL: plate line, Pcc, Phh,
PS, PW, PW0: PMOS transistor, R: signal, / RAS: row address strobe signal, SC: switching circuit, SN: sense amplifier (for low potential amplification),
SP: sense amplifier (for high-potential amplification), Sb, St: transfer MOS transistor, SB, ST: switch element, SW: switching circuit, SW1, SW2: switch, SWD: sub-word driver, TC: timing circuit, Vc: intermediate Potential, Vch: high potential, VH: high potential,
VL: low potential, Vp: precharge level, VP: intermediate potential, VPL: plate voltage source, VR: plate voltage source, Vs: memory cell signal, W, / W: signal, / WE:
Write enable signal, W0-Wn: word line, WC:
Write circuit, WD, WDC: word driver, XD,
XDEC: row decoder, Xp: precharge signal, YS
0 to YSn: column selection line, Ys: column selection signal.

 ──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Ken Sakata 1-280 Higashi-Koikekubo, Kokubunji-shi, Tokyo Inside the Central Research Laboratory of Hitachi, Ltd. Inside the Central Research Laboratory

Claims (9)

[Claims] 1. A plurality of bit line pairs and a plurality of word lines arranged in a matrix, arranged at intersections of the word lines and the bit lines, a MOS transistor for charge transfer, and a MOS transistor for information storage. A semiconductor device having at least a memory cell comprising a capacitor and a sense amplifier connected between the pair of bit lines for reading and writing information stored in the memory cell, wherein the potential of the word line is set to a high potential. ,
A word line potential control means for switching to an intermediate potential and a low potential in a time series manner; and setting the high potential storage information to the memory cell when the word line potential control means sets the word line to a high potential. A semiconductor device comprising: a write control means for performing writing and writing the low-potential storage information to the memory cell when the word line potential control means sets the intermediate potential of the word line. apparatus. 2. The semiconductor device according to claim 1, wherein
The sense amplifier includes a first sense amplifier that amplifies a high-potential memory cell signal output from the memory cell and a second sense amplifier that amplifies a low-potential memory cell signal output from the memory cell. The write control means drives and controls the first and second sense amplifiers, and sets the memory by the first sense amplifier during the high potential setting of the word line by the word line potential control means. The amplifying operation of the cell signal is completed, and the amplifying operation of the memory cell signal by the second sense amplifier is completed while the intermediate potential of the word line is being set by the word line potential control means. Semiconductor device. 3. The semiconductor device according to claim 1, wherein said word line potential control means detects a rise and a fall of a row address strobe signal; A semiconductor device comprising: at least a potential switching unit that switches and connects the word line to either a high-potential power supply or an intermediate-potential power supply based on a detection result of the / RAS detection unit. 4. The semiconductor device according to claim 3, wherein
The write control means has at least a switching detection means for detecting a switching operation of the connection destination of the word line by the potential switching means, and at least the low-potential storage information corresponding to a detection result of the switching detection means. A writing control to said memory cell. 5. The semiconductor device according to claim 1, wherein said word line potential control means includes: a delay means for delaying transmission of a signal R generated in advance for a predetermined time; NAN of the previously generated signal R input and the signal R input via the delay means
A NAND gate for performing a D operation, and potential switching means for switching the word line to either a high-potential power supply or an intermediate-potential power supply based on an output of the NAND gate, and connecting the word line to a high potential power supply or an intermediate potential power supply. A semiconductor device characterized by switching to and connecting to an intermediate potential power supply after a predetermined time has elapsed by the delay means after connection to the potential power supply. 6. The semiconductor device according to claim 1, wherein a high potential VH and an intermediate potential Vp are generated at the time of inputting information from outside the semiconductor device. If the potential is high, the high potential VH is output to the bit line to which the memory cell for storing the information is connected, and the intermediate potential Vp is output to the pair of bit lines. External information writing means for outputting an intermediate potential Vp to a bit line to which a memory cell for storing information is connected and a high potential VH to a pair of bit lines is provided. If low potential information is input from outside the semiconductor device, When the intermediate potential of the word line to which the memory cell is connected is set by the word line potential control means, the sense amplifier is activated to amplify the intermediate potential Vp to a low potential and apply the amplified potential to the memory cell. A semiconductor device characterized by the above-mentioned. 7. The semiconductor device according to claim 1, wherein a period during which the word line is maintained at a high potential when information is output to the outside of the semiconductor device is defined as:
When the information is input from outside the semiconductor device,
A potential maintaining time control means for setting a period shorter than a period for maintaining a high potential of the gate line. 8. The semiconductor device according to claim 7, wherein
The potential maintaining time control means includes a / WE detection means for detecting a write enable signal, and when the detection result of the write enable signal by the / WE detection means indicates a read operation, the potential maintenance time control means changes from the high potential of the word line to the intermediate potential. A semiconductor device comprising: timing control means for making a switching timing to a potential earlier. 9. The semiconductor device according to claim 7, wherein
The potential maintaining time control means includes switching means for controlling connection between the memory cell and the sense amplifier in each of the bit line pairs, and termination of high potential amplification by the sense amplifier when outputting information to the outside of the semiconductor device. At that point,
At least a switch control means for making the switching means non-conductive, after disconnecting the connection between the memory cell and the sense amplifier by the switch control means of the potential maintaining time control means, A semiconductor device which performs amplification and outputs information to the outside of the semiconductor device.